arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/l3_2xxx.h>
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "wd_timer.h"
  30
  31 /*
  32  * OMAP2430 hardware module integration data
  33  *
  34  * ALl of the data in this section should be autogeneratable from the
  35  * TI hardware database or other technical documentation.  Data that
  36  * is driver-specific or driver-kernel integration-specific belongs
  37  * elsewhere.
  38  */
  39
  40 static struct omap_hwmod omap2430_mpu_hwmod;
  41 static struct omap_hwmod omap2430_iva_hwmod;
  42 static struct omap_hwmod omap2430_l3_main_hwmod;
  43 static struct omap_hwmod omap2430_l4_core_hwmod;
  44 static struct omap_hwmod omap2430_dss_core_hwmod;
  45 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  46 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  47 static struct omap_hwmod omap2430_dss_venc_hwmod;
  48 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  49 static struct omap_hwmod omap2430_gpio1_hwmod;
  50 static struct omap_hwmod omap2430_gpio2_hwmod;
  51 static struct omap_hwmod omap2430_gpio3_hwmod;
  52 static struct omap_hwmod omap2430_gpio4_hwmod;
  53 static struct omap_hwmod omap2430_gpio5_hwmod;
  54 static struct omap_hwmod omap2430_dma_system_hwmod;
  55 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  56 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  60 static struct omap_hwmod omap2430_mcspi1_hwmod;
  61 static struct omap_hwmod omap2430_mcspi2_hwmod;
  62 static struct omap_hwmod omap2430_mcspi3_hwmod;
  63
  64 /* L3 -> L4_CORE interface */
  65 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  66         .master = &omap2430_l3_main_hwmod,
  67         .slave  = &omap2430_l4_core_hwmod,
  68         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  69 };
  70
  71 /* MPU -> L3 interface */
  72 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  73         .master = &omap2430_mpu_hwmod,
  74         .slave  = &omap2430_l3_main_hwmod,
  75         .user   = OCP_USER_MPU,
  76 };
  77
  78 /* Slave interfaces on the L3 interconnect */
  79 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  80         &omap2430_mpu__l3_main,
  81 };
  82
  83 /* DSS -> l3 */
  84 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  85         .master         = &omap2430_dss_core_hwmod,
  86         .slave          = &omap2430_l3_main_hwmod,
  87         .fw = {
  88                 .omap2 = {
  89                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  90                         .flags  = OMAP_FIREWALL_L3,
  91                 }
  92         },
  93         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  94 };
  95
  96 /* Master interfaces on the L3 interconnect */
  97 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
  98         &omap2430_l3_main__l4_core,
  99 };
 100
 101 /* L3 */
 102 static struct omap_hwmod omap2430_l3_main_hwmod = {
 103         .name           = "l3_main",
 104         .class          = &l3_hwmod_class,
 105         .masters        = omap2430_l3_main_masters,
 106         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 107         .slaves         = omap2430_l3_main_slaves,
 108         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 109         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 110         .flags          = HWMOD_NO_IDLEST,
 111 };
 112
 113 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 114 static struct omap_hwmod omap2430_uart1_hwmod;
 115 static struct omap_hwmod omap2430_uart2_hwmod;
 116 static struct omap_hwmod omap2430_uart3_hwmod;
 117 static struct omap_hwmod omap2430_i2c1_hwmod;
 118 static struct omap_hwmod omap2430_i2c2_hwmod;
 119
 120 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 121
 122 /* l3_core -> usbhsotg  interface */
 123 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 124         .master         = &omap2430_usbhsotg_hwmod,
 125         .slave          = &omap2430_l3_main_hwmod,
 126         .clk            = "core_l3_ck",
 127         .user           = OCP_USER_MPU,
 128 };
 129
 130 /* I2C IP block address space length (in bytes) */
 131 #define OMAP2_I2C_AS_LEN                128
 132
 133 /* L4 CORE -> I2C1 interface */
 134 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
 135         {
 136                 .pa_start       = 0x48070000,
 137                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 138                 .flags          = ADDR_TYPE_RT,
 139         },
 140 };
 141
 142 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 143         .master         = &omap2430_l4_core_hwmod,
 144         .slave          = &omap2430_i2c1_hwmod,
 145         .clk            = "i2c1_ick",
 146         .addr           = omap2430_i2c1_addr_space,
 147         .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
 148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 149 };
 150
 151 /* L4 CORE -> I2C2 interface */
 152 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 153         {
 154                 .pa_start       = 0x48072000,
 155                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 156                 .flags          = ADDR_TYPE_RT,
 157         },
 158 };
 159
 160 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 161         .master         = &omap2430_l4_core_hwmod,
 162         .slave          = &omap2430_i2c2_hwmod,
 163         .clk            = "i2c2_ick",
 164         .addr           = omap2430_i2c2_addr_space,
 165         .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
 166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 167 };
 168
 169 /* L4_CORE -> L4_WKUP interface */
 170 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 171         .master = &omap2430_l4_core_hwmod,
 172         .slave  = &omap2430_l4_wkup_hwmod,
 173         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 174 };
 175
 176 /* L4 CORE -> UART1 interface */
 177 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 178         {
 179                 .pa_start       = OMAP2_UART1_BASE,
 180                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 181                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 182         },
 183 };
 184
 185 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 186         .master         = &omap2430_l4_core_hwmod,
 187         .slave          = &omap2430_uart1_hwmod,
 188         .clk            = "uart1_ick",
 189         .addr           = omap2430_uart1_addr_space,
 190         .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
 191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 192 };
 193
 194 /* L4 CORE -> UART2 interface */
 195 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 196         {
 197                 .pa_start       = OMAP2_UART2_BASE,
 198                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 199                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 200         },
 201 };
 202
 203 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 204         .master         = &omap2430_l4_core_hwmod,
 205         .slave          = &omap2430_uart2_hwmod,
 206         .clk            = "uart2_ick",
 207         .addr           = omap2430_uart2_addr_space,
 208         .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
 209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 210 };
 211
 212 /* L4 PER -> UART3 interface */
 213 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 214         {
 215                 .pa_start       = OMAP2_UART3_BASE,
 216                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 217                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 218         },
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 222         .master         = &omap2430_l4_core_hwmod,
 223         .slave          = &omap2430_uart3_hwmod,
 224         .clk            = "uart3_ick",
 225         .addr           = omap2430_uart3_addr_space,
 226         .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228 };
 229
 230 /*
 231 * usbhsotg interface data
 232 */
 233 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 234         {
 235                 .pa_start       = OMAP243X_HS_BASE,
 236                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 237                 .flags          = ADDR_TYPE_RT
 238         },
 239 };
 240
 241 /*  l4_core ->usbhsotg  interface */
 242 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 243         .master         = &omap2430_l4_core_hwmod,
 244         .slave          = &omap2430_usbhsotg_hwmod,
 245         .clk            = "usb_l4_ick",
 246         .addr           = omap2430_usbhsotg_addrs,
 247         .addr_cnt       = ARRAY_SIZE(omap2430_usbhsotg_addrs),
 248         .user           = OCP_USER_MPU,
 249 };
 250
 251 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 252         &omap2430_usbhsotg__l3,
 253 };
 254
 255 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 256         &omap2430_l4_core__usbhsotg,
 257 };
 258
 259 /* Slave interfaces on the L4_CORE interconnect */
 260 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 261         &omap2430_l3_main__l4_core,
 262 };
 263
 264 /* Master interfaces on the L4_CORE interconnect */
 265 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 266         &omap2430_l4_core__l4_wkup,
 267 };
 268
 269 /* L4 CORE */
 270 static struct omap_hwmod omap2430_l4_core_hwmod = {
 271         .name           = "l4_core",
 272         .class          = &l4_hwmod_class,
 273         .masters        = omap2430_l4_core_masters,
 274         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 275         .slaves         = omap2430_l4_core_slaves,
 276         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 277         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 278         .flags          = HWMOD_NO_IDLEST,
 279 };
 280
 281 /* Slave interfaces on the L4_WKUP interconnect */
 282 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 283         &omap2430_l4_core__l4_wkup,
 284         &omap2_l4_core__uart1,
 285         &omap2_l4_core__uart2,
 286         &omap2_l4_core__uart3,
 287 };
 288
 289 /* Master interfaces on the L4_WKUP interconnect */
 290 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 291 };
 292
 293 /* l4 core -> mcspi1 interface */
 294 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
 295         {
 296                 .pa_start       = 0x48098000,
 297                 .pa_end         = 0x480980ff,
 298                 .flags          = ADDR_TYPE_RT,
 299         },
 300 };
 301
 302 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 303         .master         = &omap2430_l4_core_hwmod,
 304         .slave          = &omap2430_mcspi1_hwmod,
 305         .clk            = "mcspi1_ick",
 306         .addr           = omap2430_mcspi1_addr_space,
 307         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi1_addr_space),
 308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 309 };
 310
 311 /* l4 core -> mcspi2 interface */
 312 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
 313         {
 314                 .pa_start       = 0x4809a000,
 315                 .pa_end         = 0x4809a0ff,
 316                 .flags          = ADDR_TYPE_RT,
 317         },
 318 };
 319
 320 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 321         .master         = &omap2430_l4_core_hwmod,
 322         .slave          = &omap2430_mcspi2_hwmod,
 323         .clk            = "mcspi2_ick",
 324         .addr           = omap2430_mcspi2_addr_space,
 325         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi2_addr_space),
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* l4 core -> mcspi3 interface */
 330 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
 331         {
 332                 .pa_start       = 0x480b8000,
 333                 .pa_end         = 0x480b80ff,
 334                 .flags          = ADDR_TYPE_RT,
 335         },
 336 };
 337
 338 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 339         .master         = &omap2430_l4_core_hwmod,
 340         .slave          = &omap2430_mcspi3_hwmod,
 341         .clk            = "mcspi3_ick",
 342         .addr           = omap2430_mcspi3_addr_space,
 343         .addr_cnt       = ARRAY_SIZE(omap2430_mcspi3_addr_space),
 344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 345 };
 346
 347 /* L4 WKUP */
 348 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 349         .name           = "l4_wkup",
 350         .class          = &l4_hwmod_class,
 351         .masters        = omap2430_l4_wkup_masters,
 352         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 353         .slaves         = omap2430_l4_wkup_slaves,
 354         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 355         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 356         .flags          = HWMOD_NO_IDLEST,
 357 };
 358
 359 /* Master interfaces on the MPU device */
 360 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 361         &omap2430_mpu__l3_main,
 362 };
 363
 364 /* MPU */
 365 static struct omap_hwmod omap2430_mpu_hwmod = {
 366         .name           = "mpu",
 367         .class          = &mpu_hwmod_class,
 368         .main_clk       = "mpu_ck",
 369         .masters        = omap2430_mpu_masters,
 370         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 371         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 372 };
 373
 374 /*
 375  * IVA2_1 interface data
 376  */
 377
 378 /* IVA2 <- L3 interface */
 379 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 380         .master         = &omap2430_l3_main_hwmod,
 381         .slave          = &omap2430_iva_hwmod,
 382         .clk            = "dsp_fck",
 383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 384 };
 385
 386 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 387         &omap2430_l3__iva,
 388 };
 389
 390 /*
 391  * IVA2 (IVA2)
 392  */
 393
 394 static struct omap_hwmod omap2430_iva_hwmod = {
 395         .name           = "iva",
 396         .class          = &iva_hwmod_class,
 397         .masters        = omap2430_iva_masters,
 398         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 399         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 400 };
 401
 402 /* l4_wkup -> wd_timer2 */
 403 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 404         {
 405                 .pa_start       = 0x49016000,
 406                 .pa_end         = 0x4901607f,
 407                 .flags          = ADDR_TYPE_RT
 408         },
 409 };
 410
 411 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 412         .master         = &omap2430_l4_wkup_hwmod,
 413         .slave          = &omap2430_wd_timer2_hwmod,
 414         .clk            = "mpu_wdt_ick",
 415         .addr           = omap2430_wd_timer2_addrs,
 416         .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
 417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 418 };
 419
 420 /*
 421  * 'wd_timer' class
 422  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 423  * overflow condition
 424  */
 425
 426 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 427         .rev_offs       = 0x0,
 428         .sysc_offs      = 0x0010,
 429         .syss_offs      = 0x0014,
 430         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 431                            SYSC_HAS_AUTOIDLE),
 432         .sysc_fields    = &omap_hwmod_sysc_type1,
 433 };
 434
 435 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
 436         .name           = "wd_timer",
 437         .sysc           = &omap2430_wd_timer_sysc,
 438         .pre_shutdown   = &omap2_wd_timer_disable
 439 };
 440
 441 /* wd_timer2 */
 442 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 443         &omap2430_l4_wkup__wd_timer2,
 444 };
 445
 446 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 447         .name           = "wd_timer2",
 448         .class          = &omap2430_wd_timer_hwmod_class,
 449         .main_clk       = "mpu_wdt_fck",
 450         .prcm           = {
 451                 .omap2 = {
 452                         .prcm_reg_id = 1,
 453                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 454                         .module_offs = WKUP_MOD,
 455                         .idlest_reg_id = 1,
 456                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 457                 },
 458         },
 459         .slaves         = omap2430_wd_timer2_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 461         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 462 };
 463
 464 /* UART */
 465
 466 static struct omap_hwmod_class_sysconfig uart_sysc = {
 467         .rev_offs       = 0x50,
 468         .sysc_offs      = 0x54,
 469         .syss_offs      = 0x58,
 470         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 471                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 472                            SYSC_HAS_AUTOIDLE),
 473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 474         .sysc_fields    = &omap_hwmod_sysc_type1,
 475 };
 476
 477 static struct omap_hwmod_class uart_class = {
 478         .name = "uart",
 479         .sysc = &uart_sysc,
 480 };
 481
 482 /* UART1 */
 483
 484 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 485         { .irq = INT_24XX_UART1_IRQ, },
 486 };
 487
 488 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 489         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 490         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 491 };
 492
 493 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 494         &omap2_l4_core__uart1,
 495 };
 496
 497 static struct omap_hwmod omap2430_uart1_hwmod = {
 498         .name           = "uart1",
 499         .mpu_irqs       = uart1_mpu_irqs,
 500         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 501         .sdma_reqs      = uart1_sdma_reqs,
 502         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 503         .main_clk       = "uart1_fck",
 504         .prcm           = {
 505                 .omap2 = {
 506                         .module_offs = CORE_MOD,
 507                         .prcm_reg_id = 1,
 508                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 509                         .idlest_reg_id = 1,
 510                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 511                 },
 512         },
 513         .slaves         = omap2430_uart1_slaves,
 514         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 515         .class          = &uart_class,
 516         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 517 };
 518
 519 /* UART2 */
 520
 521 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 522         { .irq = INT_24XX_UART2_IRQ, },
 523 };
 524
 525 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 526         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 527         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 528 };
 529
 530 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 531         &omap2_l4_core__uart2,
 532 };
 533
 534 static struct omap_hwmod omap2430_uart2_hwmod = {
 535         .name           = "uart2",
 536         .mpu_irqs       = uart2_mpu_irqs,
 537         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 538         .sdma_reqs      = uart2_sdma_reqs,
 539         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 540         .main_clk       = "uart2_fck",
 541         .prcm           = {
 542                 .omap2 = {
 543                         .module_offs = CORE_MOD,
 544                         .prcm_reg_id = 1,
 545                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 546                         .idlest_reg_id = 1,
 547                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 548                 },
 549         },
 550         .slaves         = omap2430_uart2_slaves,
 551         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
 552         .class          = &uart_class,
 553         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 554 };
 555
 556 /* UART3 */
 557
 558 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 559         { .irq = INT_24XX_UART3_IRQ, },
 560 };
 561
 562 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 563         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 564         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 565 };
 566
 567 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
 568         &omap2_l4_core__uart3,
 569 };
 570
 571 static struct omap_hwmod omap2430_uart3_hwmod = {
 572         .name           = "uart3",
 573         .mpu_irqs       = uart3_mpu_irqs,
 574         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 575         .sdma_reqs      = uart3_sdma_reqs,
 576         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 577         .main_clk       = "uart3_fck",
 578         .prcm           = {
 579                 .omap2 = {
 580                         .module_offs = CORE_MOD,
 581                         .prcm_reg_id = 2,
 582                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 583                         .idlest_reg_id = 2,
 584                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 585                 },
 586         },
 587         .slaves         = omap2430_uart3_slaves,
 588         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
 589         .class          = &uart_class,
 590         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 591 };
 592
 593 /*
 594  * 'dss' class
 595  * display sub-system
 596  */
 597
 598 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
 599         .rev_offs       = 0x0000,
 600         .sysc_offs      = 0x0010,
 601         .syss_offs      = 0x0014,
 602         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 603         .sysc_fields    = &omap_hwmod_sysc_type1,
 604 };
 605
 606 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
 607         .name = "dss",
 608         .sysc = &omap2430_dss_sysc,
 609 };
 610
 611 /* dss */
 612 static struct omap_hwmod_irq_info omap2430_dss_irqs[] = {
 613         { .irq = 25 },
 614 };
 615 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
 616         { .name = "dispc", .dma_req = 5 },
 617 };
 618
 619 /* dss */
 620 /* dss master ports */
 621 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
 622         &omap2430_dss__l3,
 623 };
 624
 625 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
 626         {
 627                 .pa_start       = 0x48050000,
 628                 .pa_end         = 0x480503FF,
 629                 .flags          = ADDR_TYPE_RT
 630         },
 631 };
 632
 633 /* l4_core -> dss */
 634 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
 635         .master         = &omap2430_l4_core_hwmod,
 636         .slave          = &omap2430_dss_core_hwmod,
 637         .clk            = "dss_ick",
 638         .addr           = omap2430_dss_addrs,
 639         .addr_cnt       = ARRAY_SIZE(omap2430_dss_addrs),
 640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 641 };
 642
 643 /* dss slave ports */
 644 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 645         &omap2430_l4_core__dss,
 646 };
 647
 648 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 649         { .role = "tv_clk", .clk = "dss_54m_fck" },
 650         { .role = "sys_clk", .clk = "dss2_fck" },
 651 };
 652
 653 static struct omap_hwmod omap2430_dss_core_hwmod = {
 654         .name           = "dss_core",
 655         .class          = &omap2430_dss_hwmod_class,
 656         .main_clk       = "dss1_fck", /* instead of dss_fck */
 657         .mpu_irqs       = omap2430_dss_irqs,
 658         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dss_irqs),
 659         .sdma_reqs      = omap2430_dss_sdma_chs,
 660         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_dss_sdma_chs),
 661         .prcm           = {
 662                 .omap2 = {
 663                         .prcm_reg_id = 1,
 664                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 665                         .module_offs = CORE_MOD,
 666                         .idlest_reg_id = 1,
 667                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 668                 },
 669         },
 670         .opt_clks       = dss_opt_clks,
 671         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 672         .slaves         = omap2430_dss_slaves,
 673         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
 674         .masters        = omap2430_dss_masters,
 675         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
 676         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 677         .flags          = HWMOD_NO_IDLEST,
 678 };
 679
 680 /*
 681  * 'dispc' class
 682  * display controller
 683  */
 684
 685 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
 686         .rev_offs       = 0x0000,
 687         .sysc_offs      = 0x0010,
 688         .syss_offs      = 0x0014,
 689         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 690                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
 697         .name = "dispc",
 698         .sysc = &omap2430_dispc_sysc,
 699 };
 700
 701 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
 702         {
 703                 .pa_start       = 0x48050400,
 704                 .pa_end         = 0x480507FF,
 705                 .flags          = ADDR_TYPE_RT
 706         },
 707 };
 708
 709 /* l4_core -> dss_dispc */
 710 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
 711         .master         = &omap2430_l4_core_hwmod,
 712         .slave          = &omap2430_dss_dispc_hwmod,
 713         .clk            = "dss_ick",
 714         .addr           = omap2430_dss_dispc_addrs,
 715         .addr_cnt       = ARRAY_SIZE(omap2430_dss_dispc_addrs),
 716         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 717 };
 718
 719 /* dss_dispc slave ports */
 720 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
 721         &omap2430_l4_core__dss_dispc,
 722 };
 723
 724 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
 725         .name           = "dss_dispc",
 726         .class          = &omap2430_dispc_hwmod_class,
 727         .main_clk       = "dss1_fck",
 728         .prcm           = {
 729                 .omap2 = {
 730                         .prcm_reg_id = 1,
 731                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 732                         .module_offs = CORE_MOD,
 733                         .idlest_reg_id = 1,
 734                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 735                 },
 736         },
 737         .slaves         = omap2430_dss_dispc_slaves,
 738         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
 739         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 740         .flags          = HWMOD_NO_IDLEST,
 741 };
 742
 743 /*
 744  * 'rfbi' class
 745  * remote frame buffer interface
 746  */
 747
 748 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
 749         .rev_offs       = 0x0000,
 750         .sysc_offs      = 0x0010,
 751         .syss_offs      = 0x0014,
 752         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 753                            SYSC_HAS_AUTOIDLE),
 754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 755         .sysc_fields    = &omap_hwmod_sysc_type1,
 756 };
 757
 758 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
 759         .name = "rfbi",
 760         .sysc = &omap2430_rfbi_sysc,
 761 };
 762
 763 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
 764         {
 765                 .pa_start       = 0x48050800,
 766                 .pa_end         = 0x48050BFF,
 767                 .flags          = ADDR_TYPE_RT
 768         },
 769 };
 770
 771 /* l4_core -> dss_rfbi */
 772 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
 773         .master         = &omap2430_l4_core_hwmod,
 774         .slave          = &omap2430_dss_rfbi_hwmod,
 775         .clk            = "dss_ick",
 776         .addr           = omap2430_dss_rfbi_addrs,
 777         .addr_cnt       = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
 778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 779 };
 780
 781 /* dss_rfbi slave ports */
 782 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
 783         &omap2430_l4_core__dss_rfbi,
 784 };
 785
 786 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 787         .name           = "dss_rfbi",
 788         .class          = &omap2430_rfbi_hwmod_class,
 789         .main_clk       = "dss1_fck",
 790         .prcm           = {
 791                 .omap2 = {
 792                         .prcm_reg_id = 1,
 793                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 794                         .module_offs = CORE_MOD,
 795                 },
 796         },
 797         .slaves         = omap2430_dss_rfbi_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
 799         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 800         .flags          = HWMOD_NO_IDLEST,
 801 };
 802
 803 /*
 804  * 'venc' class
 805  * video encoder
 806  */
 807
 808 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
 809         .name = "venc",
 810 };
 811
 812 /* dss_venc */
 813 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
 814         {
 815                 .pa_start       = 0x48050C00,
 816                 .pa_end         = 0x48050FFF,
 817                 .flags          = ADDR_TYPE_RT
 818         },
 819 };
 820
 821 /* l4_core -> dss_venc */
 822 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
 823         .master         = &omap2430_l4_core_hwmod,
 824         .slave          = &omap2430_dss_venc_hwmod,
 825         .clk            = "dss_54m_fck",
 826         .addr           = omap2430_dss_venc_addrs,
 827         .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
 828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 829 };
 830
 831 /* dss_venc slave ports */
 832 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
 833         &omap2430_l4_core__dss_venc,
 834 };
 835
 836 static struct omap_hwmod omap2430_dss_venc_hwmod = {
 837         .name           = "dss_venc",
 838         .class          = &omap2430_venc_hwmod_class,
 839         .main_clk       = "dss1_fck",
 840         .prcm           = {
 841                 .omap2 = {
 842                         .prcm_reg_id = 1,
 843                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 844                         .module_offs = CORE_MOD,
 845                 },
 846         },
 847         .slaves         = omap2430_dss_venc_slaves,
 848         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
 849         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 850         .flags          = HWMOD_NO_IDLEST,
 851 };
 852
 853 /* I2C common */
 854 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 855         .rev_offs       = 0x00,
 856         .sysc_offs      = 0x20,
 857         .syss_offs      = 0x10,
 858         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 859         .sysc_fields    = &omap_hwmod_sysc_type1,
 860 };
 861
 862 static struct omap_hwmod_class i2c_class = {
 863         .name           = "i2c",
 864         .sysc           = &i2c_sysc,
 865 };
 866
 867 static struct omap_i2c_dev_attr i2c_dev_attr = {
 868         .fifo_depth     = 8, /* bytes */
 869 };
 870
 871 /* I2C1 */
 872
 873 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 874         { .irq = INT_24XX_I2C1_IRQ, },
 875 };
 876
 877 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
 878         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 879         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 880 };
 881
 882 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
 883         &omap2430_l4_core__i2c1,
 884 };
 885
 886 static struct omap_hwmod omap2430_i2c1_hwmod = {
 887         .name           = "i2c1",
 888         .mpu_irqs       = i2c1_mpu_irqs,
 889         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
 890         .sdma_reqs      = i2c1_sdma_reqs,
 891         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
 892         .main_clk       = "i2chs1_fck",
 893         .prcm           = {
 894                 .omap2 = {
 895                         /*
 896                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
 897                          * I2CHS IP's do not follow the usual pattern.
 898                          * prcm_reg_id alone cannot be used to program
 899                          * the iclk and fclk. Needs to be handled using
 900                          * additonal flags when clk handling is moved
 901                          * to hwmod framework.
 902                          */
 903                         .module_offs = CORE_MOD,
 904                         .prcm_reg_id = 1,
 905                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
 906                         .idlest_reg_id = 1,
 907                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
 908                 },
 909         },
 910         .slaves         = omap2430_i2c1_slaves,
 911         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
 912         .class          = &i2c_class,
 913         .dev_attr       = &i2c_dev_attr,
 914         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 915 };
 916
 917 /* I2C2 */
 918
 919 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 920         { .irq = INT_24XX_I2C2_IRQ, },
 921 };
 922
 923 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 924         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 925         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 926 };
 927
 928 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
 929         &omap2430_l4_core__i2c2,
 930 };
 931
 932 static struct omap_hwmod omap2430_i2c2_hwmod = {
 933         .name           = "i2c2",
 934         .mpu_irqs       = i2c2_mpu_irqs,
 935         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 936         .sdma_reqs      = i2c2_sdma_reqs,
 937         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 938         .main_clk       = "i2chs2_fck",
 939         .prcm           = {
 940                 .omap2 = {
 941                         .module_offs = CORE_MOD,
 942                         .prcm_reg_id = 1,
 943                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
 944                         .idlest_reg_id = 1,
 945                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
 946                 },
 947         },
 948         .slaves         = omap2430_i2c2_slaves,
 949         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
 950         .class          = &i2c_class,
 951         .dev_attr       = &i2c_dev_attr,
 952         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 953 };
 954
 955 /* l4_wkup -> gpio1 */
 956 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
 957         {
 958                 .pa_start       = 0x4900C000,
 959                 .pa_end         = 0x4900C1ff,
 960                 .flags          = ADDR_TYPE_RT
 961         },
 962 };
 963
 964 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
 965         .master         = &omap2430_l4_wkup_hwmod,
 966         .slave          = &omap2430_gpio1_hwmod,
 967         .clk            = "gpios_ick",
 968         .addr           = omap2430_gpio1_addr_space,
 969         .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
 970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 971 };
 972
 973 /* l4_wkup -> gpio2 */
 974 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
 975         {
 976                 .pa_start       = 0x4900E000,
 977                 .pa_end         = 0x4900E1ff,
 978                 .flags          = ADDR_TYPE_RT
 979         },
 980 };
 981
 982 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
 983         .master         = &omap2430_l4_wkup_hwmod,
 984         .slave          = &omap2430_gpio2_hwmod,
 985         .clk            = "gpios_ick",
 986         .addr           = omap2430_gpio2_addr_space,
 987         .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
 988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 989 };
 990
 991 /* l4_wkup -> gpio3 */
 992 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
 993         {
 994                 .pa_start       = 0x49010000,
 995                 .pa_end         = 0x490101ff,
 996                 .flags          = ADDR_TYPE_RT
 997         },
 998 };
 999
1000 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1001         .master         = &omap2430_l4_wkup_hwmod,
1002         .slave          = &omap2430_gpio3_hwmod,
1003         .clk            = "gpios_ick",
1004         .addr           = omap2430_gpio3_addr_space,
1005         .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
1006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1007 };
1008
1009 /* l4_wkup -> gpio4 */
1010 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1011         {
1012                 .pa_start       = 0x49012000,
1013                 .pa_end         = 0x490121ff,
1014                 .flags          = ADDR_TYPE_RT
1015         },
1016 };
1017
1018 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1019         .master         = &omap2430_l4_wkup_hwmod,
1020         .slave          = &omap2430_gpio4_hwmod,
1021         .clk            = "gpios_ick",
1022         .addr           = omap2430_gpio4_addr_space,
1023         .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
1024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1025 };
1026
1027 /* l4_core -> gpio5 */
1028 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1029         {
1030                 .pa_start       = 0x480B6000,
1031                 .pa_end         = 0x480B61ff,
1032                 .flags          = ADDR_TYPE_RT
1033         },
1034 };
1035
1036 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1037         .master         = &omap2430_l4_core_hwmod,
1038         .slave          = &omap2430_gpio5_hwmod,
1039         .clk            = "gpio5_ick",
1040         .addr           = omap2430_gpio5_addr_space,
1041         .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
1042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1043 };
1044
1045 /* gpio dev_attr */
1046 static struct omap_gpio_dev_attr gpio_dev_attr = {
1047         .bank_width = 32,
1048         .dbck_flag = false,
1049 };
1050
1051 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1052         .rev_offs       = 0x0000,
1053         .sysc_offs      = 0x0010,
1054         .syss_offs      = 0x0014,
1055         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1056                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1057         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1058         .sysc_fields    = &omap_hwmod_sysc_type1,
1059 };
1060
1061 /*
1062  * 'gpio' class
1063  * general purpose io module
1064  */
1065 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1066         .name = "gpio",
1067         .sysc = &omap243x_gpio_sysc,
1068         .rev = 0,
1069 };
1070
1071 /* gpio1 */
1072 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1073         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1074 };
1075
1076 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1077         &omap2430_l4_wkup__gpio1,
1078 };
1079
1080 static struct omap_hwmod omap2430_gpio1_hwmod = {
1081         .name           = "gpio1",
1082         .mpu_irqs       = omap243x_gpio1_irqs,
1083         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
1084         .main_clk       = "gpios_fck",
1085         .prcm           = {
1086                 .omap2 = {
1087                         .prcm_reg_id = 1,
1088                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1089                         .module_offs = WKUP_MOD,
1090                         .idlest_reg_id = 1,
1091                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1092                 },
1093         },
1094         .slaves         = omap2430_gpio1_slaves,
1095         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1096         .class          = &omap243x_gpio_hwmod_class,
1097         .dev_attr       = &gpio_dev_attr,
1098         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1099 };
1100
1101 /* gpio2 */
1102 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1103         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1104 };
1105
1106 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1107         &omap2430_l4_wkup__gpio2,
1108 };
1109
1110 static struct omap_hwmod omap2430_gpio2_hwmod = {
1111         .name           = "gpio2",
1112         .mpu_irqs       = omap243x_gpio2_irqs,
1113         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
1114         .main_clk       = "gpios_fck",
1115         .prcm           = {
1116                 .omap2 = {
1117                         .prcm_reg_id = 1,
1118                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1119                         .module_offs = WKUP_MOD,
1120                         .idlest_reg_id = 1,
1121                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1122                 },
1123         },
1124         .slaves         = omap2430_gpio2_slaves,
1125         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1126         .class          = &omap243x_gpio_hwmod_class,
1127         .dev_attr       = &gpio_dev_attr,
1128         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1129 };
1130
1131 /* gpio3 */
1132 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1133         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1134 };
1135
1136 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1137         &omap2430_l4_wkup__gpio3,
1138 };
1139
1140 static struct omap_hwmod omap2430_gpio3_hwmod = {
1141         .name           = "gpio3",
1142         .mpu_irqs       = omap243x_gpio3_irqs,
1143         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
1144         .main_clk       = "gpios_fck",
1145         .prcm           = {
1146                 .omap2 = {
1147                         .prcm_reg_id = 1,
1148                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1149                         .module_offs = WKUP_MOD,
1150                         .idlest_reg_id = 1,
1151                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1152                 },
1153         },
1154         .slaves         = omap2430_gpio3_slaves,
1155         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1156         .class          = &omap243x_gpio_hwmod_class,
1157         .dev_attr       = &gpio_dev_attr,
1158         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1159 };
1160
1161 /* gpio4 */
1162 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1163         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1164 };
1165
1166 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1167         &omap2430_l4_wkup__gpio4,
1168 };
1169
1170 static struct omap_hwmod omap2430_gpio4_hwmod = {
1171         .name           = "gpio4",
1172         .mpu_irqs       = omap243x_gpio4_irqs,
1173         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
1174         .main_clk       = "gpios_fck",
1175         .prcm           = {
1176                 .omap2 = {
1177                         .prcm_reg_id = 1,
1178                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1179                         .module_offs = WKUP_MOD,
1180                         .idlest_reg_id = 1,
1181                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1182                 },
1183         },
1184         .slaves         = omap2430_gpio4_slaves,
1185         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1186         .class          = &omap243x_gpio_hwmod_class,
1187         .dev_attr       = &gpio_dev_attr,
1188         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1189 };
1190
1191 /* gpio5 */
1192 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1193         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1194 };
1195
1196 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1197         &omap2430_l4_core__gpio5,
1198 };
1199
1200 static struct omap_hwmod omap2430_gpio5_hwmod = {
1201         .name           = "gpio5",
1202         .mpu_irqs       = omap243x_gpio5_irqs,
1203         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
1204         .main_clk       = "gpio5_fck",
1205         .prcm           = {
1206                 .omap2 = {
1207                         .prcm_reg_id = 2,
1208                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1209                         .module_offs = CORE_MOD,
1210                         .idlest_reg_id = 2,
1211                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1212                 },
1213         },
1214         .slaves         = omap2430_gpio5_slaves,
1215         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1216         .class          = &omap243x_gpio_hwmod_class,
1217         .dev_attr       = &gpio_dev_attr,
1218         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1219 };
1220
1221 /* dma_system */
1222 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1223         .rev_offs       = 0x0000,
1224         .sysc_offs      = 0x002c,
1225         .syss_offs      = 0x0028,
1226         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1227                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1228                            SYSC_HAS_AUTOIDLE),
1229         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1230         .sysc_fields    = &omap_hwmod_sysc_type1,
1231 };
1232
1233 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1234         .name = "dma",
1235         .sysc = &omap2430_dma_sysc,
1236 };
1237
1238 /* dma attributes */
1239 static struct omap_dma_dev_attr dma_dev_attr = {
1240         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1241                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1242         .lch_count = 32,
1243 };
1244
1245 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1246         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1247         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1248         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1249         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1250 };
1251
1252 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1253         {
1254                 .pa_start       = 0x48056000,
1255                 .pa_end         = 0x4a0560ff,
1256                 .flags          = ADDR_TYPE_RT
1257         },
1258 };
1259
1260 /* dma_system -> L3 */
1261 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1262         .master         = &omap2430_dma_system_hwmod,
1263         .slave          = &omap2430_l3_main_hwmod,
1264         .clk            = "core_l3_ck",
1265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1266 };
1267
1268 /* dma_system master ports */
1269 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1270         &omap2430_dma_system__l3,
1271 };
1272
1273 /* l4_core -> dma_system */
1274 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1275         .master         = &omap2430_l4_core_hwmod,
1276         .slave          = &omap2430_dma_system_hwmod,
1277         .clk            = "sdma_ick",
1278         .addr           = omap2430_dma_system_addrs,
1279         .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
1280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1281 };
1282
1283 /* dma_system slave ports */
1284 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1285         &omap2430_l4_core__dma_system,
1286 };
1287
1288 static struct omap_hwmod omap2430_dma_system_hwmod = {
1289         .name           = "dma",
1290         .class          = &omap2430_dma_hwmod_class,
1291         .mpu_irqs       = omap2430_dma_system_irqs,
1292         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
1293         .main_clk       = "core_l3_ck",
1294         .slaves         = omap2430_dma_system_slaves,
1295         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1296         .masters        = omap2430_dma_system_masters,
1297         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1298         .dev_attr       = &dma_dev_attr,
1299         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1300         .flags          = HWMOD_NO_IDLEST,
1301 };
1302
1303 /*
1304  * 'mailbox' class
1305  * mailbox module allowing communication between the on-chip processors
1306  * using a queued mailbox-interrupt mechanism.
1307  */
1308
1309 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1310         .rev_offs       = 0x000,
1311         .sysc_offs      = 0x010,
1312         .syss_offs      = 0x014,
1313         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1314                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1316         .sysc_fields    = &omap_hwmod_sysc_type1,
1317 };
1318
1319 static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1320         .name = "mailbox",
1321         .sysc = &omap2430_mailbox_sysc,
1322 };
1323
1324 /* mailbox */
1325 static struct omap_hwmod omap2430_mailbox_hwmod;
1326 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1327         { .irq = 26 },
1328 };
1329
1330 static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1331         {
1332                 .pa_start       = 0x48094000,
1333                 .pa_end         = 0x480941ff,
1334                 .flags          = ADDR_TYPE_RT,
1335         },
1336 };
1337
1338 /* l4_core -> mailbox */
1339 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1340         .master         = &omap2430_l4_core_hwmod,
1341         .slave          = &omap2430_mailbox_hwmod,
1342         .addr           = omap2430_mailbox_addrs,
1343         .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
1344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1345 };
1346
1347 /* mailbox slave ports */
1348 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1349         &omap2430_l4_core__mailbox,
1350 };
1351
1352 static struct omap_hwmod omap2430_mailbox_hwmod = {
1353         .name           = "mailbox",
1354         .class          = &omap2430_mailbox_hwmod_class,
1355         .mpu_irqs       = omap2430_mailbox_irqs,
1356         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
1357         .main_clk       = "mailboxes_ick",
1358         .prcm           = {
1359                 .omap2 = {
1360                         .prcm_reg_id = 1,
1361                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1362                         .module_offs = CORE_MOD,
1363                         .idlest_reg_id = 1,
1364                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1365                 },
1366         },
1367         .slaves         = omap2430_mailbox_slaves,
1368         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
1369         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1370 };
1371
1372 /*
1373  * 'mcspi' class
1374  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1375  * bus
1376  */
1377
1378 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
1379         .rev_offs       = 0x0000,
1380         .sysc_offs      = 0x0010,
1381         .syss_offs      = 0x0014,
1382         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1383                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1384                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386         .sysc_fields    = &omap_hwmod_sysc_type1,
1387 };
1388
1389 static struct omap_hwmod_class omap2430_mcspi_class = {
1390         .name = "mcspi",
1391         .sysc = &omap2430_mcspi_sysc,
1392         .rev = OMAP2_MCSPI_REV,
1393 };
1394
1395 /* mcspi1 */
1396 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
1397         { .irq = 65 },
1398 };
1399
1400 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
1401         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1402         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1403         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1404         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1405         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1406         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1407         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1408         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1409 };
1410
1411 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1412         &omap2430_l4_core__mcspi1,
1413 };
1414
1415 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1416         .num_chipselect = 4,
1417 };
1418
1419 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1420         .name           = "mcspi1_hwmod",
1421         .mpu_irqs       = omap2430_mcspi1_mpu_irqs,
1422         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
1423         .sdma_reqs      = omap2430_mcspi1_sdma_reqs,
1424         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
1425         .main_clk       = "mcspi1_fck",
1426         .prcm           = {
1427                 .omap2 = {
1428                         .module_offs = CORE_MOD,
1429                         .prcm_reg_id = 1,
1430                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1431                         .idlest_reg_id = 1,
1432                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1433                 },
1434         },
1435         .slaves         = omap2430_mcspi1_slaves,
1436         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1437         .class          = &omap2430_mcspi_class,
1438         .dev_attr       = &omap_mcspi1_dev_attr,
1439         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1440 };
1441
1442 /* mcspi2 */
1443 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
1444         { .irq = 66 },
1445 };
1446
1447 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
1448         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1449         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1450         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1451         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1452 };
1453
1454 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1455         &omap2430_l4_core__mcspi2,
1456 };
1457
1458 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1459         .num_chipselect = 2,
1460 };
1461
1462 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1463         .name           = "mcspi2_hwmod",
1464         .mpu_irqs       = omap2430_mcspi2_mpu_irqs,
1465         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
1466         .sdma_reqs      = omap2430_mcspi2_sdma_reqs,
1467         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
1468         .main_clk       = "mcspi2_fck",
1469         .prcm           = {
1470                 .omap2 = {
1471                         .module_offs = CORE_MOD,
1472                         .prcm_reg_id = 1,
1473                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1474                         .idlest_reg_id = 1,
1475                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1476                 },
1477         },
1478         .slaves         = omap2430_mcspi2_slaves,
1479         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
1480         .class          = &omap2430_mcspi_class,
1481         .dev_attr       = &omap_mcspi2_dev_attr,
1482         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1483 };
1484
1485 /* mcspi3 */
1486 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1487         { .irq = 91 },
1488 };
1489
1490 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1491         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1492         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1493         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1494         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1495 };
1496
1497 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1498         &omap2430_l4_core__mcspi3,
1499 };
1500
1501 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1502         .num_chipselect = 2,
1503 };
1504
1505 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1506         .name           = "mcspi3_hwmod",
1507         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
1508         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
1509         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
1510         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
1511         .main_clk       = "mcspi3_fck",
1512         .prcm           = {
1513                 .omap2 = {
1514                         .module_offs = CORE_MOD,
1515                         .prcm_reg_id = 2,
1516                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1517                         .idlest_reg_id = 2,
1518                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1519                 },
1520         },
1521         .slaves         = omap2430_mcspi3_slaves,
1522         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
1523         .class          = &omap2430_mcspi_class,
1524         .dev_attr       = &omap_mcspi3_dev_attr,
1525         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1526 };
1527
1528 /*
1529  * usbhsotg
1530  */
1531 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1532         .rev_offs       = 0x0400,
1533         .sysc_offs      = 0x0404,
1534         .syss_offs      = 0x0408,
1535         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1536                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1537                           SYSC_HAS_AUTOIDLE),
1538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1539                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1540         .sysc_fields    = &omap_hwmod_sysc_type1,
1541 };
1542
1543 static struct omap_hwmod_class usbotg_class = {
1544         .name = "usbotg",
1545         .sysc = &omap2430_usbhsotg_sysc,
1546 };
1547
1548 /* usb_otg_hs */
1549 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1550
1551         { .name = "mc", .irq = 92 },
1552         { .name = "dma", .irq = 93 },
1553 };
1554
1555 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1556         .name           = "usb_otg_hs",
1557         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
1558         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
1559         .main_clk       = "usbhs_ick",
1560         .prcm           = {
1561                 .omap2 = {
1562                         .prcm_reg_id = 1,
1563                         .module_bit = OMAP2430_EN_USBHS_MASK,
1564                         .module_offs = CORE_MOD,
1565                         .idlest_reg_id = 1,
1566                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1567                 },
1568         },
1569         .masters        = omap2430_usbhsotg_masters,
1570         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
1571         .slaves         = omap2430_usbhsotg_slaves,
1572         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1573         .class          = &usbotg_class,
1574         /*
1575          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1576          * broken when autoidle is enabled
1577          * workaround is to disable the autoidle bit at module level.
1578          */
1579         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1580                                 | HWMOD_SWSUP_MSTANDBY,
1581         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1582 };
1583
1584 /*
1585  * 'mcbsp' class
1586  * multi channel buffered serial port controller
1587  */
1588
1589 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1590         .rev_offs       = 0x007C,
1591         .sysc_offs      = 0x008C,
1592         .sysc_flags     = (SYSC_HAS_SOFTRESET),
1593         .sysc_fields    = &omap_hwmod_sysc_type1,
1594 };
1595
1596 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1597         .name = "mcbsp",
1598         .sysc = &omap2430_mcbsp_sysc,
1599         .rev  = MCBSP_CONFIG_TYPE2,
1600 };
1601
1602 /* mcbsp1 */
1603 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1604         { .name = "tx",         .irq = 59 },
1605         { .name = "rx",         .irq = 60 },
1606         { .name = "ovr",        .irq = 61 },
1607         { .name = "common",     .irq = 64 },
1608 };
1609
1610 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
1611         { .name = "rx", .dma_req = 32 },
1612         { .name = "tx", .dma_req = 31 },
1613 };
1614
1615 static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
1616         {
1617                 .name           = "mpu",
1618                 .pa_start       = 0x48074000,
1619                 .pa_end         = 0x480740ff,
1620                 .flags          = ADDR_TYPE_RT
1621         },
1622 };
1623
1624 /* l4_core -> mcbsp1 */
1625 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1626         .master         = &omap2430_l4_core_hwmod,
1627         .slave          = &omap2430_mcbsp1_hwmod,
1628         .clk            = "mcbsp1_ick",
1629         .addr           = omap2430_mcbsp1_addrs,
1630         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
1631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1632 };
1633
1634 /* mcbsp1 slave ports */
1635 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1636         &omap2430_l4_core__mcbsp1,
1637 };
1638
1639 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1640         .name           = "mcbsp1",
1641         .class          = &omap2430_mcbsp_hwmod_class,
1642         .mpu_irqs       = omap2430_mcbsp1_irqs,
1643         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
1644         .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
1645         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
1646         .main_clk       = "mcbsp1_fck",
1647         .prcm           = {
1648                 .omap2 = {
1649                         .prcm_reg_id = 1,
1650                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1651                         .module_offs = CORE_MOD,
1652                         .idlest_reg_id = 1,
1653                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1654                 },
1655         },
1656         .slaves         = omap2430_mcbsp1_slaves,
1657         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1658         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1659 };
1660
1661 /* mcbsp2 */
1662 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1663         { .name = "tx",         .irq = 62 },
1664         { .name = "rx",         .irq = 63 },
1665         { .name = "common",     .irq = 16 },
1666 };
1667
1668 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
1669         { .name = "rx", .dma_req = 34 },
1670         { .name = "tx", .dma_req = 33 },
1671 };
1672
1673 static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
1674         {
1675                 .name           = "mpu",
1676                 .pa_start       = 0x48076000,
1677                 .pa_end         = 0x480760ff,
1678                 .flags          = ADDR_TYPE_RT
1679         },
1680 };
1681
1682 /* l4_core -> mcbsp2 */
1683 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1684         .master         = &omap2430_l4_core_hwmod,
1685         .slave          = &omap2430_mcbsp2_hwmod,
1686         .clk            = "mcbsp2_ick",
1687         .addr           = omap2430_mcbsp2_addrs,
1688         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
1689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1690 };
1691
1692 /* mcbsp2 slave ports */
1693 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1694         &omap2430_l4_core__mcbsp2,
1695 };
1696
1697 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1698         .name           = "mcbsp2",
1699         .class          = &omap2430_mcbsp_hwmod_class,
1700         .mpu_irqs       = omap2430_mcbsp2_irqs,
1701         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
1702         .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
1703         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
1704         .main_clk       = "mcbsp2_fck",
1705         .prcm           = {
1706                 .omap2 = {
1707                         .prcm_reg_id = 1,
1708                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1709                         .module_offs = CORE_MOD,
1710                         .idlest_reg_id = 1,
1711                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1712                 },
1713         },
1714         .slaves         = omap2430_mcbsp2_slaves,
1715         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1716         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1717 };
1718
1719 /* mcbsp3 */
1720 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1721         { .name = "tx",         .irq = 89 },
1722         { .name = "rx",         .irq = 90 },
1723         { .name = "common",     .irq = 17 },
1724 };
1725
1726 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
1727         { .name = "rx", .dma_req = 18 },
1728         { .name = "tx", .dma_req = 17 },
1729 };
1730
1731 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1732         {
1733                 .name           = "mpu",
1734                 .pa_start       = 0x4808C000,
1735                 .pa_end         = 0x4808C0ff,
1736                 .flags          = ADDR_TYPE_RT
1737         },
1738 };
1739
1740 /* l4_core -> mcbsp3 */
1741 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1742         .master         = &omap2430_l4_core_hwmod,
1743         .slave          = &omap2430_mcbsp3_hwmod,
1744         .clk            = "mcbsp3_ick",
1745         .addr           = omap2430_mcbsp3_addrs,
1746         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
1747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1748 };
1749
1750 /* mcbsp3 slave ports */
1751 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1752         &omap2430_l4_core__mcbsp3,
1753 };
1754
1755 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1756         .name           = "mcbsp3",
1757         .class          = &omap2430_mcbsp_hwmod_class,
1758         .mpu_irqs       = omap2430_mcbsp3_irqs,
1759         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
1760         .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
1761         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
1762         .main_clk       = "mcbsp3_fck",
1763         .prcm           = {
1764                 .omap2 = {
1765                         .prcm_reg_id = 1,
1766                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1767                         .module_offs = CORE_MOD,
1768                         .idlest_reg_id = 2,
1769                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1770                 },
1771         },
1772         .slaves         = omap2430_mcbsp3_slaves,
1773         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1774         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1775 };
1776
1777 /* mcbsp4 */
1778 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1779         { .name = "tx",         .irq = 54 },
1780         { .name = "rx",         .irq = 55 },
1781         { .name = "common",     .irq = 18 },
1782 };
1783
1784 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1785         { .name = "rx", .dma_req = 20 },
1786         { .name = "tx", .dma_req = 19 },
1787 };
1788
1789 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1790         {
1791                 .name           = "mpu",
1792                 .pa_start       = 0x4808E000,
1793                 .pa_end         = 0x4808E0ff,
1794                 .flags          = ADDR_TYPE_RT
1795         },
1796 };
1797
1798 /* l4_core -> mcbsp4 */
1799 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1800         .master         = &omap2430_l4_core_hwmod,
1801         .slave          = &omap2430_mcbsp4_hwmod,
1802         .clk            = "mcbsp4_ick",
1803         .addr           = omap2430_mcbsp4_addrs,
1804         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
1805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1806 };
1807
1808 /* mcbsp4 slave ports */
1809 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1810         &omap2430_l4_core__mcbsp4,
1811 };
1812
1813 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1814         .name           = "mcbsp4",
1815         .class          = &omap2430_mcbsp_hwmod_class,
1816         .mpu_irqs       = omap2430_mcbsp4_irqs,
1817         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
1818         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
1819         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
1820         .main_clk       = "mcbsp4_fck",
1821         .prcm           = {
1822                 .omap2 = {
1823                         .prcm_reg_id = 1,
1824                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1825                         .module_offs = CORE_MOD,
1826                         .idlest_reg_id = 2,
1827                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1828                 },
1829         },
1830         .slaves         = omap2430_mcbsp4_slaves,
1831         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1832         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1833 };
1834
1835 /* mcbsp5 */
1836 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1837         { .name = "tx",         .irq = 81 },
1838         { .name = "rx",         .irq = 82 },
1839         { .name = "common",     .irq = 19 },
1840 };
1841
1842 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1843         { .name = "rx", .dma_req = 22 },
1844         { .name = "tx", .dma_req = 21 },
1845 };
1846
1847 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1848         {
1849                 .name           = "mpu",
1850                 .pa_start       = 0x48096000,
1851                 .pa_end         = 0x480960ff,
1852                 .flags          = ADDR_TYPE_RT
1853         },
1854 };
1855
1856 /* l4_core -> mcbsp5 */
1857 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1858         .master         = &omap2430_l4_core_hwmod,
1859         .slave          = &omap2430_mcbsp5_hwmod,
1860         .clk            = "mcbsp5_ick",
1861         .addr           = omap2430_mcbsp5_addrs,
1862         .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
1863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1864 };
1865
1866 /* mcbsp5 slave ports */
1867 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1868         &omap2430_l4_core__mcbsp5,
1869 };
1870
1871 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1872         .name           = "mcbsp5",
1873         .class          = &omap2430_mcbsp_hwmod_class,
1874         .mpu_irqs       = omap2430_mcbsp5_irqs,
1875         .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
1876         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
1877         .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
1878         .main_clk       = "mcbsp5_fck",
1879         .prcm           = {
1880                 .omap2 = {
1881                         .prcm_reg_id = 1,
1882                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1883                         .module_offs = CORE_MOD,
1884                         .idlest_reg_id = 2,
1885                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1886                 },
1887         },
1888         .slaves         = omap2430_mcbsp5_slaves,
1889         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1890         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1891 };
1892
1893 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1894         &omap2430_l3_main_hwmod,
1895         &omap2430_l4_core_hwmod,
1896         &omap2430_l4_wkup_hwmod,
1897         &omap2430_mpu_hwmod,
1898         &omap2430_iva_hwmod,
1899         &omap2430_wd_timer2_hwmod,
1900         &omap2430_uart1_hwmod,
1901         &omap2430_uart2_hwmod,
1902         &omap2430_uart3_hwmod,
1903         /* dss class */
1904         &omap2430_dss_core_hwmod,
1905         &omap2430_dss_dispc_hwmod,
1906         &omap2430_dss_rfbi_hwmod,
1907         &omap2430_dss_venc_hwmod,
1908         /* i2c class */
1909         &omap2430_i2c1_hwmod,
1910         &omap2430_i2c2_hwmod,
1911
1912         /* gpio class */
1913         &omap2430_gpio1_hwmod,
1914         &omap2430_gpio2_hwmod,
1915         &omap2430_gpio3_hwmod,
1916         &omap2430_gpio4_hwmod,
1917         &omap2430_gpio5_hwmod,
1918
1919         /* dma_system class*/
1920         &omap2430_dma_system_hwmod,
1921
1922         /* mcbsp class */
1923         &omap2430_mcbsp1_hwmod,
1924         &omap2430_mcbsp2_hwmod,
1925         &omap2430_mcbsp3_hwmod,
1926         &omap2430_mcbsp4_hwmod,
1927         &omap2430_mcbsp5_hwmod,
1928
1929         /* mailbox class */
1930         &omap2430_mailbox_hwmod,
1931
1932         /* mcspi class */
1933         &omap2430_mcspi1_hwmod,
1934         &omap2430_mcspi2_hwmod,
1935         &omap2430_mcspi3_hwmod,
1936
1937         /* usbotg class*/
1938         &omap2430_usbhsotg_hwmod,
1939
1940         NULL,
1941 };
1942
1943 int __init omap2430_hwmod_init(void)
1944 {
1945         return omap_hwmod_init(omap2430_hwmods);
1946 }