arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .modulemode   = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 /*
 353  * 'c2c' class
 354  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355  * soc
 356  */
 357
 358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359         .name   = "c2c",
 360 };
 361
 362 /* c2c */
 363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365         { .irq = -1 }
 366 };
 367
 368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370         { .dma_req = -1 }
 371 };
 372
 373 static struct omap_hwmod omap44xx_c2c_hwmod = {
 374         .name           = "c2c",
 375         .class          = &omap44xx_c2c_hwmod_class,
 376         .clkdm_name     = "d2d_clkdm",
 377         .mpu_irqs       = omap44xx_c2c_irqs,
 378         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383                 },
 384         },
 385 };
 386
 387 /*
 388  * 'counter' class
 389  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390  */
 391
 392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393         .rev_offs       = 0x0000,
 394         .sysc_offs      = 0x0004,
 395         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 397                            SIDLE_SMART_WKUP),
 398         .sysc_fields    = &omap_hwmod_sysc_type1,
 399 };
 400
 401 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 402         .name   = "counter",
 403         .sysc   = &omap44xx_counter_sysc,
 404 };
 405
 406 /* counter_32k */
 407 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 408         .name           = "counter_32k",
 409         .class          = &omap44xx_counter_hwmod_class,
 410         .clkdm_name     = "l4_wkup_clkdm",
 411         .flags          = HWMOD_SWSUP_SIDLE,
 412         .main_clk       = "sys_32k_ck",
 413         .prcm = {
 414                 .omap4 = {
 415                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 416                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 417                 },
 418         },
 419 };
 420
 421 /*
 422  * 'ctrl_module' class
 423  * attila core control module + core pad control module + wkup pad control
 424  * module + attila wkup control module
 425  */
 426
 427 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 428         .rev_offs       = 0x0000,
 429         .sysc_offs      = 0x0010,
 430         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 432                            SIDLE_SMART_WKUP),
 433         .sysc_fields    = &omap_hwmod_sysc_type2,
 434 };
 435
 436 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 437         .name   = "ctrl_module",
 438         .sysc   = &omap44xx_ctrl_module_sysc,
 439 };
 440
 441 /* ctrl_module_core */
 442 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 443         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 444         { .irq = -1 }
 445 };
 446
 447 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 448         .name           = "ctrl_module_core",
 449         .class          = &omap44xx_ctrl_module_hwmod_class,
 450         .clkdm_name     = "l4_cfg_clkdm",
 451         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 452 };
 453
 454 /* ctrl_module_pad_core */
 455 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 456         .name           = "ctrl_module_pad_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459 };
 460
 461 /* ctrl_module_wkup */
 462 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 463         .name           = "ctrl_module_wkup",
 464         .class          = &omap44xx_ctrl_module_hwmod_class,
 465         .clkdm_name     = "l4_wkup_clkdm",
 466 };
 467
 468 /* ctrl_module_pad_wkup */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 470         .name           = "ctrl_module_pad_wkup",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_wkup_clkdm",
 473 };
 474
 475 /*
 476  * 'debugss' class
 477  * debug and emulation sub system
 478  */
 479
 480 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 481         .name   = "debugss",
 482 };
 483
 484 /* debugss */
 485 static struct omap_hwmod omap44xx_debugss_hwmod = {
 486         .name           = "debugss",
 487         .class          = &omap44xx_debugss_hwmod_class,
 488         .clkdm_name     = "emu_sys_clkdm",
 489         .main_clk       = "trace_clk_div_ck",
 490         .prcm = {
 491                 .omap4 = {
 492                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 493                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 494                 },
 495         },
 496 };
 497
 498 /*
 499  * 'dma' class
 500  * dma controller for data exchange between memory to memory (i.e. internal or
 501  * external memory) and gp peripherals to memory or memory to gp peripherals
 502  */
 503
 504 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 505         .rev_offs       = 0x0000,
 506         .sysc_offs      = 0x002c,
 507         .syss_offs      = 0x0028,
 508         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 509                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 510                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 511                            SYSS_HAS_RESET_STATUS),
 512         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 513                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 514         .sysc_fields    = &omap_hwmod_sysc_type1,
 515 };
 516
 517 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 518         .name   = "dma",
 519         .sysc   = &omap44xx_dma_sysc,
 520 };
 521
 522 /* dma dev_attr */
 523 static struct omap_dma_dev_attr dma_dev_attr = {
 524         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 525                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 526         .lch_count      = 32,
 527 };
 528
 529 /* dma_system */
 530 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 531         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 534         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 535         { .irq = -1 }
 536 };
 537
 538 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 539         .name           = "dma_system",
 540         .class          = &omap44xx_dma_hwmod_class,
 541         .clkdm_name     = "l3_dma_clkdm",
 542         .mpu_irqs       = omap44xx_dma_system_irqs,
 543         .main_clk       = "l3_div_ck",
 544         .prcm = {
 545                 .omap4 = {
 546                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 547                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 548                 },
 549         },
 550         .dev_attr       = &dma_dev_attr,
 551 };
 552
 553 /*
 554  * 'dmic' class
 555  * digital microphone controller
 556  */
 557
 558 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 559         .rev_offs       = 0x0000,
 560         .sysc_offs      = 0x0010,
 561         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 562                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 564                            SIDLE_SMART_WKUP),
 565         .sysc_fields    = &omap_hwmod_sysc_type2,
 566 };
 567
 568 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 569         .name   = "dmic",
 570         .sysc   = &omap44xx_dmic_sysc,
 571 };
 572
 573 /* dmic */
 574 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 575         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 576         { .irq = -1 }
 577 };
 578
 579 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 580         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 581         { .dma_req = -1 }
 582 };
 583
 584 static struct omap_hwmod omap44xx_dmic_hwmod = {
 585         .name           = "dmic",
 586         .class          = &omap44xx_dmic_hwmod_class,
 587         .clkdm_name     = "abe_clkdm",
 588         .mpu_irqs       = omap44xx_dmic_irqs,
 589         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 590         .main_clk       = "dmic_fck",
 591         .prcm = {
 592                 .omap4 = {
 593                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 594                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 595                         .modulemode   = MODULEMODE_SWCTRL,
 596                 },
 597         },
 598 };
 599
 600 /*
 601  * 'dsp' class
 602  * dsp sub-system
 603  */
 604
 605 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 606         .name   = "dsp",
 607 };
 608
 609 /* dsp */
 610 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 611         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 612         { .irq = -1 }
 613 };
 614
 615 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 616         { .name = "dsp", .rst_shift = 0 },
 617         { .name = "mmu_cache", .rst_shift = 1 },
 618 };
 619
 620 static struct omap_hwmod omap44xx_dsp_hwmod = {
 621         .name           = "dsp",
 622         .class          = &omap44xx_dsp_hwmod_class,
 623         .clkdm_name     = "tesla_clkdm",
 624         .mpu_irqs       = omap44xx_dsp_irqs,
 625         .rst_lines      = omap44xx_dsp_resets,
 626         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 627         .main_clk       = "dsp_fck",
 628         .prcm = {
 629                 .omap4 = {
 630                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 631                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 633                         .modulemode   = MODULEMODE_HWCTRL,
 634                 },
 635         },
 636 };
 637
 638 /*
 639  * 'dss' class
 640  * display sub-system
 641  */
 642
 643 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 644         .rev_offs       = 0x0000,
 645         .syss_offs      = 0x0014,
 646         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 647 };
 648
 649 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 650         .name   = "dss",
 651         .sysc   = &omap44xx_dss_sysc,
 652         .reset  = omap_dss_reset,
 653 };
 654
 655 /* dss */
 656 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 657         { .role = "sys_clk", .clk = "dss_sys_clk" },
 658         { .role = "tv_clk", .clk = "dss_tv_clk" },
 659         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 660 };
 661
 662 static struct omap_hwmod omap44xx_dss_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap44xx_dss_hwmod_class,
 666         .clkdm_name     = "l3_dss_clkdm",
 667         .main_clk       = "dss_dss_clk",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 671                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 672                 },
 673         },
 674         .opt_clks       = dss_opt_clks,
 675         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 676 };
 677
 678 /*
 679  * 'dispc' class
 680  * display controller
 681  */
 682
 683 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 684         .rev_offs       = 0x0000,
 685         .sysc_offs      = 0x0010,
 686         .syss_offs      = 0x0014,
 687         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 688                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 689                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 690                            SYSS_HAS_RESET_STATUS),
 691         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 692                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 697         .name   = "dispc",
 698         .sysc   = &omap44xx_dispc_sysc,
 699 };
 700
 701 /* dss_dispc */
 702 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 703         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 704         { .irq = -1 }
 705 };
 706
 707 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 708         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 709         { .dma_req = -1 }
 710 };
 711
 712 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 713         .manager_count          = 3,
 714         .has_framedonetv_irq    = 1
 715 };
 716
 717 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 718         .name           = "dss_dispc",
 719         .class          = &omap44xx_dispc_hwmod_class,
 720         .clkdm_name     = "l3_dss_clkdm",
 721         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 722         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 723         .main_clk       = "dss_dss_clk",
 724         .prcm = {
 725                 .omap4 = {
 726                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 727                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 728                 },
 729         },
 730         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 731 };
 732
 733 /*
 734  * 'dsi' class
 735  * display serial interface controller
 736  */
 737
 738 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 739         .rev_offs       = 0x0000,
 740         .sysc_offs      = 0x0010,
 741         .syss_offs      = 0x0014,
 742         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 743                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 744                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 746         .sysc_fields    = &omap_hwmod_sysc_type1,
 747 };
 748
 749 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 750         .name   = "dsi",
 751         .sysc   = &omap44xx_dsi_sysc,
 752 };
 753
 754 /* dss_dsi1 */
 755 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 756         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 757         { .irq = -1 }
 758 };
 759
 760 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 761         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 762         { .dma_req = -1 }
 763 };
 764
 765 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 766         { .role = "sys_clk", .clk = "dss_sys_clk" },
 767 };
 768
 769 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 770         .name           = "dss_dsi1",
 771         .class          = &omap44xx_dsi_hwmod_class,
 772         .clkdm_name     = "l3_dss_clkdm",
 773         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 774         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 775         .main_clk       = "dss_dss_clk",
 776         .prcm = {
 777                 .omap4 = {
 778                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 779                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 780                 },
 781         },
 782         .opt_clks       = dss_dsi1_opt_clks,
 783         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 784 };
 785
 786 /* dss_dsi2 */
 787 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 788         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 789         { .irq = -1 }
 790 };
 791
 792 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 793         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 794         { .dma_req = -1 }
 795 };
 796
 797 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 798         { .role = "sys_clk", .clk = "dss_sys_clk" },
 799 };
 800
 801 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 802         .name           = "dss_dsi2",
 803         .class          = &omap44xx_dsi_hwmod_class,
 804         .clkdm_name     = "l3_dss_clkdm",
 805         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 806         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 807         .main_clk       = "dss_dss_clk",
 808         .prcm = {
 809                 .omap4 = {
 810                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 811                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 812                 },
 813         },
 814         .opt_clks       = dss_dsi2_opt_clks,
 815         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 816 };
 817
 818 /*
 819  * 'hdmi' class
 820  * hdmi controller
 821  */
 822
 823 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 824         .rev_offs       = 0x0000,
 825         .sysc_offs      = 0x0010,
 826         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 827                            SYSC_HAS_SOFTRESET),
 828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 829                            SIDLE_SMART_WKUP),
 830         .sysc_fields    = &omap_hwmod_sysc_type2,
 831 };
 832
 833 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 834         .name   = "hdmi",
 835         .sysc   = &omap44xx_hdmi_sysc,
 836 };
 837
 838 /* dss_hdmi */
 839 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 840         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 841         { .irq = -1 }
 842 };
 843
 844 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 845         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 846         { .dma_req = -1 }
 847 };
 848
 849 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 850         { .role = "sys_clk", .clk = "dss_sys_clk" },
 851 };
 852
 853 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 854         .name           = "dss_hdmi",
 855         .class          = &omap44xx_hdmi_hwmod_class,
 856         .clkdm_name     = "l3_dss_clkdm",
 857         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 858         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 859         .main_clk       = "dss_48mhz_clk",
 860         .prcm = {
 861                 .omap4 = {
 862                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 863                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 864                 },
 865         },
 866         .opt_clks       = dss_hdmi_opt_clks,
 867         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 868 };
 869
 870 /*
 871  * 'rfbi' class
 872  * remote frame buffer interface
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 876         .rev_offs       = 0x0000,
 877         .sysc_offs      = 0x0010,
 878         .syss_offs      = 0x0014,
 879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 880                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 881         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 882         .sysc_fields    = &omap_hwmod_sysc_type1,
 883 };
 884
 885 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 886         .name   = "rfbi",
 887         .sysc   = &omap44xx_rfbi_sysc,
 888 };
 889
 890 /* dss_rfbi */
 891 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 892         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 893         { .dma_req = -1 }
 894 };
 895
 896 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 897         { .role = "ick", .clk = "dss_fck" },
 898 };
 899
 900 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 901         .name           = "dss_rfbi",
 902         .class          = &omap44xx_rfbi_hwmod_class,
 903         .clkdm_name     = "l3_dss_clkdm",
 904         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 905         .main_clk       = "dss_dss_clk",
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 909                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 910                 },
 911         },
 912         .opt_clks       = dss_rfbi_opt_clks,
 913         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 914 };
 915
 916 /*
 917  * 'venc' class
 918  * video encoder
 919  */
 920
 921 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 922         .name   = "venc",
 923 };
 924
 925 /* dss_venc */
 926 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 927         .name           = "dss_venc",
 928         .class          = &omap44xx_venc_hwmod_class,
 929         .clkdm_name     = "l3_dss_clkdm",
 930         .main_clk       = "dss_tv_clk",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 934                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 935                 },
 936         },
 937 };
 938
 939 /*
 940  * 'elm' class
 941  * bch error location module
 942  */
 943
 944 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 945         .rev_offs       = 0x0000,
 946         .sysc_offs      = 0x0010,
 947         .syss_offs      = 0x0014,
 948         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 949                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 950                            SYSS_HAS_RESET_STATUS),
 951         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 952         .sysc_fields    = &omap_hwmod_sysc_type1,
 953 };
 954
 955 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 956         .name   = "elm",
 957         .sysc   = &omap44xx_elm_sysc,
 958 };
 959
 960 /* elm */
 961 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 962         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 963         { .irq = -1 }
 964 };
 965
 966 static struct omap_hwmod omap44xx_elm_hwmod = {
 967         .name           = "elm",
 968         .class          = &omap44xx_elm_hwmod_class,
 969         .clkdm_name     = "l4_per_clkdm",
 970         .mpu_irqs       = omap44xx_elm_irqs,
 971         .prcm = {
 972                 .omap4 = {
 973                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 974                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 975                 },
 976         },
 977 };
 978
 979 /*
 980  * 'emif' class
 981  * external memory interface no1
 982  */
 983
 984 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 985         .rev_offs       = 0x0000,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 989         .name   = "emif",
 990         .sysc   = &omap44xx_emif_sysc,
 991 };
 992
 993 /* emif1 */
 994 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 995         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_emif1_hwmod = {
1000         .name           = "emif1",
1001         .class          = &omap44xx_emif_hwmod_class,
1002         .clkdm_name     = "l3_emif_clkdm",
1003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004         .mpu_irqs       = omap44xx_emif1_irqs,
1005         .main_clk       = "ddrphy_ck",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013 };
1014
1015 /* emif2 */
1016 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1017         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1018         { .irq = -1 }
1019 };
1020
1021 static struct omap_hwmod omap44xx_emif2_hwmod = {
1022         .name           = "emif2",
1023         .class          = &omap44xx_emif_hwmod_class,
1024         .clkdm_name     = "l3_emif_clkdm",
1025         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026         .mpu_irqs       = omap44xx_emif2_irqs,
1027         .main_clk       = "ddrphy_ck",
1028         .prcm = {
1029                 .omap4 = {
1030                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1031                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1032                         .modulemode   = MODULEMODE_HWCTRL,
1033                 },
1034         },
1035 };
1036
1037 /*
1038  * 'fdif' class
1039  * face detection hw accelerator module
1040  */
1041
1042 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1043         .rev_offs       = 0x0000,
1044         .sysc_offs      = 0x0010,
1045         /*
1046          * FDIF needs 100 OCP clk cycles delay after a softreset before
1047          * accessing sysconfig again.
1048          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050          *
1051          * TODO: Indicate errata when available.
1052          */
1053         .srst_udelay    = 2,
1054         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058         .sysc_fields    = &omap_hwmod_sysc_type2,
1059 };
1060
1061 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1062         .name   = "fdif",
1063         .sysc   = &omap44xx_fdif_sysc,
1064 };
1065
1066 /* fdif */
1067 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1068         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1069         { .irq = -1 }
1070 };
1071
1072 static struct omap_hwmod omap44xx_fdif_hwmod = {
1073         .name           = "fdif",
1074         .class          = &omap44xx_fdif_hwmod_class,
1075         .clkdm_name     = "iss_clkdm",
1076         .mpu_irqs       = omap44xx_fdif_irqs,
1077         .main_clk       = "fdif_fck",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085 };
1086
1087 /*
1088  * 'gpio' class
1089  * general purpose io module
1090  */
1091
1092 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1093         .rev_offs       = 0x0000,
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0114,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1097                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1098                            SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .sysc_fields    = &omap_hwmod_sysc_type1,
1102 };
1103
1104 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1105         .name   = "gpio",
1106         .sysc   = &omap44xx_gpio_sysc,
1107         .rev    = 2,
1108 };
1109
1110 /* gpio dev_attr */
1111 static struct omap_gpio_dev_attr gpio_dev_attr = {
1112         .bank_width     = 32,
1113         .dbck_flag      = true,
1114 };
1115
1116 /* gpio1 */
1117 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1118         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1119         { .irq = -1 }
1120 };
1121
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1123         { .role = "dbclk", .clk = "gpio1_dbclk" },
1124 };
1125
1126 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1127         .name           = "gpio1",
1128         .class          = &omap44xx_gpio_hwmod_class,
1129         .clkdm_name     = "l4_wkup_clkdm",
1130         .mpu_irqs       = omap44xx_gpio1_irqs,
1131         .main_clk       = "gpio1_ick",
1132         .prcm = {
1133                 .omap4 = {
1134                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1135                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1136                         .modulemode   = MODULEMODE_HWCTRL,
1137                 },
1138         },
1139         .opt_clks       = gpio1_opt_clks,
1140         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1141         .dev_attr       = &gpio_dev_attr,
1142 };
1143
1144 /* gpio2 */
1145 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1146         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1147         { .irq = -1 }
1148 };
1149
1150 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1151         { .role = "dbclk", .clk = "gpio2_dbclk" },
1152 };
1153
1154 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1155         .name           = "gpio2",
1156         .class          = &omap44xx_gpio_hwmod_class,
1157         .clkdm_name     = "l4_per_clkdm",
1158         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1159         .mpu_irqs       = omap44xx_gpio2_irqs,
1160         .main_clk       = "gpio2_ick",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168         .opt_clks       = gpio2_opt_clks,
1169         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1170         .dev_attr       = &gpio_dev_attr,
1171 };
1172
1173 /* gpio3 */
1174 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1175         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1176         { .irq = -1 }
1177 };
1178
1179 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1180         { .role = "dbclk", .clk = "gpio3_dbclk" },
1181 };
1182
1183 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1184         .name           = "gpio3",
1185         .class          = &omap44xx_gpio_hwmod_class,
1186         .clkdm_name     = "l4_per_clkdm",
1187         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1188         .mpu_irqs       = omap44xx_gpio3_irqs,
1189         .main_clk       = "gpio3_ick",
1190         .prcm = {
1191                 .omap4 = {
1192                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1193                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1194                         .modulemode   = MODULEMODE_HWCTRL,
1195                 },
1196         },
1197         .opt_clks       = gpio3_opt_clks,
1198         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1199         .dev_attr       = &gpio_dev_attr,
1200 };
1201
1202 /* gpio4 */
1203 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1204         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1205         { .irq = -1 }
1206 };
1207
1208 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1209         { .role = "dbclk", .clk = "gpio4_dbclk" },
1210 };
1211
1212 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1213         .name           = "gpio4",
1214         .class          = &omap44xx_gpio_hwmod_class,
1215         .clkdm_name     = "l4_per_clkdm",
1216         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1217         .mpu_irqs       = omap44xx_gpio4_irqs,
1218         .main_clk       = "gpio4_ick",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1222                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1223                         .modulemode   = MODULEMODE_HWCTRL,
1224                 },
1225         },
1226         .opt_clks       = gpio4_opt_clks,
1227         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1228         .dev_attr       = &gpio_dev_attr,
1229 };
1230
1231 /* gpio5 */
1232 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1233         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1234         { .irq = -1 }
1235 };
1236
1237 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1238         { .role = "dbclk", .clk = "gpio5_dbclk" },
1239 };
1240
1241 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1242         .name           = "gpio5",
1243         .class          = &omap44xx_gpio_hwmod_class,
1244         .clkdm_name     = "l4_per_clkdm",
1245         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1246         .mpu_irqs       = omap44xx_gpio5_irqs,
1247         .main_clk       = "gpio5_ick",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1251                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_HWCTRL,
1253                 },
1254         },
1255         .opt_clks       = gpio5_opt_clks,
1256         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1257         .dev_attr       = &gpio_dev_attr,
1258 };
1259
1260 /* gpio6 */
1261 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1262         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1263         { .irq = -1 }
1264 };
1265
1266 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1267         { .role = "dbclk", .clk = "gpio6_dbclk" },
1268 };
1269
1270 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1271         .name           = "gpio6",
1272         .class          = &omap44xx_gpio_hwmod_class,
1273         .clkdm_name     = "l4_per_clkdm",
1274         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1275         .mpu_irqs       = omap44xx_gpio6_irqs,
1276         .main_clk       = "gpio6_ick",
1277         .prcm = {
1278                 .omap4 = {
1279                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1280                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1281                         .modulemode   = MODULEMODE_HWCTRL,
1282                 },
1283         },
1284         .opt_clks       = gpio6_opt_clks,
1285         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1286         .dev_attr       = &gpio_dev_attr,
1287 };
1288
1289 /*
1290  * 'gpmc' class
1291  * general purpose memory controller
1292  */
1293
1294 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1295         .rev_offs       = 0x0000,
1296         .sysc_offs      = 0x0010,
1297         .syss_offs      = 0x0014,
1298         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1299                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1300         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1301         .sysc_fields    = &omap_hwmod_sysc_type1,
1302 };
1303
1304 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1305         .name   = "gpmc",
1306         .sysc   = &omap44xx_gpmc_sysc,
1307 };
1308
1309 /* gpmc */
1310 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1311         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1312         { .irq = -1 }
1313 };
1314
1315 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1316         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1317         { .dma_req = -1 }
1318 };
1319
1320 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1321         .name           = "gpmc",
1322         .class          = &omap44xx_gpmc_hwmod_class,
1323         .clkdm_name     = "l3_2_clkdm",
1324         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1325         .mpu_irqs       = omap44xx_gpmc_irqs,
1326         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1327         .prcm = {
1328                 .omap4 = {
1329                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1330                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1331                         .modulemode   = MODULEMODE_HWCTRL,
1332                 },
1333         },
1334 };
1335
1336 /*
1337  * 'gpu' class
1338  * 2d/3d graphics accelerator
1339  */
1340
1341 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1342         .rev_offs       = 0x1fc00,
1343         .sysc_offs      = 0x1fc10,
1344         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1347                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1348         .sysc_fields    = &omap_hwmod_sysc_type2,
1349 };
1350
1351 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1352         .name   = "gpu",
1353         .sysc   = &omap44xx_gpu_sysc,
1354 };
1355
1356 /* gpu */
1357 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1358         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1359         { .irq = -1 }
1360 };
1361
1362 static struct omap_hwmod omap44xx_gpu_hwmod = {
1363         .name           = "gpu",
1364         .class          = &omap44xx_gpu_hwmod_class,
1365         .clkdm_name     = "l3_gfx_clkdm",
1366         .mpu_irqs       = omap44xx_gpu_irqs,
1367         .main_clk       = "gpu_fck",
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_SWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'hdq1w' class
1379  * hdq / 1-wire serial interface controller
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1383         .rev_offs       = 0x0000,
1384         .sysc_offs      = 0x0014,
1385         .syss_offs      = 0x0018,
1386         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1387                            SYSS_HAS_RESET_STATUS),
1388         .sysc_fields    = &omap_hwmod_sysc_type1,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1392         .name   = "hdq1w",
1393         .sysc   = &omap44xx_hdq1w_sysc,
1394 };
1395
1396 /* hdq1w */
1397 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1398         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1403         .name           = "hdq1w",
1404         .class          = &omap44xx_hdq1w_hwmod_class,
1405         .clkdm_name     = "l4_per_clkdm",
1406         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1407         .mpu_irqs       = omap44xx_hdq1w_irqs,
1408         .main_clk       = "hdq1w_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hsi' class
1420  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1421  * serial if)
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0010,
1427         .syss_offs      = 0x0014,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1429                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1430                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1432                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1433                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1434         .sysc_fields    = &omap_hwmod_sysc_type1,
1435 };
1436
1437 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1438         .name   = "hsi",
1439         .sysc   = &omap44xx_hsi_sysc,
1440 };
1441
1442 /* hsi */
1443 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1444         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1445         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1446         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1447         { .irq = -1 }
1448 };
1449
1450 static struct omap_hwmod omap44xx_hsi_hwmod = {
1451         .name           = "hsi",
1452         .class          = &omap44xx_hsi_hwmod_class,
1453         .clkdm_name     = "l3_init_clkdm",
1454         .mpu_irqs       = omap44xx_hsi_irqs,
1455         .main_clk       = "hsi_fck",
1456         .prcm = {
1457                 .omap4 = {
1458                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1459                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1460                         .modulemode   = MODULEMODE_HWCTRL,
1461                 },
1462         },
1463 };
1464
1465 /*
1466  * 'i2c' class
1467  * multimaster high-speed i2c controller
1468  */
1469
1470 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1471         .sysc_offs      = 0x0010,
1472         .syss_offs      = 0x0090,
1473         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1474                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1475                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1476         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1477                            SIDLE_SMART_WKUP),
1478         .clockact       = CLOCKACT_TEST_ICLK,
1479         .sysc_fields    = &omap_hwmod_sysc_type1,
1480 };
1481
1482 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1483         .name   = "i2c",
1484         .sysc   = &omap44xx_i2c_sysc,
1485         .rev    = OMAP_I2C_IP_VERSION_2,
1486         .reset  = &omap_i2c_reset,
1487 };
1488
1489 static struct omap_i2c_dev_attr i2c_dev_attr = {
1490         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1491 };
1492
1493 /* i2c1 */
1494 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1495         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1496         { .irq = -1 }
1497 };
1498
1499 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1500         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1501         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1502         { .dma_req = -1 }
1503 };
1504
1505 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1506         .name           = "i2c1",
1507         .class          = &omap44xx_i2c_hwmod_class,
1508         .clkdm_name     = "l4_per_clkdm",
1509         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1510         .mpu_irqs       = omap44xx_i2c1_irqs,
1511         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1512         .main_clk       = "i2c1_fck",
1513         .prcm = {
1514                 .omap4 = {
1515                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1516                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1517                         .modulemode   = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520         .dev_attr       = &i2c_dev_attr,
1521 };
1522
1523 /* i2c2 */
1524 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1525         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1526         { .irq = -1 }
1527 };
1528
1529 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1530         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1531         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1532         { .dma_req = -1 }
1533 };
1534
1535 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1536         .name           = "i2c2",
1537         .class          = &omap44xx_i2c_hwmod_class,
1538         .clkdm_name     = "l4_per_clkdm",
1539         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1540         .mpu_irqs       = omap44xx_i2c2_irqs,
1541         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1542         .main_clk       = "i2c2_fck",
1543         .prcm = {
1544                 .omap4 = {
1545                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1546                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1547                         .modulemode   = MODULEMODE_SWCTRL,
1548                 },
1549         },
1550         .dev_attr       = &i2c_dev_attr,
1551 };
1552
1553 /* i2c3 */
1554 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1555         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1556         { .irq = -1 }
1557 };
1558
1559 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1560         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1561         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1562         { .dma_req = -1 }
1563 };
1564
1565 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1566         .name           = "i2c3",
1567         .class          = &omap44xx_i2c_hwmod_class,
1568         .clkdm_name     = "l4_per_clkdm",
1569         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1570         .mpu_irqs       = omap44xx_i2c3_irqs,
1571         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1572         .main_clk       = "i2c3_fck",
1573         .prcm = {
1574                 .omap4 = {
1575                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1576                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1577                         .modulemode   = MODULEMODE_SWCTRL,
1578                 },
1579         },
1580         .dev_attr       = &i2c_dev_attr,
1581 };
1582
1583 /* i2c4 */
1584 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1585         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1586         { .irq = -1 }
1587 };
1588
1589 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1590         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1591         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1592         { .dma_req = -1 }
1593 };
1594
1595 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1596         .name           = "i2c4",
1597         .class          = &omap44xx_i2c_hwmod_class,
1598         .clkdm_name     = "l4_per_clkdm",
1599         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1600         .mpu_irqs       = omap44xx_i2c4_irqs,
1601         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1602         .main_clk       = "i2c4_fck",
1603         .prcm = {
1604                 .omap4 = {
1605                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1606                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1607                         .modulemode   = MODULEMODE_SWCTRL,
1608                 },
1609         },
1610         .dev_attr       = &i2c_dev_attr,
1611 };
1612
1613 /*
1614  * 'ipu' class
1615  * imaging processor unit
1616  */
1617
1618 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1619         .name   = "ipu",
1620 };
1621
1622 /* ipu */
1623 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1624         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1625         { .irq = -1 }
1626 };
1627
1628 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1629         { .name = "cpu0", .rst_shift = 0 },
1630         { .name = "cpu1", .rst_shift = 1 },
1631         { .name = "mmu_cache", .rst_shift = 2 },
1632 };
1633
1634 static struct omap_hwmod omap44xx_ipu_hwmod = {
1635         .name           = "ipu",
1636         .class          = &omap44xx_ipu_hwmod_class,
1637         .clkdm_name     = "ducati_clkdm",
1638         .mpu_irqs       = omap44xx_ipu_irqs,
1639         .rst_lines      = omap44xx_ipu_resets,
1640         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1641         .main_clk       = "ipu_fck",
1642         .prcm = {
1643                 .omap4 = {
1644                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1645                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1646                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1647                         .modulemode   = MODULEMODE_HWCTRL,
1648                 },
1649         },
1650 };
1651
1652 /*
1653  * 'iss' class
1654  * external images sensor pixel data processor
1655  */
1656
1657 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1658         .rev_offs       = 0x0000,
1659         .sysc_offs      = 0x0010,
1660         /*
1661          * ISS needs 100 OCP clk cycles delay after a softreset before
1662          * accessing sysconfig again.
1663          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1664          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1665          *
1666          * TODO: Indicate errata when available.
1667          */
1668         .srst_udelay    = 2,
1669         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1670                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1672                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1673                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1674         .sysc_fields    = &omap_hwmod_sysc_type2,
1675 };
1676
1677 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1678         .name   = "iss",
1679         .sysc   = &omap44xx_iss_sysc,
1680 };
1681
1682 /* iss */
1683 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1684         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1685         { .irq = -1 }
1686 };
1687
1688 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1689         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1690         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1691         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1692         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1693         { .dma_req = -1 }
1694 };
1695
1696 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1697         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1698 };
1699
1700 static struct omap_hwmod omap44xx_iss_hwmod = {
1701         .name           = "iss",
1702         .class          = &omap44xx_iss_hwmod_class,
1703         .clkdm_name     = "iss_clkdm",
1704         .mpu_irqs       = omap44xx_iss_irqs,
1705         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1706         .main_clk       = "iss_fck",
1707         .prcm = {
1708                 .omap4 = {
1709                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1710                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1711                         .modulemode   = MODULEMODE_SWCTRL,
1712                 },
1713         },
1714         .opt_clks       = iss_opt_clks,
1715         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1716 };
1717
1718 /*
1719  * 'iva' class
1720  * multi-standard video encoder/decoder hardware accelerator
1721  */
1722
1723 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1724         .name   = "iva",
1725 };
1726
1727 /* iva */
1728 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1729         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1730         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1731         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1732         { .irq = -1 }
1733 };
1734
1735 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1736         { .name = "seq0", .rst_shift = 0 },
1737         { .name = "seq1", .rst_shift = 1 },
1738         { .name = "logic", .rst_shift = 2 },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iva_hwmod = {
1742         .name           = "iva",
1743         .class          = &omap44xx_iva_hwmod_class,
1744         .clkdm_name     = "ivahd_clkdm",
1745         .mpu_irqs       = omap44xx_iva_irqs,
1746         .rst_lines      = omap44xx_iva_resets,
1747         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1748         .main_clk       = "iva_fck",
1749         .prcm = {
1750                 .omap4 = {
1751                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1752                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1753                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1754                         .modulemode   = MODULEMODE_HWCTRL,
1755                 },
1756         },
1757 };
1758
1759 /*
1760  * 'kbd' class
1761  * keyboard controller
1762  */
1763
1764 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1765         .rev_offs       = 0x0000,
1766         .sysc_offs      = 0x0010,
1767         .syss_offs      = 0x0014,
1768         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1769                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1770                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1771                            SYSS_HAS_RESET_STATUS),
1772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1773         .sysc_fields    = &omap_hwmod_sysc_type1,
1774 };
1775
1776 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1777         .name   = "kbd",
1778         .sysc   = &omap44xx_kbd_sysc,
1779 };
1780
1781 /* kbd */
1782 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1783         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1784         { .irq = -1 }
1785 };
1786
1787 static struct omap_hwmod omap44xx_kbd_hwmod = {
1788         .name           = "kbd",
1789         .class          = &omap44xx_kbd_hwmod_class,
1790         .clkdm_name     = "l4_wkup_clkdm",
1791         .mpu_irqs       = omap44xx_kbd_irqs,
1792         .main_clk       = "kbd_fck",
1793         .prcm = {
1794                 .omap4 = {
1795                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1796                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1797                         .modulemode   = MODULEMODE_SWCTRL,
1798                 },
1799         },
1800 };
1801
1802 /*
1803  * 'mailbox' class
1804  * mailbox module allowing communication between the on-chip processors using a
1805  * queued mailbox-interrupt mechanism.
1806  */
1807
1808 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1809         .rev_offs       = 0x0000,
1810         .sysc_offs      = 0x0010,
1811         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1812                            SYSC_HAS_SOFTRESET),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type2,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1818         .name   = "mailbox",
1819         .sysc   = &omap44xx_mailbox_sysc,
1820 };
1821
1822 /* mailbox */
1823 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1824         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1829         .name           = "mailbox",
1830         .class          = &omap44xx_mailbox_hwmod_class,
1831         .clkdm_name     = "l4_cfg_clkdm",
1832         .mpu_irqs       = omap44xx_mailbox_irqs,
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1837                 },
1838         },
1839 };
1840
1841 /*
1842  * 'mcasp' class
1843  * multi-channel audio serial port controller
1844  */
1845
1846 /* The IP is not compliant to type1 / type2 scheme */
1847 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1848         .sidle_shift    = 0,
1849 };
1850
1851 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1852         .sysc_offs      = 0x0004,
1853         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1855                            SIDLE_SMART_WKUP),
1856         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1857 };
1858
1859 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1860         .name   = "mcasp",
1861         .sysc   = &omap44xx_mcasp_sysc,
1862 };
1863
1864 /* mcasp */
1865 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1866         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1867         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1868         { .irq = -1 }
1869 };
1870
1871 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1872         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1873         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1874         { .dma_req = -1 }
1875 };
1876
1877 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1878         .name           = "mcasp",
1879         .class          = &omap44xx_mcasp_hwmod_class,
1880         .clkdm_name     = "abe_clkdm",
1881         .mpu_irqs       = omap44xx_mcasp_irqs,
1882         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1883         .main_clk       = "mcasp_fck",
1884         .prcm = {
1885                 .omap4 = {
1886                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1887                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1888                         .modulemode   = MODULEMODE_SWCTRL,
1889                 },
1890         },
1891 };
1892
1893 /*
1894  * 'mcbsp' class
1895  * multi channel buffered serial port controller
1896  */
1897
1898 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1899         .sysc_offs      = 0x008c,
1900         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1901                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1902         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1903         .sysc_fields    = &omap_hwmod_sysc_type1,
1904 };
1905
1906 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1907         .name   = "mcbsp",
1908         .sysc   = &omap44xx_mcbsp_sysc,
1909         .rev    = MCBSP_CONFIG_TYPE4,
1910 };
1911
1912 /* mcbsp1 */
1913 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1914         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
1915         { .irq = -1 }
1916 };
1917
1918 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1919         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1920         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1921         { .dma_req = -1 }
1922 };
1923
1924 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1925         { .role = "pad_fck", .clk = "pad_clks_ck" },
1926         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1927 };
1928
1929 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1930         .name           = "mcbsp1",
1931         .class          = &omap44xx_mcbsp_hwmod_class,
1932         .clkdm_name     = "abe_clkdm",
1933         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1934         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1935         .main_clk       = "mcbsp1_fck",
1936         .prcm = {
1937                 .omap4 = {
1938                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1939                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1940                         .modulemode   = MODULEMODE_SWCTRL,
1941                 },
1942         },
1943         .opt_clks       = mcbsp1_opt_clks,
1944         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1945 };
1946
1947 /* mcbsp2 */
1948 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1949         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
1950         { .irq = -1 }
1951 };
1952
1953 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1954         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1955         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1956         { .dma_req = -1 }
1957 };
1958
1959 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1960         { .role = "pad_fck", .clk = "pad_clks_ck" },
1961         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1962 };
1963
1964 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1965         .name           = "mcbsp2",
1966         .class          = &omap44xx_mcbsp_hwmod_class,
1967         .clkdm_name     = "abe_clkdm",
1968         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1969         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1970         .main_clk       = "mcbsp2_fck",
1971         .prcm = {
1972                 .omap4 = {
1973                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1974                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1975                         .modulemode   = MODULEMODE_SWCTRL,
1976                 },
1977         },
1978         .opt_clks       = mcbsp2_opt_clks,
1979         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1980 };
1981
1982 /* mcbsp3 */
1983 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1984         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
1985         { .irq = -1 }
1986 };
1987
1988 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1989         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1990         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1991         { .dma_req = -1 }
1992 };
1993
1994 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1995         { .role = "pad_fck", .clk = "pad_clks_ck" },
1996         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
1997 };
1998
1999 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2000         .name           = "mcbsp3",
2001         .class          = &omap44xx_mcbsp_hwmod_class,
2002         .clkdm_name     = "abe_clkdm",
2003         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2004         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2005         .main_clk       = "mcbsp3_fck",
2006         .prcm = {
2007                 .omap4 = {
2008                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2009                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2010                         .modulemode   = MODULEMODE_SWCTRL,
2011                 },
2012         },
2013         .opt_clks       = mcbsp3_opt_clks,
2014         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2015 };
2016
2017 /* mcbsp4 */
2018 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2019         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2020         { .irq = -1 }
2021 };
2022
2023 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2024         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2025         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2026         { .dma_req = -1 }
2027 };
2028
2029 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2030         { .role = "pad_fck", .clk = "pad_clks_ck" },
2031         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2032 };
2033
2034 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2035         .name           = "mcbsp4",
2036         .class          = &omap44xx_mcbsp_hwmod_class,
2037         .clkdm_name     = "l4_per_clkdm",
2038         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2039         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2040         .main_clk       = "mcbsp4_fck",
2041         .prcm = {
2042                 .omap4 = {
2043                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2044                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2045                         .modulemode   = MODULEMODE_SWCTRL,
2046                 },
2047         },
2048         .opt_clks       = mcbsp4_opt_clks,
2049         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2050 };
2051
2052 /*
2053  * 'mcpdm' class
2054  * multi channel pdm controller (proprietary interface with phoenix power
2055  * ic)
2056  */
2057
2058 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2059         .rev_offs       = 0x0000,
2060         .sysc_offs      = 0x0010,
2061         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2062                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2063         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2064                            SIDLE_SMART_WKUP),
2065         .sysc_fields    = &omap_hwmod_sysc_type2,
2066 };
2067
2068 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2069         .name   = "mcpdm",
2070         .sysc   = &omap44xx_mcpdm_sysc,
2071 };
2072
2073 /* mcpdm */
2074 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2075         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2076         { .irq = -1 }
2077 };
2078
2079 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2080         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2081         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2082         { .dma_req = -1 }
2083 };
2084
2085 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2086         .name           = "mcpdm",
2087         .class          = &omap44xx_mcpdm_hwmod_class,
2088         .clkdm_name     = "abe_clkdm",
2089         .mpu_irqs       = omap44xx_mcpdm_irqs,
2090         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2091         .main_clk       = "mcpdm_fck",
2092         .prcm = {
2093                 .omap4 = {
2094                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2095                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2096                         .modulemode   = MODULEMODE_SWCTRL,
2097                 },
2098         },
2099 };
2100
2101 /*
2102  * 'mcspi' class
2103  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2104  * bus
2105  */
2106
2107 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2108         .rev_offs       = 0x0000,
2109         .sysc_offs      = 0x0010,
2110         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2111                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2113                            SIDLE_SMART_WKUP),
2114         .sysc_fields    = &omap_hwmod_sysc_type2,
2115 };
2116
2117 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2118         .name   = "mcspi",
2119         .sysc   = &omap44xx_mcspi_sysc,
2120         .rev    = OMAP4_MCSPI_REV,
2121 };
2122
2123 /* mcspi1 */
2124 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2125         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2126         { .irq = -1 }
2127 };
2128
2129 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2130         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2131         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2132         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2133         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2134         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2135         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2136         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2137         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2138         { .dma_req = -1 }
2139 };
2140
2141 /* mcspi1 dev_attr */
2142 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2143         .num_chipselect = 4,
2144 };
2145
2146 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2147         .name           = "mcspi1",
2148         .class          = &omap44xx_mcspi_hwmod_class,
2149         .clkdm_name     = "l4_per_clkdm",
2150         .mpu_irqs       = omap44xx_mcspi1_irqs,
2151         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2152         .main_clk       = "mcspi1_fck",
2153         .prcm = {
2154                 .omap4 = {
2155                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2156                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2157                         .modulemode   = MODULEMODE_SWCTRL,
2158                 },
2159         },
2160         .dev_attr       = &mcspi1_dev_attr,
2161 };
2162
2163 /* mcspi2 */
2164 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2165         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2166         { .irq = -1 }
2167 };
2168
2169 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2170         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2171         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2172         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2173         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2174         { .dma_req = -1 }
2175 };
2176
2177 /* mcspi2 dev_attr */
2178 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2179         .num_chipselect = 2,
2180 };
2181
2182 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2183         .name           = "mcspi2",
2184         .class          = &omap44xx_mcspi_hwmod_class,
2185         .clkdm_name     = "l4_per_clkdm",
2186         .mpu_irqs       = omap44xx_mcspi2_irqs,
2187         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2188         .main_clk       = "mcspi2_fck",
2189         .prcm = {
2190                 .omap4 = {
2191                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2192                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2193                         .modulemode   = MODULEMODE_SWCTRL,
2194                 },
2195         },
2196         .dev_attr       = &mcspi2_dev_attr,
2197 };
2198
2199 /* mcspi3 */
2200 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2201         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2202         { .irq = -1 }
2203 };
2204
2205 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2206         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2207         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2208         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2209         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2210         { .dma_req = -1 }
2211 };
2212
2213 /* mcspi3 dev_attr */
2214 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2215         .num_chipselect = 2,
2216 };
2217
2218 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2219         .name           = "mcspi3",
2220         .class          = &omap44xx_mcspi_hwmod_class,
2221         .clkdm_name     = "l4_per_clkdm",
2222         .mpu_irqs       = omap44xx_mcspi3_irqs,
2223         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2224         .main_clk       = "mcspi3_fck",
2225         .prcm = {
2226                 .omap4 = {
2227                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2228                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2229                         .modulemode   = MODULEMODE_SWCTRL,
2230                 },
2231         },
2232         .dev_attr       = &mcspi3_dev_attr,
2233 };
2234
2235 /* mcspi4 */
2236 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2237         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2238         { .irq = -1 }
2239 };
2240
2241 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2242         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2243         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2244         { .dma_req = -1 }
2245 };
2246
2247 /* mcspi4 dev_attr */
2248 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2249         .num_chipselect = 1,
2250 };
2251
2252 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2253         .name           = "mcspi4",
2254         .class          = &omap44xx_mcspi_hwmod_class,
2255         .clkdm_name     = "l4_per_clkdm",
2256         .mpu_irqs       = omap44xx_mcspi4_irqs,
2257         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2258         .main_clk       = "mcspi4_fck",
2259         .prcm = {
2260                 .omap4 = {
2261                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2262                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2263                         .modulemode   = MODULEMODE_SWCTRL,
2264                 },
2265         },
2266         .dev_attr       = &mcspi4_dev_attr,
2267 };
2268
2269 /*
2270  * 'mmc' class
2271  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2272  */
2273
2274 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2275         .rev_offs       = 0x0000,
2276         .sysc_offs      = 0x0010,
2277         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2278                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2279                            SYSC_HAS_SOFTRESET),
2280         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2281                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2282                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2283         .sysc_fields    = &omap_hwmod_sysc_type2,
2284 };
2285
2286 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2287         .name   = "mmc",
2288         .sysc   = &omap44xx_mmc_sysc,
2289 };
2290
2291 /* mmc1 */
2292 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2293         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2294         { .irq = -1 }
2295 };
2296
2297 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2298         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2299         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2300         { .dma_req = -1 }
2301 };
2302
2303 /* mmc1 dev_attr */
2304 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2305         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2306 };
2307
2308 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2309         .name           = "mmc1",
2310         .class          = &omap44xx_mmc_hwmod_class,
2311         .clkdm_name     = "l3_init_clkdm",
2312         .mpu_irqs       = omap44xx_mmc1_irqs,
2313         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2314         .main_clk       = "mmc1_fck",
2315         .prcm = {
2316                 .omap4 = {
2317                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2318                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2319                         .modulemode   = MODULEMODE_SWCTRL,
2320                 },
2321         },
2322         .dev_attr       = &mmc1_dev_attr,
2323 };
2324
2325 /* mmc2 */
2326 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2327         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2328         { .irq = -1 }
2329 };
2330
2331 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2332         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2333         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2334         { .dma_req = -1 }
2335 };
2336
2337 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2338         .name           = "mmc2",
2339         .class          = &omap44xx_mmc_hwmod_class,
2340         .clkdm_name     = "l3_init_clkdm",
2341         .mpu_irqs       = omap44xx_mmc2_irqs,
2342         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2343         .main_clk       = "mmc2_fck",
2344         .prcm = {
2345                 .omap4 = {
2346                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2347                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2348                         .modulemode   = MODULEMODE_SWCTRL,
2349                 },
2350         },
2351 };
2352
2353 /* mmc3 */
2354 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2355         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2356         { .irq = -1 }
2357 };
2358
2359 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2360         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2361         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2362         { .dma_req = -1 }
2363 };
2364
2365 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2366         .name           = "mmc3",
2367         .class          = &omap44xx_mmc_hwmod_class,
2368         .clkdm_name     = "l4_per_clkdm",
2369         .mpu_irqs       = omap44xx_mmc3_irqs,
2370         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2371         .main_clk       = "mmc3_fck",
2372         .prcm = {
2373                 .omap4 = {
2374                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2375                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2376                         .modulemode   = MODULEMODE_SWCTRL,
2377                 },
2378         },
2379 };
2380
2381 /* mmc4 */
2382 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2383         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2384         { .irq = -1 }
2385 };
2386
2387 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2388         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2389         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2390         { .dma_req = -1 }
2391 };
2392
2393 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2394         .name           = "mmc4",
2395         .class          = &omap44xx_mmc_hwmod_class,
2396         .clkdm_name     = "l4_per_clkdm",
2397         .mpu_irqs       = omap44xx_mmc4_irqs,
2398         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2399         .main_clk       = "mmc4_fck",
2400         .prcm = {
2401                 .omap4 = {
2402                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2403                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2404                         .modulemode   = MODULEMODE_SWCTRL,
2405                 },
2406         },
2407 };
2408
2409 /* mmc5 */
2410 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2411         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2412         { .irq = -1 }
2413 };
2414
2415 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2416         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2417         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2418         { .dma_req = -1 }
2419 };
2420
2421 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2422         .name           = "mmc5",
2423         .class          = &omap44xx_mmc_hwmod_class,
2424         .clkdm_name     = "l4_per_clkdm",
2425         .mpu_irqs       = omap44xx_mmc5_irqs,
2426         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2427         .main_clk       = "mmc5_fck",
2428         .prcm = {
2429                 .omap4 = {
2430                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2431                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2432                         .modulemode   = MODULEMODE_SWCTRL,
2433                 },
2434         },
2435 };
2436
2437 /*
2438  * 'mpu' class
2439  * mpu sub-system
2440  */
2441
2442 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2443         .name   = "mpu",
2444 };
2445
2446 /* mpu */
2447 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2448         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2449         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2450         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2451         { .irq = -1 }
2452 };
2453
2454 static struct omap_hwmod omap44xx_mpu_hwmod = {
2455         .name           = "mpu",
2456         .class          = &omap44xx_mpu_hwmod_class,
2457         .clkdm_name     = "mpuss_clkdm",
2458         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2459         .mpu_irqs       = omap44xx_mpu_irqs,
2460         .main_clk       = "dpll_mpu_m2_ck",
2461         .prcm = {
2462                 .omap4 = {
2463                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2464                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2465                 },
2466         },
2467 };
2468
2469 /*
2470  * 'ocmc_ram' class
2471  * top-level core on-chip ram
2472  */
2473
2474 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2475         .name   = "ocmc_ram",
2476 };
2477
2478 /* ocmc_ram */
2479 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2480         .name           = "ocmc_ram",
2481         .class          = &omap44xx_ocmc_ram_hwmod_class,
2482         .clkdm_name     = "l3_2_clkdm",
2483         .prcm = {
2484                 .omap4 = {
2485                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2486                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2487                 },
2488         },
2489 };
2490
2491 /*
2492  * 'ocp2scp' class
2493  * bridge to transform ocp interface protocol to scp (serial control port)
2494  * protocol
2495  */
2496
2497 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2498         .name   = "ocp2scp",
2499 };
2500
2501 /* ocp2scp_usb_phy */
2502 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2503         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2504 };
2505
2506 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2507         .name           = "ocp2scp_usb_phy",
2508         .class          = &omap44xx_ocp2scp_hwmod_class,
2509         .clkdm_name     = "l3_init_clkdm",
2510         .prcm = {
2511                 .omap4 = {
2512                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2513                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2514                         .modulemode   = MODULEMODE_HWCTRL,
2515                 },
2516         },
2517         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2518         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2519 };
2520
2521 /*
2522  * 'prcm' class
2523  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2524  * + clock manager 1 (in always on power domain) + local prm in mpu
2525  */
2526
2527 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2528         .name   = "prcm",
2529 };
2530
2531 /* prcm_mpu */
2532 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2533         .name           = "prcm_mpu",
2534         .class          = &omap44xx_prcm_hwmod_class,
2535         .clkdm_name     = "l4_wkup_clkdm",
2536 };
2537
2538 /* cm_core_aon */
2539 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2540         .name           = "cm_core_aon",
2541         .class          = &omap44xx_prcm_hwmod_class,
2542         .clkdm_name     = "cm_clkdm",
2543 };
2544
2545 /* cm_core */
2546 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2547         .name           = "cm_core",
2548         .class          = &omap44xx_prcm_hwmod_class,
2549         .clkdm_name     = "cm_clkdm",
2550 };
2551
2552 /* prm */
2553 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2554         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2555         { .irq = -1 }
2556 };
2557
2558 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2559         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2560         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2561 };
2562
2563 static struct omap_hwmod omap44xx_prm_hwmod = {
2564         .name           = "prm",
2565         .class          = &omap44xx_prcm_hwmod_class,
2566         .clkdm_name     = "prm_clkdm",
2567         .mpu_irqs       = omap44xx_prm_irqs,
2568         .rst_lines      = omap44xx_prm_resets,
2569         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2570 };
2571
2572 /*
2573  * 'scrm' class
2574  * system clock and reset manager
2575  */
2576
2577 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2578         .name   = "scrm",
2579 };
2580
2581 /* scrm */
2582 static struct omap_hwmod omap44xx_scrm_hwmod = {
2583         .name           = "scrm",
2584         .class          = &omap44xx_scrm_hwmod_class,
2585         .clkdm_name     = "l4_wkup_clkdm",
2586 };
2587
2588 /*
2589  * 'sl2if' class
2590  * shared level 2 memory interface
2591  */
2592
2593 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2594         .name   = "sl2if",
2595 };
2596
2597 /* sl2if */
2598 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2599         .name           = "sl2if",
2600         .class          = &omap44xx_sl2if_hwmod_class,
2601         .clkdm_name     = "ivahd_clkdm",
2602         .prcm = {
2603                 .omap4 = {
2604                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2605                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2606                         .modulemode   = MODULEMODE_HWCTRL,
2607                 },
2608         },
2609 };
2610
2611 /*
2612  * 'slimbus' class
2613  * bidirectional, multi-drop, multi-channel two-line serial interface between
2614  * the device and external components
2615  */
2616
2617 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2618         .rev_offs       = 0x0000,
2619         .sysc_offs      = 0x0010,
2620         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2621                            SYSC_HAS_SOFTRESET),
2622         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2623                            SIDLE_SMART_WKUP),
2624         .sysc_fields    = &omap_hwmod_sysc_type2,
2625 };
2626
2627 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2628         .name   = "slimbus",
2629         .sysc   = &omap44xx_slimbus_sysc,
2630 };
2631
2632 /* slimbus1 */
2633 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2634         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2635         { .irq = -1 }
2636 };
2637
2638 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2639         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2640         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2641         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2642         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2643         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2644         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2645         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2646         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2647         { .dma_req = -1 }
2648 };
2649
2650 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2651         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2652         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2653         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2654         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2655 };
2656
2657 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2658         .name           = "slimbus1",
2659         .class          = &omap44xx_slimbus_hwmod_class,
2660         .clkdm_name     = "abe_clkdm",
2661         .mpu_irqs       = omap44xx_slimbus1_irqs,
2662         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2663         .prcm = {
2664                 .omap4 = {
2665                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2666                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2667                         .modulemode   = MODULEMODE_SWCTRL,
2668                 },
2669         },
2670         .opt_clks       = slimbus1_opt_clks,
2671         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2672 };
2673
2674 /* slimbus2 */
2675 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2676         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2677         { .irq = -1 }
2678 };
2679
2680 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2681         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2682         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2683         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2684         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2685         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2686         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2687         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2688         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2689         { .dma_req = -1 }
2690 };
2691
2692 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2693         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2694         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2695         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2696 };
2697
2698 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2699         .name           = "slimbus2",
2700         .class          = &omap44xx_slimbus_hwmod_class,
2701         .clkdm_name     = "l4_per_clkdm",
2702         .mpu_irqs       = omap44xx_slimbus2_irqs,
2703         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2704         .prcm = {
2705                 .omap4 = {
2706                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2707                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2708                         .modulemode   = MODULEMODE_SWCTRL,
2709                 },
2710         },
2711         .opt_clks       = slimbus2_opt_clks,
2712         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2713 };
2714
2715 /*
2716  * 'smartreflex' class
2717  * smartreflex module (monitor silicon performance and outputs a measure of
2718  * performance error)
2719  */
2720
2721 /* The IP is not compliant to type1 / type2 scheme */
2722 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2723         .sidle_shift    = 24,
2724         .enwkup_shift   = 26,
2725 };
2726
2727 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2728         .sysc_offs      = 0x0038,
2729         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2731                            SIDLE_SMART_WKUP),
2732         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2733 };
2734
2735 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2736         .name   = "smartreflex",
2737         .sysc   = &omap44xx_smartreflex_sysc,
2738         .rev    = 2,
2739 };
2740
2741 /* smartreflex_core */
2742 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2743         .sensor_voltdm_name   = "core",
2744 };
2745
2746 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2747         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2748         { .irq = -1 }
2749 };
2750
2751 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2752         .name           = "smartreflex_core",
2753         .class          = &omap44xx_smartreflex_hwmod_class,
2754         .clkdm_name     = "l4_ao_clkdm",
2755         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2756
2757         .main_clk       = "smartreflex_core_fck",
2758         .prcm = {
2759                 .omap4 = {
2760                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2761                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2762                         .modulemode   = MODULEMODE_SWCTRL,
2763                 },
2764         },
2765         .dev_attr       = &smartreflex_core_dev_attr,
2766 };
2767
2768 /* smartreflex_iva */
2769 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2770         .sensor_voltdm_name     = "iva",
2771 };
2772
2773 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2774         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2775         { .irq = -1 }
2776 };
2777
2778 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2779         .name           = "smartreflex_iva",
2780         .class          = &omap44xx_smartreflex_hwmod_class,
2781         .clkdm_name     = "l4_ao_clkdm",
2782         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2783         .main_clk       = "smartreflex_iva_fck",
2784         .prcm = {
2785                 .omap4 = {
2786                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2787                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2788                         .modulemode   = MODULEMODE_SWCTRL,
2789                 },
2790         },
2791         .dev_attr       = &smartreflex_iva_dev_attr,
2792 };
2793
2794 /* smartreflex_mpu */
2795 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2796         .sensor_voltdm_name     = "mpu",
2797 };
2798
2799 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2800         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2801         { .irq = -1 }
2802 };
2803
2804 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2805         .name           = "smartreflex_mpu",
2806         .class          = &omap44xx_smartreflex_hwmod_class,
2807         .clkdm_name     = "l4_ao_clkdm",
2808         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2809         .main_clk       = "smartreflex_mpu_fck",
2810         .prcm = {
2811                 .omap4 = {
2812                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2813                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2814                         .modulemode   = MODULEMODE_SWCTRL,
2815                 },
2816         },
2817         .dev_attr       = &smartreflex_mpu_dev_attr,
2818 };
2819
2820 /*
2821  * 'spinlock' class
2822  * spinlock provides hardware assistance for synchronizing the processes
2823  * running on multiple processors
2824  */
2825
2826 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2827         .rev_offs       = 0x0000,
2828         .sysc_offs      = 0x0010,
2829         .syss_offs      = 0x0014,
2830         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2831                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2832                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2833         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2834                            SIDLE_SMART_WKUP),
2835         .sysc_fields    = &omap_hwmod_sysc_type1,
2836 };
2837
2838 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2839         .name   = "spinlock",
2840         .sysc   = &omap44xx_spinlock_sysc,
2841 };
2842
2843 /* spinlock */
2844 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2845         .name           = "spinlock",
2846         .class          = &omap44xx_spinlock_hwmod_class,
2847         .clkdm_name     = "l4_cfg_clkdm",
2848         .prcm = {
2849                 .omap4 = {
2850                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2851                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2852                 },
2853         },
2854 };
2855
2856 /*
2857  * 'timer' class
2858  * general purpose timer module with accurate 1ms tick
2859  * This class contains several variants: ['timer_1ms', 'timer']
2860  */
2861
2862 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2863         .rev_offs       = 0x0000,
2864         .sysc_offs      = 0x0010,
2865         .syss_offs      = 0x0014,
2866         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2867                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2868                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2869                            SYSS_HAS_RESET_STATUS),
2870         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2871         .sysc_fields    = &omap_hwmod_sysc_type1,
2872 };
2873
2874 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2875         .name   = "timer",
2876         .sysc   = &omap44xx_timer_1ms_sysc,
2877 };
2878
2879 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2880         .rev_offs       = 0x0000,
2881         .sysc_offs      = 0x0010,
2882         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2883                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2884         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2885                            SIDLE_SMART_WKUP),
2886         .sysc_fields    = &omap_hwmod_sysc_type2,
2887 };
2888
2889 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2890         .name   = "timer",
2891         .sysc   = &omap44xx_timer_sysc,
2892 };
2893
2894 /* always-on timers dev attribute */
2895 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2896         .timer_capability       = OMAP_TIMER_ALWON,
2897 };
2898
2899 /* pwm timers dev attribute */
2900 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2901         .timer_capability       = OMAP_TIMER_HAS_PWM,
2902 };
2903
2904 /* timer1 */
2905 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2906         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2907         { .irq = -1 }
2908 };
2909
2910 static struct omap_hwmod omap44xx_timer1_hwmod = {
2911         .name           = "timer1",
2912         .class          = &omap44xx_timer_1ms_hwmod_class,
2913         .clkdm_name     = "l4_wkup_clkdm",
2914         .mpu_irqs       = omap44xx_timer1_irqs,
2915         .main_clk       = "timer1_fck",
2916         .prcm = {
2917                 .omap4 = {
2918                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2919                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2920                         .modulemode   = MODULEMODE_SWCTRL,
2921                 },
2922         },
2923         .dev_attr       = &capability_alwon_dev_attr,
2924 };
2925
2926 /* timer2 */
2927 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2928         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2929         { .irq = -1 }
2930 };
2931
2932 static struct omap_hwmod omap44xx_timer2_hwmod = {
2933         .name           = "timer2",
2934         .class          = &omap44xx_timer_1ms_hwmod_class,
2935         .clkdm_name     = "l4_per_clkdm",
2936         .mpu_irqs       = omap44xx_timer2_irqs,
2937         .main_clk       = "timer2_fck",
2938         .prcm = {
2939                 .omap4 = {
2940                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2941                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2942                         .modulemode   = MODULEMODE_SWCTRL,
2943                 },
2944         },
2945         .dev_attr       = &capability_alwon_dev_attr,
2946 };
2947
2948 /* timer3 */
2949 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2950         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2951         { .irq = -1 }
2952 };
2953
2954 static struct omap_hwmod omap44xx_timer3_hwmod = {
2955         .name           = "timer3",
2956         .class          = &omap44xx_timer_hwmod_class,
2957         .clkdm_name     = "l4_per_clkdm",
2958         .mpu_irqs       = omap44xx_timer3_irqs,
2959         .main_clk       = "timer3_fck",
2960         .prcm = {
2961                 .omap4 = {
2962                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2963                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2964                         .modulemode   = MODULEMODE_SWCTRL,
2965                 },
2966         },
2967         .dev_attr       = &capability_alwon_dev_attr,
2968 };
2969
2970 /* timer4 */
2971 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2972         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2973         { .irq = -1 }
2974 };
2975
2976 static struct omap_hwmod omap44xx_timer4_hwmod = {
2977         .name           = "timer4",
2978         .class          = &omap44xx_timer_hwmod_class,
2979         .clkdm_name     = "l4_per_clkdm",
2980         .mpu_irqs       = omap44xx_timer4_irqs,
2981         .main_clk       = "timer4_fck",
2982         .prcm = {
2983                 .omap4 = {
2984                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2985                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2986                         .modulemode   = MODULEMODE_SWCTRL,
2987                 },
2988         },
2989         .dev_attr       = &capability_alwon_dev_attr,
2990 };
2991
2992 /* timer5 */
2993 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2994         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2995         { .irq = -1 }
2996 };
2997
2998 static struct omap_hwmod omap44xx_timer5_hwmod = {
2999         .name           = "timer5",
3000         .class          = &omap44xx_timer_hwmod_class,
3001         .clkdm_name     = "abe_clkdm",
3002         .mpu_irqs       = omap44xx_timer5_irqs,
3003         .main_clk       = "timer5_fck",
3004         .prcm = {
3005                 .omap4 = {
3006                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3007                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3008                         .modulemode   = MODULEMODE_SWCTRL,
3009                 },
3010         },
3011         .dev_attr       = &capability_alwon_dev_attr,
3012 };
3013
3014 /* timer6 */
3015 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3016         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3017         { .irq = -1 }
3018 };
3019
3020 static struct omap_hwmod omap44xx_timer6_hwmod = {
3021         .name           = "timer6",
3022         .class          = &omap44xx_timer_hwmod_class,
3023         .clkdm_name     = "abe_clkdm",
3024         .mpu_irqs       = omap44xx_timer6_irqs,
3025
3026         .main_clk       = "timer6_fck",
3027         .prcm = {
3028                 .omap4 = {
3029                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3030                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3031                         .modulemode   = MODULEMODE_SWCTRL,
3032                 },
3033         },
3034         .dev_attr       = &capability_alwon_dev_attr,
3035 };
3036
3037 /* timer7 */
3038 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3039         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3040         { .irq = -1 }
3041 };
3042
3043 static struct omap_hwmod omap44xx_timer7_hwmod = {
3044         .name           = "timer7",
3045         .class          = &omap44xx_timer_hwmod_class,
3046         .clkdm_name     = "abe_clkdm",
3047         .mpu_irqs       = omap44xx_timer7_irqs,
3048         .main_clk       = "timer7_fck",
3049         .prcm = {
3050                 .omap4 = {
3051                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3052                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3053                         .modulemode   = MODULEMODE_SWCTRL,
3054                 },
3055         },
3056         .dev_attr       = &capability_alwon_dev_attr,
3057 };
3058
3059 /* timer8 */
3060 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3061         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3062         { .irq = -1 }
3063 };
3064
3065 static struct omap_hwmod omap44xx_timer8_hwmod = {
3066         .name           = "timer8",
3067         .class          = &omap44xx_timer_hwmod_class,
3068         .clkdm_name     = "abe_clkdm",
3069         .mpu_irqs       = omap44xx_timer8_irqs,
3070         .main_clk       = "timer8_fck",
3071         .prcm = {
3072                 .omap4 = {
3073                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3074                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3075                         .modulemode   = MODULEMODE_SWCTRL,
3076                 },
3077         },
3078         .dev_attr       = &capability_pwm_dev_attr,
3079 };
3080
3081 /* timer9 */
3082 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3083         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3084         { .irq = -1 }
3085 };
3086
3087 static struct omap_hwmod omap44xx_timer9_hwmod = {
3088         .name           = "timer9",
3089         .class          = &omap44xx_timer_hwmod_class,
3090         .clkdm_name     = "l4_per_clkdm",
3091         .mpu_irqs       = omap44xx_timer9_irqs,
3092         .main_clk       = "timer9_fck",
3093         .prcm = {
3094                 .omap4 = {
3095                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3096                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3097                         .modulemode   = MODULEMODE_SWCTRL,
3098                 },
3099         },
3100         .dev_attr       = &capability_pwm_dev_attr,
3101 };
3102
3103 /* timer10 */
3104 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3105         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3106         { .irq = -1 }
3107 };
3108
3109 static struct omap_hwmod omap44xx_timer10_hwmod = {
3110         .name           = "timer10",
3111         .class          = &omap44xx_timer_1ms_hwmod_class,
3112         .clkdm_name     = "l4_per_clkdm",
3113         .mpu_irqs       = omap44xx_timer10_irqs,
3114         .main_clk       = "timer10_fck",
3115         .prcm = {
3116                 .omap4 = {
3117                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3118                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3119                         .modulemode   = MODULEMODE_SWCTRL,
3120                 },
3121         },
3122         .dev_attr       = &capability_pwm_dev_attr,
3123 };
3124
3125 /* timer11 */
3126 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3127         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3128         { .irq = -1 }
3129 };
3130
3131 static struct omap_hwmod omap44xx_timer11_hwmod = {
3132         .name           = "timer11",
3133         .class          = &omap44xx_timer_hwmod_class,
3134         .clkdm_name     = "l4_per_clkdm",
3135         .mpu_irqs       = omap44xx_timer11_irqs,
3136         .main_clk       = "timer11_fck",
3137         .prcm = {
3138                 .omap4 = {
3139                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3140                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3141                         .modulemode   = MODULEMODE_SWCTRL,
3142                 },
3143         },
3144         .dev_attr       = &capability_pwm_dev_attr,
3145 };
3146
3147 /*
3148  * 'uart' class
3149  * universal asynchronous receiver/transmitter (uart)
3150  */
3151
3152 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3153         .rev_offs       = 0x0050,
3154         .sysc_offs      = 0x0054,
3155         .syss_offs      = 0x0058,
3156         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3157                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3158                            SYSS_HAS_RESET_STATUS),
3159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3160                            SIDLE_SMART_WKUP),
3161         .sysc_fields    = &omap_hwmod_sysc_type1,
3162 };
3163
3164 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3165         .name   = "uart",
3166         .sysc   = &omap44xx_uart_sysc,
3167 };
3168
3169 /* uart1 */
3170 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3171         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3172         { .irq = -1 }
3173 };
3174
3175 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3176         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3177         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3178         { .dma_req = -1 }
3179 };
3180
3181 static struct omap_hwmod omap44xx_uart1_hwmod = {
3182         .name           = "uart1",
3183         .class          = &omap44xx_uart_hwmod_class,
3184         .clkdm_name     = "l4_per_clkdm",
3185         .mpu_irqs       = omap44xx_uart1_irqs,
3186         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3187         .main_clk       = "uart1_fck",
3188         .prcm = {
3189                 .omap4 = {
3190                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3191                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3192                         .modulemode   = MODULEMODE_SWCTRL,
3193                 },
3194         },
3195 };
3196
3197 /* uart2 */
3198 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3199         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3200         { .irq = -1 }
3201 };
3202
3203 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3204         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3205         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3206         { .dma_req = -1 }
3207 };
3208
3209 static struct omap_hwmod omap44xx_uart2_hwmod = {
3210         .name           = "uart2",
3211         .class          = &omap44xx_uart_hwmod_class,
3212         .clkdm_name     = "l4_per_clkdm",
3213         .mpu_irqs       = omap44xx_uart2_irqs,
3214         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3215         .main_clk       = "uart2_fck",
3216         .prcm = {
3217                 .omap4 = {
3218                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3219                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3220                         .modulemode   = MODULEMODE_SWCTRL,
3221                 },
3222         },
3223 };
3224
3225 /* uart3 */
3226 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3227         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3228         { .irq = -1 }
3229 };
3230
3231 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3232         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3233         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3234         { .dma_req = -1 }
3235 };
3236
3237 static struct omap_hwmod omap44xx_uart3_hwmod = {
3238         .name           = "uart3",
3239         .class          = &omap44xx_uart_hwmod_class,
3240         .clkdm_name     = "l4_per_clkdm",
3241         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3242         .mpu_irqs       = omap44xx_uart3_irqs,
3243         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3244         .main_clk       = "uart3_fck",
3245         .prcm = {
3246                 .omap4 = {
3247                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3248                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3249                         .modulemode   = MODULEMODE_SWCTRL,
3250                 },
3251         },
3252 };
3253
3254 /* uart4 */
3255 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3256         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3257         { .irq = -1 }
3258 };
3259
3260 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3261         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3262         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3263         { .dma_req = -1 }
3264 };
3265
3266 static struct omap_hwmod omap44xx_uart4_hwmod = {
3267         .name           = "uart4",
3268         .class          = &omap44xx_uart_hwmod_class,
3269         .clkdm_name     = "l4_per_clkdm",
3270         .mpu_irqs       = omap44xx_uart4_irqs,
3271         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3272         .main_clk       = "uart4_fck",
3273         .prcm = {
3274                 .omap4 = {
3275                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3276                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3277                         .modulemode   = MODULEMODE_SWCTRL,
3278                 },
3279         },
3280 };
3281
3282 /*
3283  * 'usb_host_fs' class
3284  * full-speed usb host controller
3285  */
3286
3287 /* The IP is not compliant to type1 / type2 scheme */
3288 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3289         .midle_shift    = 4,
3290         .sidle_shift    = 2,
3291         .srst_shift     = 1,
3292 };
3293
3294 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3295         .rev_offs       = 0x0000,
3296         .sysc_offs      = 0x0210,
3297         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3298                            SYSC_HAS_SOFTRESET),
3299         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3300                            SIDLE_SMART_WKUP),
3301         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3302 };
3303
3304 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3305         .name   = "usb_host_fs",
3306         .sysc   = &omap44xx_usb_host_fs_sysc,
3307 };
3308
3309 /* usb_host_fs */
3310 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3311         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3312         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3313         { .irq = -1 }
3314 };
3315
3316 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3317         .name           = "usb_host_fs",
3318         .class          = &omap44xx_usb_host_fs_hwmod_class,
3319         .clkdm_name     = "l3_init_clkdm",
3320         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3321         .main_clk       = "usb_host_fs_fck",
3322         .prcm = {
3323                 .omap4 = {
3324                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3325                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3326                         .modulemode   = MODULEMODE_SWCTRL,
3327                 },
3328         },
3329 };
3330
3331 /*
3332  * 'usb_host_hs' class
3333  * high-speed multi-port usb host controller
3334  */
3335
3336 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3337         .rev_offs       = 0x0000,
3338         .sysc_offs      = 0x0010,
3339         .syss_offs      = 0x0014,
3340         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3341                            SYSC_HAS_SOFTRESET),
3342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3343                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3344                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3345         .sysc_fields    = &omap_hwmod_sysc_type2,
3346 };
3347
3348 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3349         .name   = "usb_host_hs",
3350         .sysc   = &omap44xx_usb_host_hs_sysc,
3351 };
3352
3353 /* usb_host_hs */
3354 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3355         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3356         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3357         { .irq = -1 }
3358 };
3359
3360 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3361         .name           = "usb_host_hs",
3362         .class          = &omap44xx_usb_host_hs_hwmod_class,
3363         .clkdm_name     = "l3_init_clkdm",
3364         .main_clk       = "usb_host_hs_fck",
3365         .prcm = {
3366                 .omap4 = {
3367                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3368                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3369                         .modulemode   = MODULEMODE_SWCTRL,
3370                 },
3371         },
3372         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3373
3374         /*
3375          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3376          * id: i660
3377          *
3378          * Description:
3379          * In the following configuration :
3380          * - USBHOST module is set to smart-idle mode
3381          * - PRCM asserts idle_req to the USBHOST module ( This typically
3382          *   happens when the system is going to a low power mode : all ports
3383          *   have been suspended, the master part of the USBHOST module has
3384          *   entered the standby state, and SW has cut the functional clocks)
3385          * - an USBHOST interrupt occurs before the module is able to answer
3386          *   idle_ack, typically a remote wakeup IRQ.
3387          * Then the USB HOST module will enter a deadlock situation where it
3388          * is no more accessible nor functional.
3389          *
3390          * Workaround:
3391          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3392          */
3393
3394         /*
3395          * Errata: USB host EHCI may stall when entering smart-standby mode
3396          * Id: i571
3397          *
3398          * Description:
3399          * When the USBHOST module is set to smart-standby mode, and when it is
3400          * ready to enter the standby state (i.e. all ports are suspended and
3401          * all attached devices are in suspend mode), then it can wrongly assert
3402          * the Mstandby signal too early while there are still some residual OCP
3403          * transactions ongoing. If this condition occurs, the internal state
3404          * machine may go to an undefined state and the USB link may be stuck
3405          * upon the next resume.
3406          *
3407          * Workaround:
3408          * Don't use smart standby; use only force standby,
3409          * hence HWMOD_SWSUP_MSTANDBY
3410          */
3411
3412         /*
3413          * During system boot; If the hwmod framework resets the module
3414          * the module will have smart idle settings; which can lead to deadlock
3415          * (above Errata Id:i660); so, dont reset the module during boot;
3416          * Use HWMOD_INIT_NO_RESET.
3417          */
3418
3419         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3420                           HWMOD_INIT_NO_RESET,
3421 };
3422
3423 /*
3424  * 'usb_otg_hs' class
3425  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3426  */
3427
3428 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3429         .rev_offs       = 0x0400,
3430         .sysc_offs      = 0x0404,
3431         .syss_offs      = 0x0408,
3432         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3433                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3434                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3435         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3436                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3437                            MSTANDBY_SMART),
3438         .sysc_fields    = &omap_hwmod_sysc_type1,
3439 };
3440
3441 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3442         .name   = "usb_otg_hs",
3443         .sysc   = &omap44xx_usb_otg_hs_sysc,
3444 };
3445
3446 /* usb_otg_hs */
3447 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3448         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3449         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3450         { .irq = -1 }
3451 };
3452
3453 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3454         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3455 };
3456
3457 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3458         .name           = "usb_otg_hs",
3459         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3460         .clkdm_name     = "l3_init_clkdm",
3461         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3462         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3463         .main_clk       = "usb_otg_hs_ick",
3464         .prcm = {
3465                 .omap4 = {
3466                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3467                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3468                         .modulemode   = MODULEMODE_HWCTRL,
3469                 },
3470         },
3471         .opt_clks       = usb_otg_hs_opt_clks,
3472         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3473 };
3474
3475 /*
3476  * 'usb_tll_hs' class
3477  * usb_tll_hs module is the adapter on the usb_host_hs ports
3478  */
3479
3480 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3481         .rev_offs       = 0x0000,
3482         .sysc_offs      = 0x0010,
3483         .syss_offs      = 0x0014,
3484         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3485                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3486                            SYSC_HAS_AUTOIDLE),
3487         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3488         .sysc_fields    = &omap_hwmod_sysc_type1,
3489 };
3490
3491 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3492         .name   = "usb_tll_hs",
3493         .sysc   = &omap44xx_usb_tll_hs_sysc,
3494 };
3495
3496 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3497         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3498         { .irq = -1 }
3499 };
3500
3501 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3502         .name           = "usb_tll_hs",
3503         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3504         .clkdm_name     = "l3_init_clkdm",
3505         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3506         .main_clk       = "usb_tll_hs_ick",
3507         .prcm = {
3508                 .omap4 = {
3509                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3510                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3511                         .modulemode   = MODULEMODE_HWCTRL,
3512                 },
3513         },
3514 };
3515
3516 /*
3517  * 'wd_timer' class
3518  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3519  * overflow condition
3520  */
3521
3522 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3523         .rev_offs       = 0x0000,
3524         .sysc_offs      = 0x0010,
3525         .syss_offs      = 0x0014,
3526         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3527                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3528         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3529                            SIDLE_SMART_WKUP),
3530         .sysc_fields    = &omap_hwmod_sysc_type1,
3531 };
3532
3533 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3534         .name           = "wd_timer",
3535         .sysc           = &omap44xx_wd_timer_sysc,
3536         .pre_shutdown   = &omap2_wd_timer_disable,
3537 };
3538
3539 /* wd_timer2 */
3540 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3541         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3542         { .irq = -1 }
3543 };
3544
3545 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3546         .name           = "wd_timer2",
3547         .class          = &omap44xx_wd_timer_hwmod_class,
3548         .clkdm_name     = "l4_wkup_clkdm",
3549         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3550         .main_clk       = "wd_timer2_fck",
3551         .prcm = {
3552                 .omap4 = {
3553                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3554                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3555                         .modulemode   = MODULEMODE_SWCTRL,
3556                 },
3557         },
3558 };
3559
3560 /* wd_timer3 */
3561 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3562         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3563         { .irq = -1 }
3564 };
3565
3566 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3567         .name           = "wd_timer3",
3568         .class          = &omap44xx_wd_timer_hwmod_class,
3569         .clkdm_name     = "abe_clkdm",
3570         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3571         .main_clk       = "wd_timer3_fck",
3572         .prcm = {
3573                 .omap4 = {
3574                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3575                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3576                         .modulemode   = MODULEMODE_SWCTRL,
3577                 },
3578         },
3579 };
3580
3581
3582 /*
3583  * interfaces
3584  */
3585
3586 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3587         {
3588                 .pa_start       = 0x4a204000,
3589                 .pa_end         = 0x4a2040ff,
3590                 .flags          = ADDR_TYPE_RT
3591         },
3592         { }
3593 };
3594
3595 /* c2c -> c2c_target_fw */
3596 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3597         .master         = &omap44xx_c2c_hwmod,
3598         .slave          = &omap44xx_c2c_target_fw_hwmod,
3599         .clk            = "div_core_ck",
3600         .addr           = omap44xx_c2c_target_fw_addrs,
3601         .user           = OCP_USER_MPU,
3602 };
3603
3604 /* l4_cfg -> c2c_target_fw */
3605 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3606         .master         = &omap44xx_l4_cfg_hwmod,
3607         .slave          = &omap44xx_c2c_target_fw_hwmod,
3608         .clk            = "l4_div_ck",
3609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3610 };
3611
3612 /* l3_main_1 -> dmm */
3613 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3614         .master         = &omap44xx_l3_main_1_hwmod,
3615         .slave          = &omap44xx_dmm_hwmod,
3616         .clk            = "l3_div_ck",
3617         .user           = OCP_USER_SDMA,
3618 };
3619
3620 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3621         {
3622                 .pa_start       = 0x4e000000,
3623                 .pa_end         = 0x4e0007ff,
3624                 .flags          = ADDR_TYPE_RT
3625         },
3626         { }
3627 };
3628
3629 /* mpu -> dmm */
3630 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3631         .master         = &omap44xx_mpu_hwmod,
3632         .slave          = &omap44xx_dmm_hwmod,
3633         .clk            = "l3_div_ck",
3634         .addr           = omap44xx_dmm_addrs,
3635         .user           = OCP_USER_MPU,
3636 };
3637
3638 /* c2c -> emif_fw */
3639 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3640         .master         = &omap44xx_c2c_hwmod,
3641         .slave          = &omap44xx_emif_fw_hwmod,
3642         .clk            = "div_core_ck",
3643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3644 };
3645
3646 /* dmm -> emif_fw */
3647 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3648         .master         = &omap44xx_dmm_hwmod,
3649         .slave          = &omap44xx_emif_fw_hwmod,
3650         .clk            = "l3_div_ck",
3651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3652 };
3653
3654 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3655         {
3656                 .pa_start       = 0x4a20c000,
3657                 .pa_end         = 0x4a20c0ff,
3658                 .flags          = ADDR_TYPE_RT
3659         },
3660         { }
3661 };
3662
3663 /* l4_cfg -> emif_fw */
3664 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3665         .master         = &omap44xx_l4_cfg_hwmod,
3666         .slave          = &omap44xx_emif_fw_hwmod,
3667         .clk            = "l4_div_ck",
3668         .addr           = omap44xx_emif_fw_addrs,
3669         .user           = OCP_USER_MPU,
3670 };
3671
3672 /* iva -> l3_instr */
3673 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3674         .master         = &omap44xx_iva_hwmod,
3675         .slave          = &omap44xx_l3_instr_hwmod,
3676         .clk            = "l3_div_ck",
3677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3678 };
3679
3680 /* l3_main_3 -> l3_instr */
3681 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3682         .master         = &omap44xx_l3_main_3_hwmod,
3683         .slave          = &omap44xx_l3_instr_hwmod,
3684         .clk            = "l3_div_ck",
3685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3686 };
3687
3688 /* ocp_wp_noc -> l3_instr */
3689 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3690         .master         = &omap44xx_ocp_wp_noc_hwmod,
3691         .slave          = &omap44xx_l3_instr_hwmod,
3692         .clk            = "l3_div_ck",
3693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3694 };
3695
3696 /* dsp -> l3_main_1 */
3697 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3698         .master         = &omap44xx_dsp_hwmod,
3699         .slave          = &omap44xx_l3_main_1_hwmod,
3700         .clk            = "l3_div_ck",
3701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3702 };
3703
3704 /* dss -> l3_main_1 */
3705 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3706         .master         = &omap44xx_dss_hwmod,
3707         .slave          = &omap44xx_l3_main_1_hwmod,
3708         .clk            = "l3_div_ck",
3709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3710 };
3711
3712 /* l3_main_2 -> l3_main_1 */
3713 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3714         .master         = &omap44xx_l3_main_2_hwmod,
3715         .slave          = &omap44xx_l3_main_1_hwmod,
3716         .clk            = "l3_div_ck",
3717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3718 };
3719
3720 /* l4_cfg -> l3_main_1 */
3721 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3722         .master         = &omap44xx_l4_cfg_hwmod,
3723         .slave          = &omap44xx_l3_main_1_hwmod,
3724         .clk            = "l4_div_ck",
3725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3726 };
3727
3728 /* mmc1 -> l3_main_1 */
3729 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3730         .master         = &omap44xx_mmc1_hwmod,
3731         .slave          = &omap44xx_l3_main_1_hwmod,
3732         .clk            = "l3_div_ck",
3733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3734 };
3735
3736 /* mmc2 -> l3_main_1 */
3737 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3738         .master         = &omap44xx_mmc2_hwmod,
3739         .slave          = &omap44xx_l3_main_1_hwmod,
3740         .clk            = "l3_div_ck",
3741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3742 };
3743
3744 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3745         {
3746                 .pa_start       = 0x44000000,
3747                 .pa_end         = 0x44000fff,
3748                 .flags          = ADDR_TYPE_RT
3749         },
3750         { }
3751 };
3752
3753 /* mpu -> l3_main_1 */
3754 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3755         .master         = &omap44xx_mpu_hwmod,
3756         .slave          = &omap44xx_l3_main_1_hwmod,
3757         .clk            = "l3_div_ck",
3758         .addr           = omap44xx_l3_main_1_addrs,
3759         .user           = OCP_USER_MPU,
3760 };
3761
3762 /* c2c_target_fw -> l3_main_2 */
3763 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3764         .master         = &omap44xx_c2c_target_fw_hwmod,
3765         .slave          = &omap44xx_l3_main_2_hwmod,
3766         .clk            = "l3_div_ck",
3767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3768 };
3769
3770 /* debugss -> l3_main_2 */
3771 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3772         .master         = &omap44xx_debugss_hwmod,
3773         .slave          = &omap44xx_l3_main_2_hwmod,
3774         .clk            = "dbgclk_mux_ck",
3775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3776 };
3777
3778 /* dma_system -> l3_main_2 */
3779 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3780         .master         = &omap44xx_dma_system_hwmod,
3781         .slave          = &omap44xx_l3_main_2_hwmod,
3782         .clk            = "l3_div_ck",
3783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3785
3786 /* fdif -> l3_main_2 */
3787 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3788         .master         = &omap44xx_fdif_hwmod,
3789         .slave          = &omap44xx_l3_main_2_hwmod,
3790         .clk            = "l3_div_ck",
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* gpu -> l3_main_2 */
3795 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3796         .master         = &omap44xx_gpu_hwmod,
3797         .slave          = &omap44xx_l3_main_2_hwmod,
3798         .clk            = "l3_div_ck",
3799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3801
3802 /* hsi -> l3_main_2 */
3803 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3804         .master         = &omap44xx_hsi_hwmod,
3805         .slave          = &omap44xx_l3_main_2_hwmod,
3806         .clk            = "l3_div_ck",
3807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3808 };
3809
3810 /* ipu -> l3_main_2 */
3811 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3812         .master         = &omap44xx_ipu_hwmod,
3813         .slave          = &omap44xx_l3_main_2_hwmod,
3814         .clk            = "l3_div_ck",
3815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3817
3818 /* iss -> l3_main_2 */
3819 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3820         .master         = &omap44xx_iss_hwmod,
3821         .slave          = &omap44xx_l3_main_2_hwmod,
3822         .clk            = "l3_div_ck",
3823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3825
3826 /* iva -> l3_main_2 */
3827 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3828         .master         = &omap44xx_iva_hwmod,
3829         .slave          = &omap44xx_l3_main_2_hwmod,
3830         .clk            = "l3_div_ck",
3831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3832 };
3833
3834 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3835         {
3836                 .pa_start       = 0x44800000,
3837                 .pa_end         = 0x44801fff,
3838                 .flags          = ADDR_TYPE_RT
3839         },
3840         { }
3841 };
3842
3843 /* l3_main_1 -> l3_main_2 */
3844 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3845         .master         = &omap44xx_l3_main_1_hwmod,
3846         .slave          = &omap44xx_l3_main_2_hwmod,
3847         .clk            = "l3_div_ck",
3848         .addr           = omap44xx_l3_main_2_addrs,
3849         .user           = OCP_USER_MPU,
3850 };
3851
3852 /* l4_cfg -> l3_main_2 */
3853 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3854         .master         = &omap44xx_l4_cfg_hwmod,
3855         .slave          = &omap44xx_l3_main_2_hwmod,
3856         .clk            = "l4_div_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* usb_host_fs -> l3_main_2 */
3861 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3862         .master         = &omap44xx_usb_host_fs_hwmod,
3863         .slave          = &omap44xx_l3_main_2_hwmod,
3864         .clk            = "l3_div_ck",
3865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3866 };
3867
3868 /* usb_host_hs -> l3_main_2 */
3869 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3870         .master         = &omap44xx_usb_host_hs_hwmod,
3871         .slave          = &omap44xx_l3_main_2_hwmod,
3872         .clk            = "l3_div_ck",
3873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3874 };
3875
3876 /* usb_otg_hs -> l3_main_2 */
3877 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3878         .master         = &omap44xx_usb_otg_hs_hwmod,
3879         .slave          = &omap44xx_l3_main_2_hwmod,
3880         .clk            = "l3_div_ck",
3881         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3882 };
3883
3884 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3885         {
3886                 .pa_start       = 0x45000000,
3887                 .pa_end         = 0x45000fff,
3888                 .flags          = ADDR_TYPE_RT
3889         },
3890         { }
3891 };
3892
3893 /* l3_main_1 -> l3_main_3 */
3894 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3895         .master         = &omap44xx_l3_main_1_hwmod,
3896         .slave          = &omap44xx_l3_main_3_hwmod,
3897         .clk            = "l3_div_ck",
3898         .addr           = omap44xx_l3_main_3_addrs,
3899         .user           = OCP_USER_MPU,
3900 };
3901
3902 /* l3_main_2 -> l3_main_3 */
3903 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3904         .master         = &omap44xx_l3_main_2_hwmod,
3905         .slave          = &omap44xx_l3_main_3_hwmod,
3906         .clk            = "l3_div_ck",
3907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3908 };
3909
3910 /* l4_cfg -> l3_main_3 */
3911 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3912         .master         = &omap44xx_l4_cfg_hwmod,
3913         .slave          = &omap44xx_l3_main_3_hwmod,
3914         .clk            = "l4_div_ck",
3915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3916 };
3917
3918 /* aess -> l4_abe */
3919 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3920         .master         = &omap44xx_aess_hwmod,
3921         .slave          = &omap44xx_l4_abe_hwmod,
3922         .clk            = "ocp_abe_iclk",
3923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3924 };
3925
3926 /* dsp -> l4_abe */
3927 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3928         .master         = &omap44xx_dsp_hwmod,
3929         .slave          = &omap44xx_l4_abe_hwmod,
3930         .clk            = "ocp_abe_iclk",
3931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3932 };
3933
3934 /* l3_main_1 -> l4_abe */
3935 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3936         .master         = &omap44xx_l3_main_1_hwmod,
3937         .slave          = &omap44xx_l4_abe_hwmod,
3938         .clk            = "l3_div_ck",
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* mpu -> l4_abe */
3943 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3944         .master         = &omap44xx_mpu_hwmod,
3945         .slave          = &omap44xx_l4_abe_hwmod,
3946         .clk            = "ocp_abe_iclk",
3947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3949
3950 /* l3_main_1 -> l4_cfg */
3951 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3952         .master         = &omap44xx_l3_main_1_hwmod,
3953         .slave          = &omap44xx_l4_cfg_hwmod,
3954         .clk            = "l3_div_ck",
3955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 /* l3_main_2 -> l4_per */
3959 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3960         .master         = &omap44xx_l3_main_2_hwmod,
3961         .slave          = &omap44xx_l4_per_hwmod,
3962         .clk            = "l3_div_ck",
3963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3964 };
3965
3966 /* l4_cfg -> l4_wkup */
3967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3968         .master         = &omap44xx_l4_cfg_hwmod,
3969         .slave          = &omap44xx_l4_wkup_hwmod,
3970         .clk            = "l4_div_ck",
3971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3972 };
3973
3974 /* mpu -> mpu_private */
3975 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3976         .master         = &omap44xx_mpu_hwmod,
3977         .slave          = &omap44xx_mpu_private_hwmod,
3978         .clk            = "l3_div_ck",
3979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3980 };
3981
3982 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3983         {
3984                 .pa_start       = 0x4a102000,
3985                 .pa_end         = 0x4a10207f,
3986                 .flags          = ADDR_TYPE_RT
3987         },
3988         { }
3989 };
3990
3991 /* l4_cfg -> ocp_wp_noc */
3992 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3993         .master         = &omap44xx_l4_cfg_hwmod,
3994         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3995         .clk            = "l4_div_ck",
3996         .addr           = omap44xx_ocp_wp_noc_addrs,
3997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
3999
4000 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4001         {
4002                 .pa_start       = 0x401f1000,
4003                 .pa_end         = 0x401f13ff,
4004                 .flags          = ADDR_TYPE_RT
4005         },
4006         { }
4007 };
4008
4009 /* l4_abe -> aess */
4010 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4011         .master         = &omap44xx_l4_abe_hwmod,
4012         .slave          = &omap44xx_aess_hwmod,
4013         .clk            = "ocp_abe_iclk",
4014         .addr           = omap44xx_aess_addrs,
4015         .user           = OCP_USER_MPU,
4016 };
4017
4018 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4019         {
4020                 .pa_start       = 0x490f1000,
4021                 .pa_end         = 0x490f13ff,
4022                 .flags          = ADDR_TYPE_RT
4023         },
4024         { }
4025 };
4026
4027 /* l4_abe -> aess (dma) */
4028 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4029         .master         = &omap44xx_l4_abe_hwmod,
4030         .slave          = &omap44xx_aess_hwmod,
4031         .clk            = "ocp_abe_iclk",
4032         .addr           = omap44xx_aess_dma_addrs,
4033         .user           = OCP_USER_SDMA,
4034 };
4035
4036 /* l3_main_2 -> c2c */
4037 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4038         .master         = &omap44xx_l3_main_2_hwmod,
4039         .slave          = &omap44xx_c2c_hwmod,
4040         .clk            = "l3_div_ck",
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4045         {
4046                 .pa_start       = 0x4a304000,
4047                 .pa_end         = 0x4a30401f,
4048                 .flags          = ADDR_TYPE_RT
4049         },
4050         { }
4051 };
4052
4053 /* l4_wkup -> counter_32k */
4054 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4055         .master         = &omap44xx_l4_wkup_hwmod,
4056         .slave          = &omap44xx_counter_32k_hwmod,
4057         .clk            = "l4_wkup_clk_mux_ck",
4058         .addr           = omap44xx_counter_32k_addrs,
4059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4060 };
4061
4062 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4063         {
4064                 .pa_start       = 0x4a002000,
4065                 .pa_end         = 0x4a0027ff,
4066                 .flags          = ADDR_TYPE_RT
4067         },
4068         { }
4069 };
4070
4071 /* l4_cfg -> ctrl_module_core */
4072 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4073         .master         = &omap44xx_l4_cfg_hwmod,
4074         .slave          = &omap44xx_ctrl_module_core_hwmod,
4075         .clk            = "l4_div_ck",
4076         .addr           = omap44xx_ctrl_module_core_addrs,
4077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4079
4080 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4081         {
4082                 .pa_start       = 0x4a100000,
4083                 .pa_end         = 0x4a1007ff,
4084                 .flags          = ADDR_TYPE_RT
4085         },
4086         { }
4087 };
4088
4089 /* l4_cfg -> ctrl_module_pad_core */
4090 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4091         .master         = &omap44xx_l4_cfg_hwmod,
4092         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4093         .clk            = "l4_div_ck",
4094         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4096 };
4097
4098 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4099         {
4100                 .pa_start       = 0x4a30c000,
4101                 .pa_end         = 0x4a30c7ff,
4102                 .flags          = ADDR_TYPE_RT
4103         },
4104         { }
4105 };
4106
4107 /* l4_wkup -> ctrl_module_wkup */
4108 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4109         .master         = &omap44xx_l4_wkup_hwmod,
4110         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4111         .clk            = "l4_wkup_clk_mux_ck",
4112         .addr           = omap44xx_ctrl_module_wkup_addrs,
4113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4115
4116 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4117         {
4118                 .pa_start       = 0x4a31e000,
4119                 .pa_end         = 0x4a31e7ff,
4120                 .flags          = ADDR_TYPE_RT
4121         },
4122         { }
4123 };
4124
4125 /* l4_wkup -> ctrl_module_pad_wkup */
4126 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4127         .master         = &omap44xx_l4_wkup_hwmod,
4128         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4129         .clk            = "l4_wkup_clk_mux_ck",
4130         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4132 };
4133
4134 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4135         {
4136                 .pa_start       = 0x54160000,
4137                 .pa_end         = 0x54167fff,
4138                 .flags          = ADDR_TYPE_RT
4139         },
4140         { }
4141 };
4142
4143 /* l3_instr -> debugss */
4144 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4145         .master         = &omap44xx_l3_instr_hwmod,
4146         .slave          = &omap44xx_debugss_hwmod,
4147         .clk            = "l3_div_ck",
4148         .addr           = omap44xx_debugss_addrs,
4149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4151
4152 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4153         {
4154                 .pa_start       = 0x4a056000,
4155                 .pa_end         = 0x4a056fff,
4156                 .flags          = ADDR_TYPE_RT
4157         },
4158         { }
4159 };
4160
4161 /* l4_cfg -> dma_system */
4162 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4163         .master         = &omap44xx_l4_cfg_hwmod,
4164         .slave          = &omap44xx_dma_system_hwmod,
4165         .clk            = "l4_div_ck",
4166         .addr           = omap44xx_dma_system_addrs,
4167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4168 };
4169
4170 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4171         {
4172                 .name           = "mpu",
4173                 .pa_start       = 0x4012e000,
4174                 .pa_end         = 0x4012e07f,
4175                 .flags          = ADDR_TYPE_RT
4176         },
4177         { }
4178 };
4179
4180 /* l4_abe -> dmic */
4181 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4182         .master         = &omap44xx_l4_abe_hwmod,
4183         .slave          = &omap44xx_dmic_hwmod,
4184         .clk            = "ocp_abe_iclk",
4185         .addr           = omap44xx_dmic_addrs,
4186         .user           = OCP_USER_MPU,
4187 };
4188
4189 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4190         {
4191                 .name           = "dma",
4192                 .pa_start       = 0x4902e000,
4193                 .pa_end         = 0x4902e07f,
4194                 .flags          = ADDR_TYPE_RT
4195         },
4196         { }
4197 };
4198
4199 /* l4_abe -> dmic (dma) */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4201         .master         = &omap44xx_l4_abe_hwmod,
4202         .slave          = &omap44xx_dmic_hwmod,
4203         .clk            = "ocp_abe_iclk",
4204         .addr           = omap44xx_dmic_dma_addrs,
4205         .user           = OCP_USER_SDMA,
4206 };
4207
4208 /* dsp -> iva */
4209 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4210         .master         = &omap44xx_dsp_hwmod,
4211         .slave          = &omap44xx_iva_hwmod,
4212         .clk            = "dpll_iva_m5x2_ck",
4213         .user           = OCP_USER_DSP,
4214 };
4215
4216 /* dsp -> sl2if */
4217 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4218         .master         = &omap44xx_dsp_hwmod,
4219         .slave          = &omap44xx_sl2if_hwmod,
4220         .clk            = "dpll_iva_m5x2_ck",
4221         .user           = OCP_USER_DSP,
4222 };
4223
4224 /* l4_cfg -> dsp */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4226         .master         = &omap44xx_l4_cfg_hwmod,
4227         .slave          = &omap44xx_dsp_hwmod,
4228         .clk            = "l4_div_ck",
4229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4233         {
4234                 .pa_start       = 0x58000000,
4235                 .pa_end         = 0x5800007f,
4236                 .flags          = ADDR_TYPE_RT
4237         },
4238         { }
4239 };
4240
4241 /* l3_main_2 -> dss */
4242 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4243         .master         = &omap44xx_l3_main_2_hwmod,
4244         .slave          = &omap44xx_dss_hwmod,
4245         .clk            = "dss_fck",
4246         .addr           = omap44xx_dss_dma_addrs,
4247         .user           = OCP_USER_SDMA,
4248 };
4249
4250 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4251         {
4252                 .pa_start       = 0x48040000,
4253                 .pa_end         = 0x4804007f,
4254                 .flags          = ADDR_TYPE_RT
4255         },
4256         { }
4257 };
4258
4259 /* l4_per -> dss */
4260 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4261         .master         = &omap44xx_l4_per_hwmod,
4262         .slave          = &omap44xx_dss_hwmod,
4263         .clk            = "l4_div_ck",
4264         .addr           = omap44xx_dss_addrs,
4265         .user           = OCP_USER_MPU,
4266 };
4267
4268 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4269         {
4270                 .pa_start       = 0x58001000,
4271                 .pa_end         = 0x58001fff,
4272                 .flags          = ADDR_TYPE_RT
4273         },
4274         { }
4275 };
4276
4277 /* l3_main_2 -> dss_dispc */
4278 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4279         .master         = &omap44xx_l3_main_2_hwmod,
4280         .slave          = &omap44xx_dss_dispc_hwmod,
4281         .clk            = "dss_fck",
4282         .addr           = omap44xx_dss_dispc_dma_addrs,
4283         .user           = OCP_USER_SDMA,
4284 };
4285
4286 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4287         {
4288                 .pa_start       = 0x48041000,
4289                 .pa_end         = 0x48041fff,
4290                 .flags          = ADDR_TYPE_RT
4291         },
4292         { }
4293 };
4294
4295 /* l4_per -> dss_dispc */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4297         .master         = &omap44xx_l4_per_hwmod,
4298         .slave          = &omap44xx_dss_dispc_hwmod,
4299         .clk            = "l4_div_ck",
4300         .addr           = omap44xx_dss_dispc_addrs,
4301         .user           = OCP_USER_MPU,
4302 };
4303
4304 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4305         {
4306                 .pa_start       = 0x58004000,
4307                 .pa_end         = 0x580041ff,
4308                 .flags          = ADDR_TYPE_RT
4309         },
4310         { }
4311 };
4312
4313 /* l3_main_2 -> dss_dsi1 */
4314 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4315         .master         = &omap44xx_l3_main_2_hwmod,
4316         .slave          = &omap44xx_dss_dsi1_hwmod,
4317         .clk            = "dss_fck",
4318         .addr           = omap44xx_dss_dsi1_dma_addrs,
4319         .user           = OCP_USER_SDMA,
4320 };
4321
4322 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4323         {
4324                 .pa_start       = 0x48044000,
4325                 .pa_end         = 0x480441ff,
4326                 .flags          = ADDR_TYPE_RT
4327         },
4328         { }
4329 };
4330
4331 /* l4_per -> dss_dsi1 */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4333         .master         = &omap44xx_l4_per_hwmod,
4334         .slave          = &omap44xx_dss_dsi1_hwmod,
4335         .clk            = "l4_div_ck",
4336         .addr           = omap44xx_dss_dsi1_addrs,
4337         .user           = OCP_USER_MPU,
4338 };
4339
4340 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4341         {
4342                 .pa_start       = 0x58005000,
4343                 .pa_end         = 0x580051ff,
4344                 .flags          = ADDR_TYPE_RT
4345         },
4346         { }
4347 };
4348
4349 /* l3_main_2 -> dss_dsi2 */
4350 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4351         .master         = &omap44xx_l3_main_2_hwmod,
4352         .slave          = &omap44xx_dss_dsi2_hwmod,
4353         .clk            = "dss_fck",
4354         .addr           = omap44xx_dss_dsi2_dma_addrs,
4355         .user           = OCP_USER_SDMA,
4356 };
4357
4358 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4359         {
4360                 .pa_start       = 0x48045000,
4361                 .pa_end         = 0x480451ff,
4362                 .flags          = ADDR_TYPE_RT
4363         },
4364         { }
4365 };
4366
4367 /* l4_per -> dss_dsi2 */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4369         .master         = &omap44xx_l4_per_hwmod,
4370         .slave          = &omap44xx_dss_dsi2_hwmod,
4371         .clk            = "l4_div_ck",
4372         .addr           = omap44xx_dss_dsi2_addrs,
4373         .user           = OCP_USER_MPU,
4374 };
4375
4376 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4377         {
4378                 .pa_start       = 0x58006000,
4379                 .pa_end         = 0x58006fff,
4380                 .flags          = ADDR_TYPE_RT
4381         },
4382         { }
4383 };
4384
4385 /* l3_main_2 -> dss_hdmi */
4386 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4387         .master         = &omap44xx_l3_main_2_hwmod,
4388         .slave          = &omap44xx_dss_hdmi_hwmod,
4389         .clk            = "dss_fck",
4390         .addr           = omap44xx_dss_hdmi_dma_addrs,
4391         .user           = OCP_USER_SDMA,
4392 };
4393
4394 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4395         {
4396                 .pa_start       = 0x48046000,
4397                 .pa_end         = 0x48046fff,
4398                 .flags          = ADDR_TYPE_RT
4399         },
4400         { }
4401 };
4402
4403 /* l4_per -> dss_hdmi */
4404 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4405         .master         = &omap44xx_l4_per_hwmod,
4406         .slave          = &omap44xx_dss_hdmi_hwmod,
4407         .clk            = "l4_div_ck",
4408         .addr           = omap44xx_dss_hdmi_addrs,
4409         .user           = OCP_USER_MPU,
4410 };
4411
4412 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4413         {
4414                 .pa_start       = 0x58002000,
4415                 .pa_end         = 0x580020ff,
4416                 .flags          = ADDR_TYPE_RT
4417         },
4418         { }
4419 };
4420
4421 /* l3_main_2 -> dss_rfbi */
4422 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4423         .master         = &omap44xx_l3_main_2_hwmod,
4424         .slave          = &omap44xx_dss_rfbi_hwmod,
4425         .clk            = "dss_fck",
4426         .addr           = omap44xx_dss_rfbi_dma_addrs,
4427         .user           = OCP_USER_SDMA,
4428 };
4429
4430 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4431         {
4432                 .pa_start       = 0x48042000,
4433                 .pa_end         = 0x480420ff,
4434                 .flags          = ADDR_TYPE_RT
4435         },
4436         { }
4437 };
4438
4439 /* l4_per -> dss_rfbi */
4440 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4441         .master         = &omap44xx_l4_per_hwmod,
4442         .slave          = &omap44xx_dss_rfbi_hwmod,
4443         .clk            = "l4_div_ck",
4444         .addr           = omap44xx_dss_rfbi_addrs,
4445         .user           = OCP_USER_MPU,
4446 };
4447
4448 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4449         {
4450                 .pa_start       = 0x58003000,
4451                 .pa_end         = 0x580030ff,
4452                 .flags          = ADDR_TYPE_RT
4453         },
4454         { }
4455 };
4456
4457 /* l3_main_2 -> dss_venc */
4458 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4459         .master         = &omap44xx_l3_main_2_hwmod,
4460         .slave          = &omap44xx_dss_venc_hwmod,
4461         .clk            = "dss_fck",
4462         .addr           = omap44xx_dss_venc_dma_addrs,
4463         .user           = OCP_USER_SDMA,
4464 };
4465
4466 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4467         {
4468                 .pa_start       = 0x48043000,
4469                 .pa_end         = 0x480430ff,
4470                 .flags          = ADDR_TYPE_RT
4471         },
4472         { }
4473 };
4474
4475 /* l4_per -> dss_venc */
4476 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4477         .master         = &omap44xx_l4_per_hwmod,
4478         .slave          = &omap44xx_dss_venc_hwmod,
4479         .clk            = "l4_div_ck",
4480         .addr           = omap44xx_dss_venc_addrs,
4481         .user           = OCP_USER_MPU,
4482 };
4483
4484 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4485         {
4486                 .pa_start       = 0x48078000,
4487                 .pa_end         = 0x48078fff,
4488                 .flags          = ADDR_TYPE_RT
4489         },
4490         { }
4491 };
4492
4493 /* l4_per -> elm */
4494 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4495         .master         = &omap44xx_l4_per_hwmod,
4496         .slave          = &omap44xx_elm_hwmod,
4497         .clk            = "l4_div_ck",
4498         .addr           = omap44xx_elm_addrs,
4499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4500 };
4501
4502 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4503         {
4504                 .pa_start       = 0x4c000000,
4505                 .pa_end         = 0x4c0000ff,
4506                 .flags          = ADDR_TYPE_RT
4507         },
4508         { }
4509 };
4510
4511 /* emif_fw -> emif1 */
4512 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4513         .master         = &omap44xx_emif_fw_hwmod,
4514         .slave          = &omap44xx_emif1_hwmod,
4515         .clk            = "l3_div_ck",
4516         .addr           = omap44xx_emif1_addrs,
4517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4518 };
4519
4520 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4521         {
4522                 .pa_start       = 0x4d000000,
4523                 .pa_end         = 0x4d0000ff,
4524                 .flags          = ADDR_TYPE_RT
4525         },
4526         { }
4527 };
4528
4529 /* emif_fw -> emif2 */
4530 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4531         .master         = &omap44xx_emif_fw_hwmod,
4532         .slave          = &omap44xx_emif2_hwmod,
4533         .clk            = "l3_div_ck",
4534         .addr           = omap44xx_emif2_addrs,
4535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4536 };
4537
4538 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4539         {
4540                 .pa_start       = 0x4a10a000,
4541                 .pa_end         = 0x4a10a1ff,
4542                 .flags          = ADDR_TYPE_RT
4543         },
4544         { }
4545 };
4546
4547 /* l4_cfg -> fdif */
4548 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4549         .master         = &omap44xx_l4_cfg_hwmod,
4550         .slave          = &omap44xx_fdif_hwmod,
4551         .clk            = "l4_div_ck",
4552         .addr           = omap44xx_fdif_addrs,
4553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4554 };
4555
4556 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4557         {
4558                 .pa_start       = 0x4a310000,
4559                 .pa_end         = 0x4a3101ff,
4560                 .flags          = ADDR_TYPE_RT
4561         },
4562         { }
4563 };
4564
4565 /* l4_wkup -> gpio1 */
4566 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4567         .master         = &omap44xx_l4_wkup_hwmod,
4568         .slave          = &omap44xx_gpio1_hwmod,
4569         .clk            = "l4_wkup_clk_mux_ck",
4570         .addr           = omap44xx_gpio1_addrs,
4571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4572 };
4573
4574 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4575         {
4576                 .pa_start       = 0x48055000,
4577                 .pa_end         = 0x480551ff,
4578                 .flags          = ADDR_TYPE_RT
4579         },
4580         { }
4581 };
4582
4583 /* l4_per -> gpio2 */
4584 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4585         .master         = &omap44xx_l4_per_hwmod,
4586         .slave          = &omap44xx_gpio2_hwmod,
4587         .clk            = "l4_div_ck",
4588         .addr           = omap44xx_gpio2_addrs,
4589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4590 };
4591
4592 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4593         {
4594                 .pa_start       = 0x48057000,
4595                 .pa_end         = 0x480571ff,
4596                 .flags          = ADDR_TYPE_RT
4597         },
4598         { }
4599 };
4600
4601 /* l4_per -> gpio3 */
4602 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4603         .master         = &omap44xx_l4_per_hwmod,
4604         .slave          = &omap44xx_gpio3_hwmod,
4605         .clk            = "l4_div_ck",
4606         .addr           = omap44xx_gpio3_addrs,
4607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4608 };
4609
4610 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4611         {
4612                 .pa_start       = 0x48059000,
4613                 .pa_end         = 0x480591ff,
4614                 .flags          = ADDR_TYPE_RT
4615         },
4616         { }
4617 };
4618
4619 /* l4_per -> gpio4 */
4620 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4621         .master         = &omap44xx_l4_per_hwmod,
4622         .slave          = &omap44xx_gpio4_hwmod,
4623         .clk            = "l4_div_ck",
4624         .addr           = omap44xx_gpio4_addrs,
4625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4626 };
4627
4628 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4629         {
4630                 .pa_start       = 0x4805b000,
4631                 .pa_end         = 0x4805b1ff,
4632                 .flags          = ADDR_TYPE_RT
4633         },
4634         { }
4635 };
4636
4637 /* l4_per -> gpio5 */
4638 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4639         .master         = &omap44xx_l4_per_hwmod,
4640         .slave          = &omap44xx_gpio5_hwmod,
4641         .clk            = "l4_div_ck",
4642         .addr           = omap44xx_gpio5_addrs,
4643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4644 };
4645
4646 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4647         {
4648                 .pa_start       = 0x4805d000,
4649                 .pa_end         = 0x4805d1ff,
4650                 .flags          = ADDR_TYPE_RT
4651         },
4652         { }
4653 };
4654
4655 /* l4_per -> gpio6 */
4656 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4657         .master         = &omap44xx_l4_per_hwmod,
4658         .slave          = &omap44xx_gpio6_hwmod,
4659         .clk            = "l4_div_ck",
4660         .addr           = omap44xx_gpio6_addrs,
4661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4662 };
4663
4664 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4665         {
4666                 .pa_start       = 0x50000000,
4667                 .pa_end         = 0x500003ff,
4668                 .flags          = ADDR_TYPE_RT
4669         },
4670         { }
4671 };
4672
4673 /* l3_main_2 -> gpmc */
4674 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4675         .master         = &omap44xx_l3_main_2_hwmod,
4676         .slave          = &omap44xx_gpmc_hwmod,
4677         .clk            = "l3_div_ck",
4678         .addr           = omap44xx_gpmc_addrs,
4679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4680 };
4681
4682 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4683         {
4684                 .pa_start       = 0x56000000,
4685                 .pa_end         = 0x5600ffff,
4686                 .flags          = ADDR_TYPE_RT
4687         },
4688         { }
4689 };
4690
4691 /* l3_main_2 -> gpu */
4692 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4693         .master         = &omap44xx_l3_main_2_hwmod,
4694         .slave          = &omap44xx_gpu_hwmod,
4695         .clk            = "l3_div_ck",
4696         .addr           = omap44xx_gpu_addrs,
4697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4698 };
4699
4700 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4701         {
4702                 .pa_start       = 0x480b2000,
4703                 .pa_end         = 0x480b201f,
4704                 .flags          = ADDR_TYPE_RT
4705         },
4706         { }
4707 };
4708
4709 /* l4_per -> hdq1w */
4710 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4711         .master         = &omap44xx_l4_per_hwmod,
4712         .slave          = &omap44xx_hdq1w_hwmod,
4713         .clk            = "l4_div_ck",
4714         .addr           = omap44xx_hdq1w_addrs,
4715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4716 };
4717
4718 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4719         {
4720                 .pa_start       = 0x4a058000,
4721                 .pa_end         = 0x4a05bfff,
4722                 .flags          = ADDR_TYPE_RT
4723         },
4724         { }
4725 };
4726
4727 /* l4_cfg -> hsi */
4728 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4729         .master         = &omap44xx_l4_cfg_hwmod,
4730         .slave          = &omap44xx_hsi_hwmod,
4731         .clk            = "l4_div_ck",
4732         .addr           = omap44xx_hsi_addrs,
4733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4734 };
4735
4736 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4737         {
4738                 .pa_start       = 0x48070000,
4739                 .pa_end         = 0x480700ff,
4740                 .flags          = ADDR_TYPE_RT
4741         },
4742         { }
4743 };
4744
4745 /* l4_per -> i2c1 */
4746 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4747         .master         = &omap44xx_l4_per_hwmod,
4748         .slave          = &omap44xx_i2c1_hwmod,
4749         .clk            = "l4_div_ck",
4750         .addr           = omap44xx_i2c1_addrs,
4751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4752 };
4753
4754 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4755         {
4756                 .pa_start       = 0x48072000,
4757                 .pa_end         = 0x480720ff,
4758                 .flags          = ADDR_TYPE_RT
4759         },
4760         { }
4761 };
4762
4763 /* l4_per -> i2c2 */
4764 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4765         .master         = &omap44xx_l4_per_hwmod,
4766         .slave          = &omap44xx_i2c2_hwmod,
4767         .clk            = "l4_div_ck",
4768         .addr           = omap44xx_i2c2_addrs,
4769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4770 };
4771
4772 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4773         {
4774                 .pa_start       = 0x48060000,
4775                 .pa_end         = 0x480600ff,
4776                 .flags          = ADDR_TYPE_RT
4777         },
4778         { }
4779 };
4780
4781 /* l4_per -> i2c3 */
4782 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4783         .master         = &omap44xx_l4_per_hwmod,
4784         .slave          = &omap44xx_i2c3_hwmod,
4785         .clk            = "l4_div_ck",
4786         .addr           = omap44xx_i2c3_addrs,
4787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4788 };
4789
4790 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4791         {
4792                 .pa_start       = 0x48350000,
4793                 .pa_end         = 0x483500ff,
4794                 .flags          = ADDR_TYPE_RT
4795         },
4796         { }
4797 };
4798
4799 /* l4_per -> i2c4 */
4800 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4801         .master         = &omap44xx_l4_per_hwmod,
4802         .slave          = &omap44xx_i2c4_hwmod,
4803         .clk            = "l4_div_ck",
4804         .addr           = omap44xx_i2c4_addrs,
4805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4806 };
4807
4808 /* l3_main_2 -> ipu */
4809 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4810         .master         = &omap44xx_l3_main_2_hwmod,
4811         .slave          = &omap44xx_ipu_hwmod,
4812         .clk            = "l3_div_ck",
4813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4814 };
4815
4816 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4817         {
4818                 .pa_start       = 0x52000000,
4819                 .pa_end         = 0x520000ff,
4820                 .flags          = ADDR_TYPE_RT
4821         },
4822         { }
4823 };
4824
4825 /* l3_main_2 -> iss */
4826 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4827         .master         = &omap44xx_l3_main_2_hwmod,
4828         .slave          = &omap44xx_iss_hwmod,
4829         .clk            = "l3_div_ck",
4830         .addr           = omap44xx_iss_addrs,
4831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4832 };
4833
4834 /* iva -> sl2if */
4835 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4836         .master         = &omap44xx_iva_hwmod,
4837         .slave          = &omap44xx_sl2if_hwmod,
4838         .clk            = "dpll_iva_m5x2_ck",
4839         .user           = OCP_USER_IVA,
4840 };
4841
4842 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4843         {
4844                 .pa_start       = 0x5a000000,
4845                 .pa_end         = 0x5a07ffff,
4846                 .flags          = ADDR_TYPE_RT
4847         },
4848         { }
4849 };
4850
4851 /* l3_main_2 -> iva */
4852 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4853         .master         = &omap44xx_l3_main_2_hwmod,
4854         .slave          = &omap44xx_iva_hwmod,
4855         .clk            = "l3_div_ck",
4856         .addr           = omap44xx_iva_addrs,
4857         .user           = OCP_USER_MPU,
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4861         {
4862                 .pa_start       = 0x4a31c000,
4863                 .pa_end         = 0x4a31c07f,
4864                 .flags          = ADDR_TYPE_RT
4865         },
4866         { }
4867 };
4868
4869 /* l4_wkup -> kbd */
4870 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4871         .master         = &omap44xx_l4_wkup_hwmod,
4872         .slave          = &omap44xx_kbd_hwmod,
4873         .clk            = "l4_wkup_clk_mux_ck",
4874         .addr           = omap44xx_kbd_addrs,
4875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4879         {
4880                 .pa_start       = 0x4a0f4000,
4881                 .pa_end         = 0x4a0f41ff,
4882                 .flags          = ADDR_TYPE_RT
4883         },
4884         { }
4885 };
4886
4887 /* l4_cfg -> mailbox */
4888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4889         .master         = &omap44xx_l4_cfg_hwmod,
4890         .slave          = &omap44xx_mailbox_hwmod,
4891         .clk            = "l4_div_ck",
4892         .addr           = omap44xx_mailbox_addrs,
4893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4894 };
4895
4896 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4897         {
4898                 .pa_start       = 0x40128000,
4899                 .pa_end         = 0x401283ff,
4900                 .flags          = ADDR_TYPE_RT
4901         },
4902         { }
4903 };
4904
4905 /* l4_abe -> mcasp */
4906 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4907         .master         = &omap44xx_l4_abe_hwmod,
4908         .slave          = &omap44xx_mcasp_hwmod,
4909         .clk            = "ocp_abe_iclk",
4910         .addr           = omap44xx_mcasp_addrs,
4911         .user           = OCP_USER_MPU,
4912 };
4913
4914 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4915         {
4916                 .pa_start       = 0x49028000,
4917                 .pa_end         = 0x490283ff,
4918                 .flags          = ADDR_TYPE_RT
4919         },
4920         { }
4921 };
4922
4923 /* l4_abe -> mcasp (dma) */
4924 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4925         .master         = &omap44xx_l4_abe_hwmod,
4926         .slave          = &omap44xx_mcasp_hwmod,
4927         .clk            = "ocp_abe_iclk",
4928         .addr           = omap44xx_mcasp_dma_addrs,
4929         .user           = OCP_USER_SDMA,
4930 };
4931
4932 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4933         {
4934                 .name           = "mpu",
4935                 .pa_start       = 0x40122000,
4936                 .pa_end         = 0x401220ff,
4937                 .flags          = ADDR_TYPE_RT
4938         },
4939         { }
4940 };
4941
4942 /* l4_abe -> mcbsp1 */
4943 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4944         .master         = &omap44xx_l4_abe_hwmod,
4945         .slave          = &omap44xx_mcbsp1_hwmod,
4946         .clk            = "ocp_abe_iclk",
4947         .addr           = omap44xx_mcbsp1_addrs,
4948         .user           = OCP_USER_MPU,
4949 };
4950
4951 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4952         {
4953                 .name           = "dma",
4954                 .pa_start       = 0x49022000,
4955                 .pa_end         = 0x490220ff,
4956                 .flags          = ADDR_TYPE_RT
4957         },
4958         { }
4959 };
4960
4961 /* l4_abe -> mcbsp1 (dma) */
4962 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4963         .master         = &omap44xx_l4_abe_hwmod,
4964         .slave          = &omap44xx_mcbsp1_hwmod,
4965         .clk            = "ocp_abe_iclk",
4966         .addr           = omap44xx_mcbsp1_dma_addrs,
4967         .user           = OCP_USER_SDMA,
4968 };
4969
4970 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4971         {
4972                 .name           = "mpu",
4973                 .pa_start       = 0x40124000,
4974                 .pa_end         = 0x401240ff,
4975                 .flags          = ADDR_TYPE_RT
4976         },
4977         { }
4978 };
4979
4980 /* l4_abe -> mcbsp2 */
4981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4982         .master         = &omap44xx_l4_abe_hwmod,
4983         .slave          = &omap44xx_mcbsp2_hwmod,
4984         .clk            = "ocp_abe_iclk",
4985         .addr           = omap44xx_mcbsp2_addrs,
4986         .user           = OCP_USER_MPU,
4987 };
4988
4989 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4990         {
4991                 .name           = "dma",
4992                 .pa_start       = 0x49024000,
4993                 .pa_end         = 0x490240ff,
4994                 .flags          = ADDR_TYPE_RT
4995         },
4996         { }
4997 };
4998
4999 /* l4_abe -> mcbsp2 (dma) */
5000 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5001         .master         = &omap44xx_l4_abe_hwmod,
5002         .slave          = &omap44xx_mcbsp2_hwmod,
5003         .clk            = "ocp_abe_iclk",
5004         .addr           = omap44xx_mcbsp2_dma_addrs,
5005         .user           = OCP_USER_SDMA,
5006 };
5007
5008 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5009         {
5010                 .name           = "mpu",
5011                 .pa_start       = 0x40126000,
5012                 .pa_end         = 0x401260ff,
5013                 .flags          = ADDR_TYPE_RT
5014         },
5015         { }
5016 };
5017
5018 /* l4_abe -> mcbsp3 */
5019 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5020         .master         = &omap44xx_l4_abe_hwmod,
5021         .slave          = &omap44xx_mcbsp3_hwmod,
5022         .clk            = "ocp_abe_iclk",
5023         .addr           = omap44xx_mcbsp3_addrs,
5024         .user           = OCP_USER_MPU,
5025 };
5026
5027 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5028         {
5029                 .name           = "dma",
5030                 .pa_start       = 0x49026000,
5031                 .pa_end         = 0x490260ff,
5032                 .flags          = ADDR_TYPE_RT
5033         },
5034         { }
5035 };
5036
5037 /* l4_abe -> mcbsp3 (dma) */
5038 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5039         .master         = &omap44xx_l4_abe_hwmod,
5040         .slave          = &omap44xx_mcbsp3_hwmod,
5041         .clk            = "ocp_abe_iclk",
5042         .addr           = omap44xx_mcbsp3_dma_addrs,
5043         .user           = OCP_USER_SDMA,
5044 };
5045
5046 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5047         {
5048                 .pa_start       = 0x48096000,
5049                 .pa_end         = 0x480960ff,
5050                 .flags          = ADDR_TYPE_RT
5051         },
5052         { }
5053 };
5054
5055 /* l4_per -> mcbsp4 */
5056 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5057         .master         = &omap44xx_l4_per_hwmod,
5058         .slave          = &omap44xx_mcbsp4_hwmod,
5059         .clk            = "l4_div_ck",
5060         .addr           = omap44xx_mcbsp4_addrs,
5061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5062 };
5063
5064 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5065         {
5066                 .pa_start       = 0x40132000,
5067                 .pa_end         = 0x4013207f,
5068                 .flags          = ADDR_TYPE_RT
5069         },
5070         { }
5071 };
5072
5073 /* l4_abe -> mcpdm */
5074 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5075         .master         = &omap44xx_l4_abe_hwmod,
5076         .slave          = &omap44xx_mcpdm_hwmod,
5077         .clk            = "ocp_abe_iclk",
5078         .addr           = omap44xx_mcpdm_addrs,
5079         .user           = OCP_USER_MPU,
5080 };
5081
5082 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5083         {
5084                 .pa_start       = 0x49032000,
5085                 .pa_end         = 0x4903207f,
5086                 .flags          = ADDR_TYPE_RT
5087         },
5088         { }
5089 };
5090
5091 /* l4_abe -> mcpdm (dma) */
5092 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5093         .master         = &omap44xx_l4_abe_hwmod,
5094         .slave          = &omap44xx_mcpdm_hwmod,
5095         .clk            = "ocp_abe_iclk",
5096         .addr           = omap44xx_mcpdm_dma_addrs,
5097         .user           = OCP_USER_SDMA,
5098 };
5099
5100 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5101         {
5102                 .pa_start       = 0x48098000,
5103                 .pa_end         = 0x480981ff,
5104                 .flags          = ADDR_TYPE_RT
5105         },
5106         { }
5107 };
5108
5109 /* l4_per -> mcspi1 */
5110 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5111         .master         = &omap44xx_l4_per_hwmod,
5112         .slave          = &omap44xx_mcspi1_hwmod,
5113         .clk            = "l4_div_ck",
5114         .addr           = omap44xx_mcspi1_addrs,
5115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5116 };
5117
5118 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5119         {
5120                 .pa_start       = 0x4809a000,
5121                 .pa_end         = 0x4809a1ff,
5122                 .flags          = ADDR_TYPE_RT
5123         },
5124         { }
5125 };
5126
5127 /* l4_per -> mcspi2 */
5128 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5129         .master         = &omap44xx_l4_per_hwmod,
5130         .slave          = &omap44xx_mcspi2_hwmod,
5131         .clk            = "l4_div_ck",
5132         .addr           = omap44xx_mcspi2_addrs,
5133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5134 };
5135
5136 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5137         {
5138                 .pa_start       = 0x480b8000,
5139                 .pa_end         = 0x480b81ff,
5140                 .flags          = ADDR_TYPE_RT
5141         },
5142         { }
5143 };
5144
5145 /* l4_per -> mcspi3 */
5146 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5147         .master         = &omap44xx_l4_per_hwmod,
5148         .slave          = &omap44xx_mcspi3_hwmod,
5149         .clk            = "l4_div_ck",
5150         .addr           = omap44xx_mcspi3_addrs,
5151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5152 };
5153
5154 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5155         {
5156                 .pa_start       = 0x480ba000,
5157                 .pa_end         = 0x480ba1ff,
5158                 .flags          = ADDR_TYPE_RT
5159         },
5160         { }
5161 };
5162
5163 /* l4_per -> mcspi4 */
5164 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5165         .master         = &omap44xx_l4_per_hwmod,
5166         .slave          = &omap44xx_mcspi4_hwmod,
5167         .clk            = "l4_div_ck",
5168         .addr           = omap44xx_mcspi4_addrs,
5169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5170 };
5171
5172 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5173         {
5174                 .pa_start       = 0x4809c000,
5175                 .pa_end         = 0x4809c3ff,
5176                 .flags          = ADDR_TYPE_RT
5177         },
5178         { }
5179 };
5180
5181 /* l4_per -> mmc1 */
5182 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5183         .master         = &omap44xx_l4_per_hwmod,
5184         .slave          = &omap44xx_mmc1_hwmod,
5185         .clk            = "l4_div_ck",
5186         .addr           = omap44xx_mmc1_addrs,
5187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5188 };
5189
5190 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5191         {
5192                 .pa_start       = 0x480b4000,
5193                 .pa_end         = 0x480b43ff,
5194                 .flags          = ADDR_TYPE_RT
5195         },
5196         { }
5197 };
5198
5199 /* l4_per -> mmc2 */
5200 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5201         .master         = &omap44xx_l4_per_hwmod,
5202         .slave          = &omap44xx_mmc2_hwmod,
5203         .clk            = "l4_div_ck",
5204         .addr           = omap44xx_mmc2_addrs,
5205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5206 };
5207
5208 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5209         {
5210                 .pa_start       = 0x480ad000,
5211                 .pa_end         = 0x480ad3ff,
5212                 .flags          = ADDR_TYPE_RT
5213         },
5214         { }
5215 };
5216
5217 /* l4_per -> mmc3 */
5218 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5219         .master         = &omap44xx_l4_per_hwmod,
5220         .slave          = &omap44xx_mmc3_hwmod,
5221         .clk            = "l4_div_ck",
5222         .addr           = omap44xx_mmc3_addrs,
5223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5224 };
5225
5226 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5227         {
5228                 .pa_start       = 0x480d1000,
5229                 .pa_end         = 0x480d13ff,
5230                 .flags          = ADDR_TYPE_RT
5231         },
5232         { }
5233 };
5234
5235 /* l4_per -> mmc4 */
5236 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5237         .master         = &omap44xx_l4_per_hwmod,
5238         .slave          = &omap44xx_mmc4_hwmod,
5239         .clk            = "l4_div_ck",
5240         .addr           = omap44xx_mmc4_addrs,
5241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5242 };
5243
5244 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5245         {
5246                 .pa_start       = 0x480d5000,
5247                 .pa_end         = 0x480d53ff,
5248                 .flags          = ADDR_TYPE_RT
5249         },
5250         { }
5251 };
5252
5253 /* l4_per -> mmc5 */
5254 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5255         .master         = &omap44xx_l4_per_hwmod,
5256         .slave          = &omap44xx_mmc5_hwmod,
5257         .clk            = "l4_div_ck",
5258         .addr           = omap44xx_mmc5_addrs,
5259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5260 };
5261
5262 /* l3_main_2 -> ocmc_ram */
5263 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5264         .master         = &omap44xx_l3_main_2_hwmod,
5265         .slave          = &omap44xx_ocmc_ram_hwmod,
5266         .clk            = "l3_div_ck",
5267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5268 };
5269
5270 /* l4_cfg -> ocp2scp_usb_phy */
5271 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5272         .master         = &omap44xx_l4_cfg_hwmod,
5273         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5274         .clk            = "l4_div_ck",
5275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5276 };
5277
5278 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5279         {
5280                 .pa_start       = 0x48243000,
5281                 .pa_end         = 0x48243fff,
5282                 .flags          = ADDR_TYPE_RT
5283         },
5284         { }
5285 };
5286
5287 /* mpu_private -> prcm_mpu */
5288 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5289         .master         = &omap44xx_mpu_private_hwmod,
5290         .slave          = &omap44xx_prcm_mpu_hwmod,
5291         .clk            = "l3_div_ck",
5292         .addr           = omap44xx_prcm_mpu_addrs,
5293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5294 };
5295
5296 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5297         {
5298                 .pa_start       = 0x4a004000,
5299                 .pa_end         = 0x4a004fff,
5300                 .flags          = ADDR_TYPE_RT
5301         },
5302         { }
5303 };
5304
5305 /* l4_wkup -> cm_core_aon */
5306 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5307         .master         = &omap44xx_l4_wkup_hwmod,
5308         .slave          = &omap44xx_cm_core_aon_hwmod,
5309         .clk            = "l4_wkup_clk_mux_ck",
5310         .addr           = omap44xx_cm_core_aon_addrs,
5311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5312 };
5313
5314 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5315         {
5316                 .pa_start       = 0x4a008000,
5317                 .pa_end         = 0x4a009fff,
5318                 .flags          = ADDR_TYPE_RT
5319         },
5320         { }
5321 };
5322
5323 /* l4_cfg -> cm_core */
5324 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5325         .master         = &omap44xx_l4_cfg_hwmod,
5326         .slave          = &omap44xx_cm_core_hwmod,
5327         .clk            = "l4_div_ck",
5328         .addr           = omap44xx_cm_core_addrs,
5329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5330 };
5331
5332 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5333         {
5334                 .pa_start       = 0x4a306000,
5335                 .pa_end         = 0x4a307fff,
5336                 .flags          = ADDR_TYPE_RT
5337         },
5338         { }
5339 };
5340
5341 /* l4_wkup -> prm */
5342 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5343         .master         = &omap44xx_l4_wkup_hwmod,
5344         .slave          = &omap44xx_prm_hwmod,
5345         .clk            = "l4_wkup_clk_mux_ck",
5346         .addr           = omap44xx_prm_addrs,
5347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5348 };
5349
5350 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5351         {
5352                 .pa_start       = 0x4a30a000,
5353                 .pa_end         = 0x4a30a7ff,
5354                 .flags          = ADDR_TYPE_RT
5355         },
5356         { }
5357 };
5358
5359 /* l4_wkup -> scrm */
5360 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5361         .master         = &omap44xx_l4_wkup_hwmod,
5362         .slave          = &omap44xx_scrm_hwmod,
5363         .clk            = "l4_wkup_clk_mux_ck",
5364         .addr           = omap44xx_scrm_addrs,
5365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5366 };
5367
5368 /* l3_main_2 -> sl2if */
5369 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5370         .master         = &omap44xx_l3_main_2_hwmod,
5371         .slave          = &omap44xx_sl2if_hwmod,
5372         .clk            = "l3_div_ck",
5373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5374 };
5375
5376 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5377         {
5378                 .pa_start       = 0x4012c000,
5379                 .pa_end         = 0x4012c3ff,
5380                 .flags          = ADDR_TYPE_RT
5381         },
5382         { }
5383 };
5384
5385 /* l4_abe -> slimbus1 */
5386 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5387         .master         = &omap44xx_l4_abe_hwmod,
5388         .slave          = &omap44xx_slimbus1_hwmod,
5389         .clk            = "ocp_abe_iclk",
5390         .addr           = omap44xx_slimbus1_addrs,
5391         .user           = OCP_USER_MPU,
5392 };
5393
5394 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5395         {
5396                 .pa_start       = 0x4902c000,
5397                 .pa_end         = 0x4902c3ff,
5398                 .flags          = ADDR_TYPE_RT
5399         },
5400         { }
5401 };
5402
5403 /* l4_abe -> slimbus1 (dma) */
5404 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5405         .master         = &omap44xx_l4_abe_hwmod,
5406         .slave          = &omap44xx_slimbus1_hwmod,
5407         .clk            = "ocp_abe_iclk",
5408         .addr           = omap44xx_slimbus1_dma_addrs,
5409         .user           = OCP_USER_SDMA,
5410 };
5411
5412 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5413         {
5414                 .pa_start       = 0x48076000,
5415                 .pa_end         = 0x480763ff,
5416                 .flags          = ADDR_TYPE_RT
5417         },
5418         { }
5419 };
5420
5421 /* l4_per -> slimbus2 */
5422 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5423         .master         = &omap44xx_l4_per_hwmod,
5424         .slave          = &omap44xx_slimbus2_hwmod,
5425         .clk            = "l4_div_ck",
5426         .addr           = omap44xx_slimbus2_addrs,
5427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5428 };
5429
5430 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5431         {
5432                 .pa_start       = 0x4a0dd000,
5433                 .pa_end         = 0x4a0dd03f,
5434                 .flags          = ADDR_TYPE_RT
5435         },
5436         { }
5437 };
5438
5439 /* l4_cfg -> smartreflex_core */
5440 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5441         .master         = &omap44xx_l4_cfg_hwmod,
5442         .slave          = &omap44xx_smartreflex_core_hwmod,
5443         .clk            = "l4_div_ck",
5444         .addr           = omap44xx_smartreflex_core_addrs,
5445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5446 };
5447
5448 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5449         {
5450                 .pa_start       = 0x4a0db000,
5451                 .pa_end         = 0x4a0db03f,
5452                 .flags          = ADDR_TYPE_RT
5453         },
5454         { }
5455 };
5456
5457 /* l4_cfg -> smartreflex_iva */
5458 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5459         .master         = &omap44xx_l4_cfg_hwmod,
5460         .slave          = &omap44xx_smartreflex_iva_hwmod,
5461         .clk            = "l4_div_ck",
5462         .addr           = omap44xx_smartreflex_iva_addrs,
5463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5464 };
5465
5466 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5467         {
5468                 .pa_start       = 0x4a0d9000,
5469                 .pa_end         = 0x4a0d903f,
5470                 .flags          = ADDR_TYPE_RT
5471         },
5472         { }
5473 };
5474
5475 /* l4_cfg -> smartreflex_mpu */
5476 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5477         .master         = &omap44xx_l4_cfg_hwmod,
5478         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5479         .clk            = "l4_div_ck",
5480         .addr           = omap44xx_smartreflex_mpu_addrs,
5481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5482 };
5483
5484 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5485         {
5486                 .pa_start       = 0x4a0f6000,
5487                 .pa_end         = 0x4a0f6fff,
5488                 .flags          = ADDR_TYPE_RT
5489         },
5490         { }
5491 };
5492
5493 /* l4_cfg -> spinlock */
5494 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5495         .master         = &omap44xx_l4_cfg_hwmod,
5496         .slave          = &omap44xx_spinlock_hwmod,
5497         .clk            = "l4_div_ck",
5498         .addr           = omap44xx_spinlock_addrs,
5499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5500 };
5501
5502 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5503         {
5504                 .pa_start       = 0x4a318000,
5505                 .pa_end         = 0x4a31807f,
5506                 .flags          = ADDR_TYPE_RT
5507         },
5508         { }
5509 };
5510
5511 /* l4_wkup -> timer1 */
5512 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5513         .master         = &omap44xx_l4_wkup_hwmod,
5514         .slave          = &omap44xx_timer1_hwmod,
5515         .clk            = "l4_wkup_clk_mux_ck",
5516         .addr           = omap44xx_timer1_addrs,
5517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5518 };
5519
5520 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5521         {
5522                 .pa_start       = 0x48032000,
5523                 .pa_end         = 0x4803207f,
5524                 .flags          = ADDR_TYPE_RT
5525         },
5526         { }
5527 };
5528
5529 /* l4_per -> timer2 */
5530 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5531         .master         = &omap44xx_l4_per_hwmod,
5532         .slave          = &omap44xx_timer2_hwmod,
5533         .clk            = "l4_div_ck",
5534         .addr           = omap44xx_timer2_addrs,
5535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5536 };
5537
5538 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5539         {
5540                 .pa_start       = 0x48034000,
5541                 .pa_end         = 0x4803407f,
5542                 .flags          = ADDR_TYPE_RT
5543         },
5544         { }
5545 };
5546
5547 /* l4_per -> timer3 */
5548 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5549         .master         = &omap44xx_l4_per_hwmod,
5550         .slave          = &omap44xx_timer3_hwmod,
5551         .clk            = "l4_div_ck",
5552         .addr           = omap44xx_timer3_addrs,
5553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5554 };
5555
5556 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5557         {
5558                 .pa_start       = 0x48036000,
5559                 .pa_end         = 0x4803607f,
5560                 .flags          = ADDR_TYPE_RT
5561         },
5562         { }
5563 };
5564
5565 /* l4_per -> timer4 */
5566 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5567         .master         = &omap44xx_l4_per_hwmod,
5568         .slave          = &omap44xx_timer4_hwmod,
5569         .clk            = "l4_div_ck",
5570         .addr           = omap44xx_timer4_addrs,
5571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5572 };
5573
5574 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5575         {
5576                 .pa_start       = 0x40138000,
5577                 .pa_end         = 0x4013807f,
5578                 .flags          = ADDR_TYPE_RT
5579         },
5580         { }
5581 };
5582
5583 /* l4_abe -> timer5 */
5584 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5585         .master         = &omap44xx_l4_abe_hwmod,
5586         .slave          = &omap44xx_timer5_hwmod,
5587         .clk            = "ocp_abe_iclk",
5588         .addr           = omap44xx_timer5_addrs,
5589         .user           = OCP_USER_MPU,
5590 };
5591
5592 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5593         {
5594                 .pa_start       = 0x49038000,
5595                 .pa_end         = 0x4903807f,
5596                 .flags          = ADDR_TYPE_RT
5597         },
5598         { }
5599 };
5600
5601 /* l4_abe -> timer5 (dma) */
5602 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5603         .master         = &omap44xx_l4_abe_hwmod,
5604         .slave          = &omap44xx_timer5_hwmod,
5605         .clk            = "ocp_abe_iclk",
5606         .addr           = omap44xx_timer5_dma_addrs,
5607         .user           = OCP_USER_SDMA,
5608 };
5609
5610 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5611         {
5612                 .pa_start       = 0x4013a000,
5613                 .pa_end         = 0x4013a07f,
5614                 .flags          = ADDR_TYPE_RT
5615         },
5616         { }
5617 };
5618
5619 /* l4_abe -> timer6 */
5620 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5621         .master         = &omap44xx_l4_abe_hwmod,
5622         .slave          = &omap44xx_timer6_hwmod,
5623         .clk            = "ocp_abe_iclk",
5624         .addr           = omap44xx_timer6_addrs,
5625         .user           = OCP_USER_MPU,
5626 };
5627
5628 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5629         {
5630                 .pa_start       = 0x4903a000,
5631                 .pa_end         = 0x4903a07f,
5632                 .flags          = ADDR_TYPE_RT
5633         },
5634         { }
5635 };
5636
5637 /* l4_abe -> timer6 (dma) */
5638 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5639         .master         = &omap44xx_l4_abe_hwmod,
5640         .slave          = &omap44xx_timer6_hwmod,
5641         .clk            = "ocp_abe_iclk",
5642         .addr           = omap44xx_timer6_dma_addrs,
5643         .user           = OCP_USER_SDMA,
5644 };
5645
5646 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5647         {
5648                 .pa_start       = 0x4013c000,
5649                 .pa_end         = 0x4013c07f,
5650                 .flags          = ADDR_TYPE_RT
5651         },
5652         { }
5653 };
5654
5655 /* l4_abe -> timer7 */
5656 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5657         .master         = &omap44xx_l4_abe_hwmod,
5658         .slave          = &omap44xx_timer7_hwmod,
5659         .clk            = "ocp_abe_iclk",
5660         .addr           = omap44xx_timer7_addrs,
5661         .user           = OCP_USER_MPU,
5662 };
5663
5664 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5665         {
5666                 .pa_start       = 0x4903c000,
5667                 .pa_end         = 0x4903c07f,
5668                 .flags          = ADDR_TYPE_RT
5669         },
5670         { }
5671 };
5672
5673 /* l4_abe -> timer7 (dma) */
5674 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5675         .master         = &omap44xx_l4_abe_hwmod,
5676         .slave          = &omap44xx_timer7_hwmod,
5677         .clk            = "ocp_abe_iclk",
5678         .addr           = omap44xx_timer7_dma_addrs,
5679         .user           = OCP_USER_SDMA,
5680 };
5681
5682 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5683         {
5684                 .pa_start       = 0x4013e000,
5685                 .pa_end         = 0x4013e07f,
5686                 .flags          = ADDR_TYPE_RT
5687         },
5688         { }
5689 };
5690
5691 /* l4_abe -> timer8 */
5692 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5693         .master         = &omap44xx_l4_abe_hwmod,
5694         .slave          = &omap44xx_timer8_hwmod,
5695         .clk            = "ocp_abe_iclk",
5696         .addr           = omap44xx_timer8_addrs,
5697         .user           = OCP_USER_MPU,
5698 };
5699
5700 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5701         {
5702                 .pa_start       = 0x4903e000,
5703                 .pa_end         = 0x4903e07f,
5704                 .flags          = ADDR_TYPE_RT
5705         },
5706         { }
5707 };
5708
5709 /* l4_abe -> timer8 (dma) */
5710 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5711         .master         = &omap44xx_l4_abe_hwmod,
5712         .slave          = &omap44xx_timer8_hwmod,
5713         .clk            = "ocp_abe_iclk",
5714         .addr           = omap44xx_timer8_dma_addrs,
5715         .user           = OCP_USER_SDMA,
5716 };
5717
5718 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5719         {
5720                 .pa_start       = 0x4803e000,
5721                 .pa_end         = 0x4803e07f,
5722                 .flags          = ADDR_TYPE_RT
5723         },
5724         { }
5725 };
5726
5727 /* l4_per -> timer9 */
5728 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5729         .master         = &omap44xx_l4_per_hwmod,
5730         .slave          = &omap44xx_timer9_hwmod,
5731         .clk            = "l4_div_ck",
5732         .addr           = omap44xx_timer9_addrs,
5733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5734 };
5735
5736 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5737         {
5738                 .pa_start       = 0x48086000,
5739                 .pa_end         = 0x4808607f,
5740                 .flags          = ADDR_TYPE_RT
5741         },
5742         { }
5743 };
5744
5745 /* l4_per -> timer10 */
5746 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5747         .master         = &omap44xx_l4_per_hwmod,
5748         .slave          = &omap44xx_timer10_hwmod,
5749         .clk            = "l4_div_ck",
5750         .addr           = omap44xx_timer10_addrs,
5751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5752 };
5753
5754 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5755         {
5756                 .pa_start       = 0x48088000,
5757                 .pa_end         = 0x4808807f,
5758                 .flags          = ADDR_TYPE_RT
5759         },
5760         { }
5761 };
5762
5763 /* l4_per -> timer11 */
5764 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5765         .master         = &omap44xx_l4_per_hwmod,
5766         .slave          = &omap44xx_timer11_hwmod,
5767         .clk            = "l4_div_ck",
5768         .addr           = omap44xx_timer11_addrs,
5769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5770 };
5771
5772 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5773         {
5774                 .pa_start       = 0x4806a000,
5775                 .pa_end         = 0x4806a0ff,
5776                 .flags          = ADDR_TYPE_RT
5777         },
5778         { }
5779 };
5780
5781 /* l4_per -> uart1 */
5782 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5783         .master         = &omap44xx_l4_per_hwmod,
5784         .slave          = &omap44xx_uart1_hwmod,
5785         .clk            = "l4_div_ck",
5786         .addr           = omap44xx_uart1_addrs,
5787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5788 };
5789
5790 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5791         {
5792                 .pa_start       = 0x4806c000,
5793                 .pa_end         = 0x4806c0ff,
5794                 .flags          = ADDR_TYPE_RT
5795         },
5796         { }
5797 };
5798
5799 /* l4_per -> uart2 */
5800 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5801         .master         = &omap44xx_l4_per_hwmod,
5802         .slave          = &omap44xx_uart2_hwmod,
5803         .clk            = "l4_div_ck",
5804         .addr           = omap44xx_uart2_addrs,
5805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5806 };
5807
5808 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5809         {
5810                 .pa_start       = 0x48020000,
5811                 .pa_end         = 0x480200ff,
5812                 .flags          = ADDR_TYPE_RT
5813         },
5814         { }
5815 };
5816
5817 /* l4_per -> uart3 */
5818 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5819         .master         = &omap44xx_l4_per_hwmod,
5820         .slave          = &omap44xx_uart3_hwmod,
5821         .clk            = "l4_div_ck",
5822         .addr           = omap44xx_uart3_addrs,
5823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5824 };
5825
5826 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5827         {
5828                 .pa_start       = 0x4806e000,
5829                 .pa_end         = 0x4806e0ff,
5830                 .flags          = ADDR_TYPE_RT
5831         },
5832         { }
5833 };
5834
5835 /* l4_per -> uart4 */
5836 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5837         .master         = &omap44xx_l4_per_hwmod,
5838         .slave          = &omap44xx_uart4_hwmod,
5839         .clk            = "l4_div_ck",
5840         .addr           = omap44xx_uart4_addrs,
5841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5842 };
5843
5844 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5845         {
5846                 .pa_start       = 0x4a0a9000,
5847                 .pa_end         = 0x4a0a93ff,
5848                 .flags          = ADDR_TYPE_RT
5849         },
5850         { }
5851 };
5852
5853 /* l4_cfg -> usb_host_fs */
5854 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5855         .master         = &omap44xx_l4_cfg_hwmod,
5856         .slave          = &omap44xx_usb_host_fs_hwmod,
5857         .clk            = "l4_div_ck",
5858         .addr           = omap44xx_usb_host_fs_addrs,
5859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5860 };
5861
5862 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5863         {
5864                 .name           = "uhh",
5865                 .pa_start       = 0x4a064000,
5866                 .pa_end         = 0x4a0647ff,
5867                 .flags          = ADDR_TYPE_RT
5868         },
5869         {
5870                 .name           = "ohci",
5871                 .pa_start       = 0x4a064800,
5872                 .pa_end         = 0x4a064bff,
5873         },
5874         {
5875                 .name           = "ehci",
5876                 .pa_start       = 0x4a064c00,
5877                 .pa_end         = 0x4a064fff,
5878         },
5879         {}
5880 };
5881
5882 /* l4_cfg -> usb_host_hs */
5883 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5884         .master         = &omap44xx_l4_cfg_hwmod,
5885         .slave          = &omap44xx_usb_host_hs_hwmod,
5886         .clk            = "l4_div_ck",
5887         .addr           = omap44xx_usb_host_hs_addrs,
5888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5889 };
5890
5891 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5892         {
5893                 .pa_start       = 0x4a0ab000,
5894                 .pa_end         = 0x4a0ab003,
5895                 .flags          = ADDR_TYPE_RT
5896         },
5897         { }
5898 };
5899
5900 /* l4_cfg -> usb_otg_hs */
5901 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5902         .master         = &omap44xx_l4_cfg_hwmod,
5903         .slave          = &omap44xx_usb_otg_hs_hwmod,
5904         .clk            = "l4_div_ck",
5905         .addr           = omap44xx_usb_otg_hs_addrs,
5906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5907 };
5908
5909 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5910         {
5911                 .name           = "tll",
5912                 .pa_start       = 0x4a062000,
5913                 .pa_end         = 0x4a063fff,
5914                 .flags          = ADDR_TYPE_RT
5915         },
5916         {}
5917 };
5918
5919 /* l4_cfg -> usb_tll_hs */
5920 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5921         .master         = &omap44xx_l4_cfg_hwmod,
5922         .slave          = &omap44xx_usb_tll_hs_hwmod,
5923         .clk            = "l4_div_ck",
5924         .addr           = omap44xx_usb_tll_hs_addrs,
5925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5926 };
5927
5928 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5929         {
5930                 .pa_start       = 0x4a314000,
5931                 .pa_end         = 0x4a31407f,
5932                 .flags          = ADDR_TYPE_RT
5933         },
5934         { }
5935 };
5936
5937 /* l4_wkup -> wd_timer2 */
5938 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5939         .master         = &omap44xx_l4_wkup_hwmod,
5940         .slave          = &omap44xx_wd_timer2_hwmod,
5941         .clk            = "l4_wkup_clk_mux_ck",
5942         .addr           = omap44xx_wd_timer2_addrs,
5943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5944 };
5945
5946 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5947         {
5948                 .pa_start       = 0x40130000,
5949                 .pa_end         = 0x4013007f,
5950                 .flags          = ADDR_TYPE_RT
5951         },
5952         { }
5953 };
5954
5955 /* l4_abe -> wd_timer3 */
5956 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5957         .master         = &omap44xx_l4_abe_hwmod,
5958         .slave          = &omap44xx_wd_timer3_hwmod,
5959         .clk            = "ocp_abe_iclk",
5960         .addr           = omap44xx_wd_timer3_addrs,
5961         .user           = OCP_USER_MPU,
5962 };
5963
5964 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5965         {
5966                 .pa_start       = 0x49030000,
5967                 .pa_end         = 0x4903007f,
5968                 .flags          = ADDR_TYPE_RT
5969         },
5970         { }
5971 };
5972
5973 /* l4_abe -> wd_timer3 (dma) */
5974 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5975         .master         = &omap44xx_l4_abe_hwmod,
5976         .slave          = &omap44xx_wd_timer3_hwmod,
5977         .clk            = "ocp_abe_iclk",
5978         .addr           = omap44xx_wd_timer3_dma_addrs,
5979         .user           = OCP_USER_SDMA,
5980 };
5981
5982 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5983         &omap44xx_c2c__c2c_target_fw,
5984         &omap44xx_l4_cfg__c2c_target_fw,
5985         &omap44xx_l3_main_1__dmm,
5986         &omap44xx_mpu__dmm,
5987         &omap44xx_c2c__emif_fw,
5988         &omap44xx_dmm__emif_fw,
5989         &omap44xx_l4_cfg__emif_fw,
5990         &omap44xx_iva__l3_instr,
5991         &omap44xx_l3_main_3__l3_instr,
5992         &omap44xx_ocp_wp_noc__l3_instr,
5993         &omap44xx_dsp__l3_main_1,
5994         &omap44xx_dss__l3_main_1,
5995         &omap44xx_l3_main_2__l3_main_1,
5996         &omap44xx_l4_cfg__l3_main_1,
5997         &omap44xx_mmc1__l3_main_1,
5998         &omap44xx_mmc2__l3_main_1,
5999         &omap44xx_mpu__l3_main_1,
6000         &omap44xx_c2c_target_fw__l3_main_2,
6001         &omap44xx_debugss__l3_main_2,
6002         &omap44xx_dma_system__l3_main_2,
6003         &omap44xx_fdif__l3_main_2,
6004         &omap44xx_gpu__l3_main_2,
6005         &omap44xx_hsi__l3_main_2,
6006         &omap44xx_ipu__l3_main_2,
6007         &omap44xx_iss__l3_main_2,
6008         &omap44xx_iva__l3_main_2,
6009         &omap44xx_l3_main_1__l3_main_2,
6010         &omap44xx_l4_cfg__l3_main_2,
6011         &omap44xx_usb_host_fs__l3_main_2,
6012         &omap44xx_usb_host_hs__l3_main_2,
6013         &omap44xx_usb_otg_hs__l3_main_2,
6014         &omap44xx_l3_main_1__l3_main_3,
6015         &omap44xx_l3_main_2__l3_main_3,
6016         &omap44xx_l4_cfg__l3_main_3,
6017         &omap44xx_aess__l4_abe,
6018         &omap44xx_dsp__l4_abe,
6019         &omap44xx_l3_main_1__l4_abe,
6020         &omap44xx_mpu__l4_abe,
6021         &omap44xx_l3_main_1__l4_cfg,
6022         &omap44xx_l3_main_2__l4_per,
6023         &omap44xx_l4_cfg__l4_wkup,
6024         &omap44xx_mpu__mpu_private,
6025         &omap44xx_l4_cfg__ocp_wp_noc,
6026         &omap44xx_l4_abe__aess,
6027         &omap44xx_l4_abe__aess_dma,
6028         &omap44xx_l3_main_2__c2c,
6029         &omap44xx_l4_wkup__counter_32k,
6030         &omap44xx_l4_cfg__ctrl_module_core,
6031         &omap44xx_l4_cfg__ctrl_module_pad_core,
6032         &omap44xx_l4_wkup__ctrl_module_wkup,
6033         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6034         &omap44xx_l3_instr__debugss,
6035         &omap44xx_l4_cfg__dma_system,
6036         &omap44xx_l4_abe__dmic,
6037         &omap44xx_l4_abe__dmic_dma,
6038         &omap44xx_dsp__iva,
6039         &omap44xx_dsp__sl2if,
6040         &omap44xx_l4_cfg__dsp,
6041         &omap44xx_l3_main_2__dss,
6042         &omap44xx_l4_per__dss,
6043         &omap44xx_l3_main_2__dss_dispc,
6044         &omap44xx_l4_per__dss_dispc,
6045         &omap44xx_l3_main_2__dss_dsi1,
6046         &omap44xx_l4_per__dss_dsi1,
6047         &omap44xx_l3_main_2__dss_dsi2,
6048         &omap44xx_l4_per__dss_dsi2,
6049         &omap44xx_l3_main_2__dss_hdmi,
6050         &omap44xx_l4_per__dss_hdmi,
6051         &omap44xx_l3_main_2__dss_rfbi,
6052         &omap44xx_l4_per__dss_rfbi,
6053         &omap44xx_l3_main_2__dss_venc,
6054         &omap44xx_l4_per__dss_venc,
6055         &omap44xx_l4_per__elm,
6056         &omap44xx_emif_fw__emif1,
6057         &omap44xx_emif_fw__emif2,
6058         &omap44xx_l4_cfg__fdif,
6059         &omap44xx_l4_wkup__gpio1,
6060         &omap44xx_l4_per__gpio2,
6061         &omap44xx_l4_per__gpio3,
6062         &omap44xx_l4_per__gpio4,
6063         &omap44xx_l4_per__gpio5,
6064         &omap44xx_l4_per__gpio6,
6065         &omap44xx_l3_main_2__gpmc,
6066         &omap44xx_l3_main_2__gpu,
6067         &omap44xx_l4_per__hdq1w,
6068         &omap44xx_l4_cfg__hsi,
6069         &omap44xx_l4_per__i2c1,
6070         &omap44xx_l4_per__i2c2,
6071         &omap44xx_l4_per__i2c3,
6072         &omap44xx_l4_per__i2c4,
6073         &omap44xx_l3_main_2__ipu,
6074         &omap44xx_l3_main_2__iss,
6075         &omap44xx_iva__sl2if,
6076         &omap44xx_l3_main_2__iva,
6077         &omap44xx_l4_wkup__kbd,
6078         &omap44xx_l4_cfg__mailbox,
6079         &omap44xx_l4_abe__mcasp,
6080         &omap44xx_l4_abe__mcasp_dma,
6081         &omap44xx_l4_abe__mcbsp1,
6082         &omap44xx_l4_abe__mcbsp1_dma,
6083         &omap44xx_l4_abe__mcbsp2,
6084         &omap44xx_l4_abe__mcbsp2_dma,
6085         &omap44xx_l4_abe__mcbsp3,
6086         &omap44xx_l4_abe__mcbsp3_dma,
6087         &omap44xx_l4_per__mcbsp4,
6088         &omap44xx_l4_abe__mcpdm,
6089         &omap44xx_l4_abe__mcpdm_dma,
6090         &omap44xx_l4_per__mcspi1,
6091         &omap44xx_l4_per__mcspi2,
6092         &omap44xx_l4_per__mcspi3,
6093         &omap44xx_l4_per__mcspi4,
6094         &omap44xx_l4_per__mmc1,
6095         &omap44xx_l4_per__mmc2,
6096         &omap44xx_l4_per__mmc3,
6097         &omap44xx_l4_per__mmc4,
6098         &omap44xx_l4_per__mmc5,
6099         &omap44xx_l3_main_2__ocmc_ram,
6100         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6101         &omap44xx_mpu_private__prcm_mpu,
6102         &omap44xx_l4_wkup__cm_core_aon,
6103         &omap44xx_l4_cfg__cm_core,
6104         &omap44xx_l4_wkup__prm,
6105         &omap44xx_l4_wkup__scrm,
6106         &omap44xx_l3_main_2__sl2if,
6107         &omap44xx_l4_abe__slimbus1,
6108         &omap44xx_l4_abe__slimbus1_dma,
6109         &omap44xx_l4_per__slimbus2,
6110         &omap44xx_l4_cfg__smartreflex_core,
6111         &omap44xx_l4_cfg__smartreflex_iva,
6112         &omap44xx_l4_cfg__smartreflex_mpu,
6113         &omap44xx_l4_cfg__spinlock,
6114         &omap44xx_l4_wkup__timer1,
6115         &omap44xx_l4_per__timer2,
6116         &omap44xx_l4_per__timer3,
6117         &omap44xx_l4_per__timer4,
6118         &omap44xx_l4_abe__timer5,
6119         &omap44xx_l4_abe__timer5_dma,
6120         &omap44xx_l4_abe__timer6,
6121         &omap44xx_l4_abe__timer6_dma,
6122         &omap44xx_l4_abe__timer7,
6123         &omap44xx_l4_abe__timer7_dma,
6124         &omap44xx_l4_abe__timer8,
6125         &omap44xx_l4_abe__timer8_dma,
6126         &omap44xx_l4_per__timer9,
6127         &omap44xx_l4_per__timer10,
6128         &omap44xx_l4_per__timer11,
6129         &omap44xx_l4_per__uart1,
6130         &omap44xx_l4_per__uart2,
6131         &omap44xx_l4_per__uart3,
6132         &omap44xx_l4_per__uart4,
6133         &omap44xx_l4_cfg__usb_host_fs,
6134         &omap44xx_l4_cfg__usb_host_hs,
6135         &omap44xx_l4_cfg__usb_otg_hs,
6136         &omap44xx_l4_cfg__usb_tll_hs,
6137         &omap44xx_l4_wkup__wd_timer2,
6138         &omap44xx_l4_abe__wd_timer3,
6139         &omap44xx_l4_abe__wd_timer3_dma,
6140         NULL,
6141 };
6142
6143 int __init omap44xx_hwmod_init(void)
6144 {
6145         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6146 }
6147