arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  *  cm_core
 296  *  cm_core_aon
 297  *  debugss
 298  *  efuse_ctrl_cust
 299  *  efuse_ctrl_std
 300  *  mpu_c0
 301  *  mpu_c1
 302  *  prcm_mpu
 303  *  prm
 304  *  scrm
 305  *  usb_phy_cm
 306  *  usim
 307  */
 308
 309 /*
 310  * 'aess' class
 311  * audio engine sub system
 312  */
 313
 314 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 315         .rev_offs       = 0x0000,
 316         .sysc_offs      = 0x0010,
 317         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 318         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 319                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 320                            MSTANDBY_SMART_WKUP),
 321         .sysc_fields    = &omap_hwmod_sysc_type2,
 322 };
 323
 324 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 325         .name   = "aess",
 326         .sysc   = &omap44xx_aess_sysc,
 327 };
 328
 329 /* aess */
 330 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 331         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 332         { .irq = -1 }
 333 };
 334
 335 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 336         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 343         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 344         { .dma_req = -1 }
 345 };
 346
 347 static struct omap_hwmod omap44xx_aess_hwmod = {
 348         .name           = "aess",
 349         .class          = &omap44xx_aess_hwmod_class,
 350         .clkdm_name     = "abe_clkdm",
 351         .mpu_irqs       = omap44xx_aess_irqs,
 352         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 353         .main_clk       = "aess_fck",
 354         .prcm = {
 355                 .omap4 = {
 356                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 357                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 408                            SIDLE_SMART_WKUP),
 409         .sysc_fields    = &omap_hwmod_sysc_type1,
 410 };
 411
 412 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 413         .name   = "counter",
 414         .sysc   = &omap44xx_counter_sysc,
 415 };
 416
 417 /* counter_32k */
 418 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 419         .name           = "counter_32k",
 420         .class          = &omap44xx_counter_hwmod_class,
 421         .clkdm_name     = "l4_wkup_clkdm",
 422         .flags          = HWMOD_SWSUP_SIDLE,
 423         .main_clk       = "sys_32k_ck",
 424         .prcm = {
 425                 .omap4 = {
 426                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 427                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 428                 },
 429         },
 430 };
 431
 432 /*
 433  * 'ctrl_module' class
 434  * attila core control module + core pad control module + wkup pad control
 435  * module + attila wkup control module
 436  */
 437
 438 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 439         .rev_offs       = 0x0000,
 440         .sysc_offs      = 0x0010,
 441         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 443                            SIDLE_SMART_WKUP),
 444         .sysc_fields    = &omap_hwmod_sysc_type2,
 445 };
 446
 447 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 448         .name   = "ctrl_module",
 449         .sysc   = &omap44xx_ctrl_module_sysc,
 450 };
 451
 452 /* ctrl_module_core */
 453 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 454         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 455         { .irq = -1 }
 456 };
 457
 458 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 459         .name           = "ctrl_module_core",
 460         .class          = &omap44xx_ctrl_module_hwmod_class,
 461         .clkdm_name     = "l4_cfg_clkdm",
 462         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 463 };
 464
 465 /* ctrl_module_pad_core */
 466 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 467         .name           = "ctrl_module_pad_core",
 468         .class          = &omap44xx_ctrl_module_hwmod_class,
 469         .clkdm_name     = "l4_cfg_clkdm",
 470 };
 471
 472 /* ctrl_module_wkup */
 473 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 474         .name           = "ctrl_module_wkup",
 475         .class          = &omap44xx_ctrl_module_hwmod_class,
 476         .clkdm_name     = "l4_wkup_clkdm",
 477 };
 478
 479 /* ctrl_module_pad_wkup */
 480 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 481         .name           = "ctrl_module_pad_wkup",
 482         .class          = &omap44xx_ctrl_module_hwmod_class,
 483         .clkdm_name     = "l4_wkup_clkdm",
 484 };
 485
 486 /*
 487  * 'dma' class
 488  * dma controller for data exchange between memory to memory (i.e. internal or
 489  * external memory) and gp peripherals to memory or memory to gp peripherals
 490  */
 491
 492 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 493         .rev_offs       = 0x0000,
 494         .sysc_offs      = 0x002c,
 495         .syss_offs      = 0x0028,
 496         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 497                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 498                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 499                            SYSS_HAS_RESET_STATUS),
 500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 501                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 502         .sysc_fields    = &omap_hwmod_sysc_type1,
 503 };
 504
 505 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 506         .name   = "dma",
 507         .sysc   = &omap44xx_dma_sysc,
 508 };
 509
 510 /* dma dev_attr */
 511 static struct omap_dma_dev_attr dma_dev_attr = {
 512         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 513                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 514         .lch_count      = 32,
 515 };
 516
 517 /* dma_system */
 518 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 519         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 520         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 521         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 522         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 523         { .irq = -1 }
 524 };
 525
 526 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 527         .name           = "dma_system",
 528         .class          = &omap44xx_dma_hwmod_class,
 529         .clkdm_name     = "l3_dma_clkdm",
 530         .mpu_irqs       = omap44xx_dma_system_irqs,
 531         .main_clk       = "l3_div_ck",
 532         .prcm = {
 533                 .omap4 = {
 534                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 535                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 536                 },
 537         },
 538         .dev_attr       = &dma_dev_attr,
 539 };
 540
 541 /*
 542  * 'dmic' class
 543  * digital microphone controller
 544  */
 545
 546 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 547         .rev_offs       = 0x0000,
 548         .sysc_offs      = 0x0010,
 549         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 550                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 551         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 552                            SIDLE_SMART_WKUP),
 553         .sysc_fields    = &omap_hwmod_sysc_type2,
 554 };
 555
 556 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 557         .name   = "dmic",
 558         .sysc   = &omap44xx_dmic_sysc,
 559 };
 560
 561 /* dmic */
 562 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 563         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 564         { .irq = -1 }
 565 };
 566
 567 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 568         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 569         { .dma_req = -1 }
 570 };
 571
 572 static struct omap_hwmod omap44xx_dmic_hwmod = {
 573         .name           = "dmic",
 574         .class          = &omap44xx_dmic_hwmod_class,
 575         .clkdm_name     = "abe_clkdm",
 576         .mpu_irqs       = omap44xx_dmic_irqs,
 577         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 578         .main_clk       = "dmic_fck",
 579         .prcm = {
 580                 .omap4 = {
 581                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 582                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 583                         .modulemode   = MODULEMODE_SWCTRL,
 584                 },
 585         },
 586 };
 587
 588 /*
 589  * 'dsp' class
 590  * dsp sub-system
 591  */
 592
 593 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 594         .name   = "dsp",
 595 };
 596
 597 /* dsp */
 598 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 599         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 600         { .irq = -1 }
 601 };
 602
 603 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 604         { .name = "dsp", .rst_shift = 0 },
 605         { .name = "mmu_cache", .rst_shift = 1 },
 606 };
 607
 608 static struct omap_hwmod omap44xx_dsp_hwmod = {
 609         .name           = "dsp",
 610         .class          = &omap44xx_dsp_hwmod_class,
 611         .clkdm_name     = "tesla_clkdm",
 612         .mpu_irqs       = omap44xx_dsp_irqs,
 613         .rst_lines      = omap44xx_dsp_resets,
 614         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 615         .main_clk       = "dsp_fck",
 616         .prcm = {
 617                 .omap4 = {
 618                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 619                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 620                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 621                         .modulemode   = MODULEMODE_HWCTRL,
 622                 },
 623         },
 624 };
 625
 626 /*
 627  * 'dss' class
 628  * display sub-system
 629  */
 630
 631 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 632         .rev_offs       = 0x0000,
 633         .syss_offs      = 0x0014,
 634         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 635 };
 636
 637 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 638         .name   = "dss",
 639         .sysc   = &omap44xx_dss_sysc,
 640         .reset  = omap_dss_reset,
 641 };
 642
 643 /* dss */
 644 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 645         { .role = "sys_clk", .clk = "dss_sys_clk" },
 646         { .role = "tv_clk", .clk = "dss_tv_clk" },
 647         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 648 };
 649
 650 static struct omap_hwmod omap44xx_dss_hwmod = {
 651         .name           = "dss_core",
 652         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 653         .class          = &omap44xx_dss_hwmod_class,
 654         .clkdm_name     = "l3_dss_clkdm",
 655         .main_clk       = "dss_dss_clk",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 659                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 660                 },
 661         },
 662         .opt_clks       = dss_opt_clks,
 663         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 664 };
 665
 666 /*
 667  * 'dispc' class
 668  * display controller
 669  */
 670
 671 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 672         .rev_offs       = 0x0000,
 673         .sysc_offs      = 0x0010,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 676                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 677                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 678                            SYSS_HAS_RESET_STATUS),
 679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 680                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 681         .sysc_fields    = &omap_hwmod_sysc_type1,
 682 };
 683
 684 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 685         .name   = "dispc",
 686         .sysc   = &omap44xx_dispc_sysc,
 687 };
 688
 689 /* dss_dispc */
 690 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 691         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 692         { .irq = -1 }
 693 };
 694
 695 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 696         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 697         { .dma_req = -1 }
 698 };
 699
 700 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 701         .manager_count          = 3,
 702         .has_framedonetv_irq    = 1
 703 };
 704
 705 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 706         .name           = "dss_dispc",
 707         .class          = &omap44xx_dispc_hwmod_class,
 708         .clkdm_name     = "l3_dss_clkdm",
 709         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 710         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 711         .main_clk       = "dss_dss_clk",
 712         .prcm = {
 713                 .omap4 = {
 714                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 715                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 716                 },
 717         },
 718         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 719 };
 720
 721 /*
 722  * 'dsi' class
 723  * display serial interface controller
 724  */
 725
 726 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 727         .rev_offs       = 0x0000,
 728         .sysc_offs      = 0x0010,
 729         .syss_offs      = 0x0014,
 730         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 731                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 732                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 734         .sysc_fields    = &omap_hwmod_sysc_type1,
 735 };
 736
 737 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 738         .name   = "dsi",
 739         .sysc   = &omap44xx_dsi_sysc,
 740 };
 741
 742 /* dss_dsi1 */
 743 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 744         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 745         { .irq = -1 }
 746 };
 747
 748 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 749         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 750         { .dma_req = -1 }
 751 };
 752
 753 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 754         { .role = "sys_clk", .clk = "dss_sys_clk" },
 755 };
 756
 757 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 758         .name           = "dss_dsi1",
 759         .class          = &omap44xx_dsi_hwmod_class,
 760         .clkdm_name     = "l3_dss_clkdm",
 761         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 762         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 763         .main_clk       = "dss_dss_clk",
 764         .prcm = {
 765                 .omap4 = {
 766                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 767                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 768                 },
 769         },
 770         .opt_clks       = dss_dsi1_opt_clks,
 771         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 772 };
 773
 774 /* dss_dsi2 */
 775 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 776         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 777         { .irq = -1 }
 778 };
 779
 780 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 781         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 782         { .dma_req = -1 }
 783 };
 784
 785 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 786         { .role = "sys_clk", .clk = "dss_sys_clk" },
 787 };
 788
 789 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 790         .name           = "dss_dsi2",
 791         .class          = &omap44xx_dsi_hwmod_class,
 792         .clkdm_name     = "l3_dss_clkdm",
 793         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 794         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 795         .main_clk       = "dss_dss_clk",
 796         .prcm = {
 797                 .omap4 = {
 798                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 799                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 800                 },
 801         },
 802         .opt_clks       = dss_dsi2_opt_clks,
 803         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 804 };
 805
 806 /*
 807  * 'hdmi' class
 808  * hdmi controller
 809  */
 810
 811 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 812         .rev_offs       = 0x0000,
 813         .sysc_offs      = 0x0010,
 814         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 815                            SYSC_HAS_SOFTRESET),
 816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 817                            SIDLE_SMART_WKUP),
 818         .sysc_fields    = &omap_hwmod_sysc_type2,
 819 };
 820
 821 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 822         .name   = "hdmi",
 823         .sysc   = &omap44xx_hdmi_sysc,
 824 };
 825
 826 /* dss_hdmi */
 827 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 828         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 829         { .irq = -1 }
 830 };
 831
 832 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 833         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 834         { .dma_req = -1 }
 835 };
 836
 837 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 838         { .role = "sys_clk", .clk = "dss_sys_clk" },
 839 };
 840
 841 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 842         .name           = "dss_hdmi",
 843         .class          = &omap44xx_hdmi_hwmod_class,
 844         .clkdm_name     = "l3_dss_clkdm",
 845         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 846         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 847         .main_clk       = "dss_48mhz_clk",
 848         .prcm = {
 849                 .omap4 = {
 850                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 851                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 852                 },
 853         },
 854         .opt_clks       = dss_hdmi_opt_clks,
 855         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 856 };
 857
 858 /*
 859  * 'rfbi' class
 860  * remote frame buffer interface
 861  */
 862
 863 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 864         .rev_offs       = 0x0000,
 865         .sysc_offs      = 0x0010,
 866         .syss_offs      = 0x0014,
 867         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 868                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 869         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 870         .sysc_fields    = &omap_hwmod_sysc_type1,
 871 };
 872
 873 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 874         .name   = "rfbi",
 875         .sysc   = &omap44xx_rfbi_sysc,
 876 };
 877
 878 /* dss_rfbi */
 879 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 880         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 881         { .dma_req = -1 }
 882 };
 883
 884 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 885         { .role = "ick", .clk = "dss_fck" },
 886 };
 887
 888 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 889         .name           = "dss_rfbi",
 890         .class          = &omap44xx_rfbi_hwmod_class,
 891         .clkdm_name     = "l3_dss_clkdm",
 892         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 893         .main_clk       = "dss_dss_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_rfbi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 902 };
 903
 904 /*
 905  * 'venc' class
 906  * video encoder
 907  */
 908
 909 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 910         .name   = "venc",
 911 };
 912
 913 /* dss_venc */
 914 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 915         .name           = "dss_venc",
 916         .class          = &omap44xx_venc_hwmod_class,
 917         .clkdm_name     = "l3_dss_clkdm",
 918         .main_clk       = "dss_tv_clk",
 919         .prcm = {
 920                 .omap4 = {
 921                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 922                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 923                 },
 924         },
 925 };
 926
 927 /*
 928  * 'elm' class
 929  * bch error location module
 930  */
 931
 932 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 933         .rev_offs       = 0x0000,
 934         .sysc_offs      = 0x0010,
 935         .syss_offs      = 0x0014,
 936         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 937                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 938                            SYSS_HAS_RESET_STATUS),
 939         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 940         .sysc_fields    = &omap_hwmod_sysc_type1,
 941 };
 942
 943 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 944         .name   = "elm",
 945         .sysc   = &omap44xx_elm_sysc,
 946 };
 947
 948 /* elm */
 949 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 950         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 951         { .irq = -1 }
 952 };
 953
 954 static struct omap_hwmod omap44xx_elm_hwmod = {
 955         .name           = "elm",
 956         .class          = &omap44xx_elm_hwmod_class,
 957         .clkdm_name     = "l4_per_clkdm",
 958         .mpu_irqs       = omap44xx_elm_irqs,
 959         .prcm = {
 960                 .omap4 = {
 961                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 962                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 963                 },
 964         },
 965 };
 966
 967 /*
 968  * 'emif' class
 969  * external memory interface no1
 970  */
 971
 972 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 973         .rev_offs       = 0x0000,
 974 };
 975
 976 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 977         .name   = "emif",
 978         .sysc   = &omap44xx_emif_sysc,
 979 };
 980
 981 /* emif1 */
 982 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 983         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
 984         { .irq = -1 }
 985 };
 986
 987 static struct omap_hwmod omap44xx_emif1_hwmod = {
 988         .name           = "emif1",
 989         .class          = &omap44xx_emif_hwmod_class,
 990         .clkdm_name     = "l3_emif_clkdm",
 991         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 992         .mpu_irqs       = omap44xx_emif1_irqs,
 993         .main_clk       = "ddrphy_ck",
 994         .prcm = {
 995                 .omap4 = {
 996                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 997                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 998                         .modulemode   = MODULEMODE_HWCTRL,
 999                 },
1000         },
1001 };
1002
1003 /* emif2 */
1004 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1005         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1006         { .irq = -1 }
1007 };
1008
1009 static struct omap_hwmod omap44xx_emif2_hwmod = {
1010         .name           = "emif2",
1011         .class          = &omap44xx_emif_hwmod_class,
1012         .clkdm_name     = "l3_emif_clkdm",
1013         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1014         .mpu_irqs       = omap44xx_emif2_irqs,
1015         .main_clk       = "ddrphy_ck",
1016         .prcm = {
1017                 .omap4 = {
1018                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1019                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1020                         .modulemode   = MODULEMODE_HWCTRL,
1021                 },
1022         },
1023 };
1024
1025 /*
1026  * 'fdif' class
1027  * face detection hw accelerator module
1028  */
1029
1030 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1031         .rev_offs       = 0x0000,
1032         .sysc_offs      = 0x0010,
1033         /*
1034          * FDIF needs 100 OCP clk cycles delay after a softreset before
1035          * accessing sysconfig again.
1036          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1037          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1038          *
1039          * TODO: Indicate errata when available.
1040          */
1041         .srst_udelay    = 2,
1042         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1043                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1044         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1045                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1046         .sysc_fields    = &omap_hwmod_sysc_type2,
1047 };
1048
1049 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1050         .name   = "fdif",
1051         .sysc   = &omap44xx_fdif_sysc,
1052 };
1053
1054 /* fdif */
1055 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1056         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1057         { .irq = -1 }
1058 };
1059
1060 static struct omap_hwmod omap44xx_fdif_hwmod = {
1061         .name           = "fdif",
1062         .class          = &omap44xx_fdif_hwmod_class,
1063         .clkdm_name     = "iss_clkdm",
1064         .mpu_irqs       = omap44xx_fdif_irqs,
1065         .main_clk       = "fdif_fck",
1066         .prcm = {
1067                 .omap4 = {
1068                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1069                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1070                         .modulemode   = MODULEMODE_SWCTRL,
1071                 },
1072         },
1073 };
1074
1075 /*
1076  * 'gpio' class
1077  * general purpose io module
1078  */
1079
1080 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1081         .rev_offs       = 0x0000,
1082         .sysc_offs      = 0x0010,
1083         .syss_offs      = 0x0114,
1084         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1085                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1086                            SYSS_HAS_RESET_STATUS),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            SIDLE_SMART_WKUP),
1089         .sysc_fields    = &omap_hwmod_sysc_type1,
1090 };
1091
1092 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1093         .name   = "gpio",
1094         .sysc   = &omap44xx_gpio_sysc,
1095         .rev    = 2,
1096 };
1097
1098 /* gpio dev_attr */
1099 static struct omap_gpio_dev_attr gpio_dev_attr = {
1100         .bank_width     = 32,
1101         .dbck_flag      = true,
1102 };
1103
1104 /* gpio1 */
1105 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1106         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1107         { .irq = -1 }
1108 };
1109
1110 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1111         { .role = "dbclk", .clk = "gpio1_dbclk" },
1112 };
1113
1114 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1115         .name           = "gpio1",
1116         .class          = &omap44xx_gpio_hwmod_class,
1117         .clkdm_name     = "l4_wkup_clkdm",
1118         .mpu_irqs       = omap44xx_gpio1_irqs,
1119         .main_clk       = "gpio1_ick",
1120         .prcm = {
1121                 .omap4 = {
1122                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1123                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1124                         .modulemode   = MODULEMODE_HWCTRL,
1125                 },
1126         },
1127         .opt_clks       = gpio1_opt_clks,
1128         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1129         .dev_attr       = &gpio_dev_attr,
1130 };
1131
1132 /* gpio2 */
1133 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1134         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1135         { .irq = -1 }
1136 };
1137
1138 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1139         { .role = "dbclk", .clk = "gpio2_dbclk" },
1140 };
1141
1142 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1143         .name           = "gpio2",
1144         .class          = &omap44xx_gpio_hwmod_class,
1145         .clkdm_name     = "l4_per_clkdm",
1146         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1147         .mpu_irqs       = omap44xx_gpio2_irqs,
1148         .main_clk       = "gpio2_ick",
1149         .prcm = {
1150                 .omap4 = {
1151                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1152                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1153                         .modulemode   = MODULEMODE_HWCTRL,
1154                 },
1155         },
1156         .opt_clks       = gpio2_opt_clks,
1157         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1158         .dev_attr       = &gpio_dev_attr,
1159 };
1160
1161 /* gpio3 */
1162 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1163         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1164         { .irq = -1 }
1165 };
1166
1167 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1168         { .role = "dbclk", .clk = "gpio3_dbclk" },
1169 };
1170
1171 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1172         .name           = "gpio3",
1173         .class          = &omap44xx_gpio_hwmod_class,
1174         .clkdm_name     = "l4_per_clkdm",
1175         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1176         .mpu_irqs       = omap44xx_gpio3_irqs,
1177         .main_clk       = "gpio3_ick",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1181                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1182                         .modulemode   = MODULEMODE_HWCTRL,
1183                 },
1184         },
1185         .opt_clks       = gpio3_opt_clks,
1186         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1187         .dev_attr       = &gpio_dev_attr,
1188 };
1189
1190 /* gpio4 */
1191 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1192         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1193         { .irq = -1 }
1194 };
1195
1196 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1197         { .role = "dbclk", .clk = "gpio4_dbclk" },
1198 };
1199
1200 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1201         .name           = "gpio4",
1202         .class          = &omap44xx_gpio_hwmod_class,
1203         .clkdm_name     = "l4_per_clkdm",
1204         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1205         .mpu_irqs       = omap44xx_gpio4_irqs,
1206         .main_clk       = "gpio4_ick",
1207         .prcm = {
1208                 .omap4 = {
1209                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1210                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1211                         .modulemode   = MODULEMODE_HWCTRL,
1212                 },
1213         },
1214         .opt_clks       = gpio4_opt_clks,
1215         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1216         .dev_attr       = &gpio_dev_attr,
1217 };
1218
1219 /* gpio5 */
1220 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1221         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1222         { .irq = -1 }
1223 };
1224
1225 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1226         { .role = "dbclk", .clk = "gpio5_dbclk" },
1227 };
1228
1229 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1230         .name           = "gpio5",
1231         .class          = &omap44xx_gpio_hwmod_class,
1232         .clkdm_name     = "l4_per_clkdm",
1233         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1234         .mpu_irqs       = omap44xx_gpio5_irqs,
1235         .main_clk       = "gpio5_ick",
1236         .prcm = {
1237                 .omap4 = {
1238                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1239                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1240                         .modulemode   = MODULEMODE_HWCTRL,
1241                 },
1242         },
1243         .opt_clks       = gpio5_opt_clks,
1244         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1245         .dev_attr       = &gpio_dev_attr,
1246 };
1247
1248 /* gpio6 */
1249 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1250         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1251         { .irq = -1 }
1252 };
1253
1254 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1255         { .role = "dbclk", .clk = "gpio6_dbclk" },
1256 };
1257
1258 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1259         .name           = "gpio6",
1260         .class          = &omap44xx_gpio_hwmod_class,
1261         .clkdm_name     = "l4_per_clkdm",
1262         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1263         .mpu_irqs       = omap44xx_gpio6_irqs,
1264         .main_clk       = "gpio6_ick",
1265         .prcm = {
1266                 .omap4 = {
1267                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1268                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1269                         .modulemode   = MODULEMODE_HWCTRL,
1270                 },
1271         },
1272         .opt_clks       = gpio6_opt_clks,
1273         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1274         .dev_attr       = &gpio_dev_attr,
1275 };
1276
1277 /*
1278  * 'gpmc' class
1279  * general purpose memory controller
1280  */
1281
1282 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1283         .rev_offs       = 0x0000,
1284         .sysc_offs      = 0x0010,
1285         .syss_offs      = 0x0014,
1286         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1287                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1288         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1289         .sysc_fields    = &omap_hwmod_sysc_type1,
1290 };
1291
1292 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1293         .name   = "gpmc",
1294         .sysc   = &omap44xx_gpmc_sysc,
1295 };
1296
1297 /* gpmc */
1298 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1299         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1300         { .irq = -1 }
1301 };
1302
1303 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1304         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1305         { .dma_req = -1 }
1306 };
1307
1308 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1309         .name           = "gpmc",
1310         .class          = &omap44xx_gpmc_hwmod_class,
1311         .clkdm_name     = "l3_2_clkdm",
1312         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1313         .mpu_irqs       = omap44xx_gpmc_irqs,
1314         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1315         .prcm = {
1316                 .omap4 = {
1317                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1318                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1319                         .modulemode   = MODULEMODE_HWCTRL,
1320                 },
1321         },
1322 };
1323
1324 /*
1325  * 'gpu' class
1326  * 2d/3d graphics accelerator
1327  */
1328
1329 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1330         .rev_offs       = 0x1fc00,
1331         .sysc_offs      = 0x1fc10,
1332         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1334                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1335                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1336         .sysc_fields    = &omap_hwmod_sysc_type2,
1337 };
1338
1339 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1340         .name   = "gpu",
1341         .sysc   = &omap44xx_gpu_sysc,
1342 };
1343
1344 /* gpu */
1345 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1346         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1347         { .irq = -1 }
1348 };
1349
1350 static struct omap_hwmod omap44xx_gpu_hwmod = {
1351         .name           = "gpu",
1352         .class          = &omap44xx_gpu_hwmod_class,
1353         .clkdm_name     = "l3_gfx_clkdm",
1354         .mpu_irqs       = omap44xx_gpu_irqs,
1355         .main_clk       = "gpu_fck",
1356         .prcm = {
1357                 .omap4 = {
1358                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1359                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1360                         .modulemode   = MODULEMODE_SWCTRL,
1361                 },
1362         },
1363 };
1364
1365 /*
1366  * 'hdq1w' class
1367  * hdq / 1-wire serial interface controller
1368  */
1369
1370 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1371         .rev_offs       = 0x0000,
1372         .sysc_offs      = 0x0014,
1373         .syss_offs      = 0x0018,
1374         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1375                            SYSS_HAS_RESET_STATUS),
1376         .sysc_fields    = &omap_hwmod_sysc_type1,
1377 };
1378
1379 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1380         .name   = "hdq1w",
1381         .sysc   = &omap44xx_hdq1w_sysc,
1382 };
1383
1384 /* hdq1w */
1385 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1386         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1387         { .irq = -1 }
1388 };
1389
1390 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1391         .name           = "hdq1w",
1392         .class          = &omap44xx_hdq1w_hwmod_class,
1393         .clkdm_name     = "l4_per_clkdm",
1394         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1395         .mpu_irqs       = omap44xx_hdq1w_irqs,
1396         .main_clk       = "hdq1w_fck",
1397         .prcm = {
1398                 .omap4 = {
1399                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1400                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1401                         .modulemode   = MODULEMODE_SWCTRL,
1402                 },
1403         },
1404 };
1405
1406 /*
1407  * 'hsi' class
1408  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1409  * serial if)
1410  */
1411
1412 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1413         .rev_offs       = 0x0000,
1414         .sysc_offs      = 0x0010,
1415         .syss_offs      = 0x0014,
1416         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1417                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1418                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1419         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1420                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1421                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1422         .sysc_fields    = &omap_hwmod_sysc_type1,
1423 };
1424
1425 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1426         .name   = "hsi",
1427         .sysc   = &omap44xx_hsi_sysc,
1428 };
1429
1430 /* hsi */
1431 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1432         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1433         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1434         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1435         { .irq = -1 }
1436 };
1437
1438 static struct omap_hwmod omap44xx_hsi_hwmod = {
1439         .name           = "hsi",
1440         .class          = &omap44xx_hsi_hwmod_class,
1441         .clkdm_name     = "l3_init_clkdm",
1442         .mpu_irqs       = omap44xx_hsi_irqs,
1443         .main_clk       = "hsi_fck",
1444         .prcm = {
1445                 .omap4 = {
1446                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1447                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1448                         .modulemode   = MODULEMODE_HWCTRL,
1449                 },
1450         },
1451 };
1452
1453 /*
1454  * 'i2c' class
1455  * multimaster high-speed i2c controller
1456  */
1457
1458 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1459         .sysc_offs      = 0x0010,
1460         .syss_offs      = 0x0090,
1461         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1462                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1463                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1464         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1465                            SIDLE_SMART_WKUP),
1466         .clockact       = CLOCKACT_TEST_ICLK,
1467         .sysc_fields    = &omap_hwmod_sysc_type1,
1468 };
1469
1470 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1471         .name   = "i2c",
1472         .sysc   = &omap44xx_i2c_sysc,
1473         .rev    = OMAP_I2C_IP_VERSION_2,
1474         .reset  = &omap_i2c_reset,
1475 };
1476
1477 static struct omap_i2c_dev_attr i2c_dev_attr = {
1478         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1479 };
1480
1481 /* i2c1 */
1482 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1483         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1484         { .irq = -1 }
1485 };
1486
1487 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1488         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1489         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1490         { .dma_req = -1 }
1491 };
1492
1493 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1494         .name           = "i2c1",
1495         .class          = &omap44xx_i2c_hwmod_class,
1496         .clkdm_name     = "l4_per_clkdm",
1497         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1498         .mpu_irqs       = omap44xx_i2c1_irqs,
1499         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1500         .main_clk       = "i2c1_fck",
1501         .prcm = {
1502                 .omap4 = {
1503                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1504                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1505                         .modulemode   = MODULEMODE_SWCTRL,
1506                 },
1507         },
1508         .dev_attr       = &i2c_dev_attr,
1509 };
1510
1511 /* i2c2 */
1512 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1513         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1514         { .irq = -1 }
1515 };
1516
1517 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1518         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1519         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1520         { .dma_req = -1 }
1521 };
1522
1523 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1524         .name           = "i2c2",
1525         .class          = &omap44xx_i2c_hwmod_class,
1526         .clkdm_name     = "l4_per_clkdm",
1527         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1528         .mpu_irqs       = omap44xx_i2c2_irqs,
1529         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1530         .main_clk       = "i2c2_fck",
1531         .prcm = {
1532                 .omap4 = {
1533                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1534                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1535                         .modulemode   = MODULEMODE_SWCTRL,
1536                 },
1537         },
1538         .dev_attr       = &i2c_dev_attr,
1539 };
1540
1541 /* i2c3 */
1542 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1543         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1544         { .irq = -1 }
1545 };
1546
1547 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1548         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1549         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1550         { .dma_req = -1 }
1551 };
1552
1553 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1554         .name           = "i2c3",
1555         .class          = &omap44xx_i2c_hwmod_class,
1556         .clkdm_name     = "l4_per_clkdm",
1557         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1558         .mpu_irqs       = omap44xx_i2c3_irqs,
1559         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1560         .main_clk       = "i2c3_fck",
1561         .prcm = {
1562                 .omap4 = {
1563                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1564                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1565                         .modulemode   = MODULEMODE_SWCTRL,
1566                 },
1567         },
1568         .dev_attr       = &i2c_dev_attr,
1569 };
1570
1571 /* i2c4 */
1572 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1573         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1574         { .irq = -1 }
1575 };
1576
1577 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1578         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1579         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1580         { .dma_req = -1 }
1581 };
1582
1583 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1584         .name           = "i2c4",
1585         .class          = &omap44xx_i2c_hwmod_class,
1586         .clkdm_name     = "l4_per_clkdm",
1587         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1588         .mpu_irqs       = omap44xx_i2c4_irqs,
1589         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1590         .main_clk       = "i2c4_fck",
1591         .prcm = {
1592                 .omap4 = {
1593                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1594                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1595                         .modulemode   = MODULEMODE_SWCTRL,
1596                 },
1597         },
1598         .dev_attr       = &i2c_dev_attr,
1599 };
1600
1601 /*
1602  * 'ipu' class
1603  * imaging processor unit
1604  */
1605
1606 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1607         .name   = "ipu",
1608 };
1609
1610 /* ipu */
1611 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1612         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1613         { .irq = -1 }
1614 };
1615
1616 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1617         { .name = "cpu0", .rst_shift = 0 },
1618         { .name = "cpu1", .rst_shift = 1 },
1619         { .name = "mmu_cache", .rst_shift = 2 },
1620 };
1621
1622 static struct omap_hwmod omap44xx_ipu_hwmod = {
1623         .name           = "ipu",
1624         .class          = &omap44xx_ipu_hwmod_class,
1625         .clkdm_name     = "ducati_clkdm",
1626         .mpu_irqs       = omap44xx_ipu_irqs,
1627         .rst_lines      = omap44xx_ipu_resets,
1628         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1629         .main_clk       = "ipu_fck",
1630         .prcm = {
1631                 .omap4 = {
1632                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1633                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1634                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1635                         .modulemode   = MODULEMODE_HWCTRL,
1636                 },
1637         },
1638 };
1639
1640 /*
1641  * 'iss' class
1642  * external images sensor pixel data processor
1643  */
1644
1645 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1646         .rev_offs       = 0x0000,
1647         .sysc_offs      = 0x0010,
1648         /*
1649          * ISS needs 100 OCP clk cycles delay after a softreset before
1650          * accessing sysconfig again.
1651          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1652          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1653          *
1654          * TODO: Indicate errata when available.
1655          */
1656         .srst_udelay    = 2,
1657         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1658                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1659         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1660                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1661                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1662         .sysc_fields    = &omap_hwmod_sysc_type2,
1663 };
1664
1665 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1666         .name   = "iss",
1667         .sysc   = &omap44xx_iss_sysc,
1668 };
1669
1670 /* iss */
1671 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1672         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1673         { .irq = -1 }
1674 };
1675
1676 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1677         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1678         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1679         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1680         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1681         { .dma_req = -1 }
1682 };
1683
1684 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1685         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1686 };
1687
1688 static struct omap_hwmod omap44xx_iss_hwmod = {
1689         .name           = "iss",
1690         .class          = &omap44xx_iss_hwmod_class,
1691         .clkdm_name     = "iss_clkdm",
1692         .mpu_irqs       = omap44xx_iss_irqs,
1693         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1694         .main_clk       = "iss_fck",
1695         .prcm = {
1696                 .omap4 = {
1697                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1698                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1699                         .modulemode   = MODULEMODE_SWCTRL,
1700                 },
1701         },
1702         .opt_clks       = iss_opt_clks,
1703         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1704 };
1705
1706 /*
1707  * 'iva' class
1708  * multi-standard video encoder/decoder hardware accelerator
1709  */
1710
1711 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1712         .name   = "iva",
1713 };
1714
1715 /* iva */
1716 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1717         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1718         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1719         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1720         { .irq = -1 }
1721 };
1722
1723 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1724         { .name = "seq0", .rst_shift = 0 },
1725         { .name = "seq1", .rst_shift = 1 },
1726         { .name = "logic", .rst_shift = 2 },
1727 };
1728
1729 static struct omap_hwmod omap44xx_iva_hwmod = {
1730         .name           = "iva",
1731         .class          = &omap44xx_iva_hwmod_class,
1732         .clkdm_name     = "ivahd_clkdm",
1733         .mpu_irqs       = omap44xx_iva_irqs,
1734         .rst_lines      = omap44xx_iva_resets,
1735         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1736         .main_clk       = "iva_fck",
1737         .prcm = {
1738                 .omap4 = {
1739                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1740                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1741                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1742                         .modulemode   = MODULEMODE_HWCTRL,
1743                 },
1744         },
1745 };
1746
1747 /*
1748  * 'kbd' class
1749  * keyboard controller
1750  */
1751
1752 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1753         .rev_offs       = 0x0000,
1754         .sysc_offs      = 0x0010,
1755         .syss_offs      = 0x0014,
1756         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1757                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1758                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1759                            SYSS_HAS_RESET_STATUS),
1760         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1761         .sysc_fields    = &omap_hwmod_sysc_type1,
1762 };
1763
1764 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1765         .name   = "kbd",
1766         .sysc   = &omap44xx_kbd_sysc,
1767 };
1768
1769 /* kbd */
1770 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1771         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod omap44xx_kbd_hwmod = {
1776         .name           = "kbd",
1777         .class          = &omap44xx_kbd_hwmod_class,
1778         .clkdm_name     = "l4_wkup_clkdm",
1779         .mpu_irqs       = omap44xx_kbd_irqs,
1780         .main_clk       = "kbd_fck",
1781         .prcm = {
1782                 .omap4 = {
1783                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1784                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1785                         .modulemode   = MODULEMODE_SWCTRL,
1786                 },
1787         },
1788 };
1789
1790 /*
1791  * 'mailbox' class
1792  * mailbox module allowing communication between the on-chip processors using a
1793  * queued mailbox-interrupt mechanism.
1794  */
1795
1796 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1797         .rev_offs       = 0x0000,
1798         .sysc_offs      = 0x0010,
1799         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1800                            SYSC_HAS_SOFTRESET),
1801         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1802         .sysc_fields    = &omap_hwmod_sysc_type2,
1803 };
1804
1805 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1806         .name   = "mailbox",
1807         .sysc   = &omap44xx_mailbox_sysc,
1808 };
1809
1810 /* mailbox */
1811 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1812         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1813         { .irq = -1 }
1814 };
1815
1816 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1817         .name           = "mailbox",
1818         .class          = &omap44xx_mailbox_hwmod_class,
1819         .clkdm_name     = "l4_cfg_clkdm",
1820         .mpu_irqs       = omap44xx_mailbox_irqs,
1821         .prcm = {
1822                 .omap4 = {
1823                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1824                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1825                 },
1826         },
1827 };
1828
1829 /*
1830  * 'mcasp' class
1831  * multi-channel audio serial port controller
1832  */
1833
1834 /* The IP is not compliant to type1 / type2 scheme */
1835 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1836         .sidle_shift    = 0,
1837 };
1838
1839 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1840         .sysc_offs      = 0x0004,
1841         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1842         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1843                            SIDLE_SMART_WKUP),
1844         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1845 };
1846
1847 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1848         .name   = "mcasp",
1849         .sysc   = &omap44xx_mcasp_sysc,
1850 };
1851
1852 /* mcasp */
1853 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1854         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1855         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1856         { .irq = -1 }
1857 };
1858
1859 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1860         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1861         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1862         { .dma_req = -1 }
1863 };
1864
1865 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1866         .name           = "mcasp",
1867         .class          = &omap44xx_mcasp_hwmod_class,
1868         .clkdm_name     = "abe_clkdm",
1869         .mpu_irqs       = omap44xx_mcasp_irqs,
1870         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1871         .main_clk       = "mcasp_fck",
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1875                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1876                         .modulemode   = MODULEMODE_SWCTRL,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcbsp' class
1883  * multi channel buffered serial port controller
1884  */
1885
1886 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1887         .sysc_offs      = 0x008c,
1888         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1889                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1890         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1891         .sysc_fields    = &omap_hwmod_sysc_type1,
1892 };
1893
1894 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1895         .name   = "mcbsp",
1896         .sysc   = &omap44xx_mcbsp_sysc,
1897         .rev    = MCBSP_CONFIG_TYPE4,
1898 };
1899
1900 /* mcbsp1 */
1901 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1902         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
1903         { .irq = -1 }
1904 };
1905
1906 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1907         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1908         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1909         { .dma_req = -1 }
1910 };
1911
1912 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1913         { .role = "pad_fck", .clk = "pad_clks_ck" },
1914         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1918         .name           = "mcbsp1",
1919         .class          = &omap44xx_mcbsp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1922         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1923         .main_clk       = "mcbsp1_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931         .opt_clks       = mcbsp1_opt_clks,
1932         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1933 };
1934
1935 /* mcbsp2 */
1936 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1937         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
1938         { .irq = -1 }
1939 };
1940
1941 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1942         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1943         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1944         { .dma_req = -1 }
1945 };
1946
1947 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1948         { .role = "pad_fck", .clk = "pad_clks_ck" },
1949         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1950 };
1951
1952 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1953         .name           = "mcbsp2",
1954         .class          = &omap44xx_mcbsp_hwmod_class,
1955         .clkdm_name     = "abe_clkdm",
1956         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1957         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1958         .main_clk       = "mcbsp2_fck",
1959         .prcm = {
1960                 .omap4 = {
1961                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1962                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1963                         .modulemode   = MODULEMODE_SWCTRL,
1964                 },
1965         },
1966         .opt_clks       = mcbsp2_opt_clks,
1967         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1968 };
1969
1970 /* mcbsp3 */
1971 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1972         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
1973         { .irq = -1 }
1974 };
1975
1976 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1977         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1978         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1979         { .dma_req = -1 }
1980 };
1981
1982 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1983         { .role = "pad_fck", .clk = "pad_clks_ck" },
1984         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
1985 };
1986
1987 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1988         .name           = "mcbsp3",
1989         .class          = &omap44xx_mcbsp_hwmod_class,
1990         .clkdm_name     = "abe_clkdm",
1991         .mpu_irqs       = omap44xx_mcbsp3_irqs,
1992         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
1993         .main_clk       = "mcbsp3_fck",
1994         .prcm = {
1995                 .omap4 = {
1996                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1997                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1998                         .modulemode   = MODULEMODE_SWCTRL,
1999                 },
2000         },
2001         .opt_clks       = mcbsp3_opt_clks,
2002         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2003 };
2004
2005 /* mcbsp4 */
2006 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2007         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2008         { .irq = -1 }
2009 };
2010
2011 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2012         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2013         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2014         { .dma_req = -1 }
2015 };
2016
2017 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2018         { .role = "pad_fck", .clk = "pad_clks_ck" },
2019         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2020 };
2021
2022 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2023         .name           = "mcbsp4",
2024         .class          = &omap44xx_mcbsp_hwmod_class,
2025         .clkdm_name     = "l4_per_clkdm",
2026         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2027         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2028         .main_clk       = "mcbsp4_fck",
2029         .prcm = {
2030                 .omap4 = {
2031                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2032                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2033                         .modulemode   = MODULEMODE_SWCTRL,
2034                 },
2035         },
2036         .opt_clks       = mcbsp4_opt_clks,
2037         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2038 };
2039
2040 /*
2041  * 'mcpdm' class
2042  * multi channel pdm controller (proprietary interface with phoenix power
2043  * ic)
2044  */
2045
2046 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2047         .rev_offs       = 0x0000,
2048         .sysc_offs      = 0x0010,
2049         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2050                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2051         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2052                            SIDLE_SMART_WKUP),
2053         .sysc_fields    = &omap_hwmod_sysc_type2,
2054 };
2055
2056 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2057         .name   = "mcpdm",
2058         .sysc   = &omap44xx_mcpdm_sysc,
2059 };
2060
2061 /* mcpdm */
2062 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2063         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2064         { .irq = -1 }
2065 };
2066
2067 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2068         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2069         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2070         { .dma_req = -1 }
2071 };
2072
2073 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2074         .name           = "mcpdm",
2075         .class          = &omap44xx_mcpdm_hwmod_class,
2076         .clkdm_name     = "abe_clkdm",
2077         .mpu_irqs       = omap44xx_mcpdm_irqs,
2078         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2079         .main_clk       = "mcpdm_fck",
2080         .prcm = {
2081                 .omap4 = {
2082                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2083                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2084                         .modulemode   = MODULEMODE_SWCTRL,
2085                 },
2086         },
2087 };
2088
2089 /*
2090  * 'mcspi' class
2091  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2092  * bus
2093  */
2094
2095 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2096         .rev_offs       = 0x0000,
2097         .sysc_offs      = 0x0010,
2098         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2099                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2100         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2101                            SIDLE_SMART_WKUP),
2102         .sysc_fields    = &omap_hwmod_sysc_type2,
2103 };
2104
2105 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2106         .name   = "mcspi",
2107         .sysc   = &omap44xx_mcspi_sysc,
2108         .rev    = OMAP4_MCSPI_REV,
2109 };
2110
2111 /* mcspi1 */
2112 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2113         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2114         { .irq = -1 }
2115 };
2116
2117 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2118         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2119         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2120         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2121         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2122         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2123         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2124         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2125         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2126         { .dma_req = -1 }
2127 };
2128
2129 /* mcspi1 dev_attr */
2130 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2131         .num_chipselect = 4,
2132 };
2133
2134 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2135         .name           = "mcspi1",
2136         .class          = &omap44xx_mcspi_hwmod_class,
2137         .clkdm_name     = "l4_per_clkdm",
2138         .mpu_irqs       = omap44xx_mcspi1_irqs,
2139         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2140         .main_clk       = "mcspi1_fck",
2141         .prcm = {
2142                 .omap4 = {
2143                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2144                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2145                         .modulemode   = MODULEMODE_SWCTRL,
2146                 },
2147         },
2148         .dev_attr       = &mcspi1_dev_attr,
2149 };
2150
2151 /* mcspi2 */
2152 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2153         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2154         { .irq = -1 }
2155 };
2156
2157 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2158         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2159         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2160         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2161         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2162         { .dma_req = -1 }
2163 };
2164
2165 /* mcspi2 dev_attr */
2166 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2167         .num_chipselect = 2,
2168 };
2169
2170 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2171         .name           = "mcspi2",
2172         .class          = &omap44xx_mcspi_hwmod_class,
2173         .clkdm_name     = "l4_per_clkdm",
2174         .mpu_irqs       = omap44xx_mcspi2_irqs,
2175         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2176         .main_clk       = "mcspi2_fck",
2177         .prcm = {
2178                 .omap4 = {
2179                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2180                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2181                         .modulemode   = MODULEMODE_SWCTRL,
2182                 },
2183         },
2184         .dev_attr       = &mcspi2_dev_attr,
2185 };
2186
2187 /* mcspi3 */
2188 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2189         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2190         { .irq = -1 }
2191 };
2192
2193 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2194         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2195         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2196         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2197         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2198         { .dma_req = -1 }
2199 };
2200
2201 /* mcspi3 dev_attr */
2202 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2203         .num_chipselect = 2,
2204 };
2205
2206 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2207         .name           = "mcspi3",
2208         .class          = &omap44xx_mcspi_hwmod_class,
2209         .clkdm_name     = "l4_per_clkdm",
2210         .mpu_irqs       = omap44xx_mcspi3_irqs,
2211         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2212         .main_clk       = "mcspi3_fck",
2213         .prcm = {
2214                 .omap4 = {
2215                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2216                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2217                         .modulemode   = MODULEMODE_SWCTRL,
2218                 },
2219         },
2220         .dev_attr       = &mcspi3_dev_attr,
2221 };
2222
2223 /* mcspi4 */
2224 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2225         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2226         { .irq = -1 }
2227 };
2228
2229 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2230         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2231         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2232         { .dma_req = -1 }
2233 };
2234
2235 /* mcspi4 dev_attr */
2236 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2237         .num_chipselect = 1,
2238 };
2239
2240 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2241         .name           = "mcspi4",
2242         .class          = &omap44xx_mcspi_hwmod_class,
2243         .clkdm_name     = "l4_per_clkdm",
2244         .mpu_irqs       = omap44xx_mcspi4_irqs,
2245         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2246         .main_clk       = "mcspi4_fck",
2247         .prcm = {
2248                 .omap4 = {
2249                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2250                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2251                         .modulemode   = MODULEMODE_SWCTRL,
2252                 },
2253         },
2254         .dev_attr       = &mcspi4_dev_attr,
2255 };
2256
2257 /*
2258  * 'mmc' class
2259  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2260  */
2261
2262 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2263         .rev_offs       = 0x0000,
2264         .sysc_offs      = 0x0010,
2265         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2266                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2267                            SYSC_HAS_SOFTRESET),
2268         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2269                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2270                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2271         .sysc_fields    = &omap_hwmod_sysc_type2,
2272 };
2273
2274 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2275         .name   = "mmc",
2276         .sysc   = &omap44xx_mmc_sysc,
2277 };
2278
2279 /* mmc1 */
2280 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2281         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2282         { .irq = -1 }
2283 };
2284
2285 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2286         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2287         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2288         { .dma_req = -1 }
2289 };
2290
2291 /* mmc1 dev_attr */
2292 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2293         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2294 };
2295
2296 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2297         .name           = "mmc1",
2298         .class          = &omap44xx_mmc_hwmod_class,
2299         .clkdm_name     = "l3_init_clkdm",
2300         .mpu_irqs       = omap44xx_mmc1_irqs,
2301         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2302         .main_clk       = "mmc1_fck",
2303         .prcm = {
2304                 .omap4 = {
2305                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2306                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2307                         .modulemode   = MODULEMODE_SWCTRL,
2308                 },
2309         },
2310         .dev_attr       = &mmc1_dev_attr,
2311 };
2312
2313 /* mmc2 */
2314 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2315         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2316         { .irq = -1 }
2317 };
2318
2319 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2320         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2321         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2322         { .dma_req = -1 }
2323 };
2324
2325 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2326         .name           = "mmc2",
2327         .class          = &omap44xx_mmc_hwmod_class,
2328         .clkdm_name     = "l3_init_clkdm",
2329         .mpu_irqs       = omap44xx_mmc2_irqs,
2330         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2331         .main_clk       = "mmc2_fck",
2332         .prcm = {
2333                 .omap4 = {
2334                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2335                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2336                         .modulemode   = MODULEMODE_SWCTRL,
2337                 },
2338         },
2339 };
2340
2341 /* mmc3 */
2342 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2343         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2344         { .irq = -1 }
2345 };
2346
2347 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2348         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2349         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2350         { .dma_req = -1 }
2351 };
2352
2353 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2354         .name           = "mmc3",
2355         .class          = &omap44xx_mmc_hwmod_class,
2356         .clkdm_name     = "l4_per_clkdm",
2357         .mpu_irqs       = omap44xx_mmc3_irqs,
2358         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2359         .main_clk       = "mmc3_fck",
2360         .prcm = {
2361                 .omap4 = {
2362                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2363                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2364                         .modulemode   = MODULEMODE_SWCTRL,
2365                 },
2366         },
2367 };
2368
2369 /* mmc4 */
2370 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2371         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2372         { .irq = -1 }
2373 };
2374
2375 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2376         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2377         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2378         { .dma_req = -1 }
2379 };
2380
2381 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2382         .name           = "mmc4",
2383         .class          = &omap44xx_mmc_hwmod_class,
2384         .clkdm_name     = "l4_per_clkdm",
2385         .mpu_irqs       = omap44xx_mmc4_irqs,
2386         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2387         .main_clk       = "mmc4_fck",
2388         .prcm = {
2389                 .omap4 = {
2390                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2391                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2392                         .modulemode   = MODULEMODE_SWCTRL,
2393                 },
2394         },
2395 };
2396
2397 /* mmc5 */
2398 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2399         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2400         { .irq = -1 }
2401 };
2402
2403 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2404         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2405         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2406         { .dma_req = -1 }
2407 };
2408
2409 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2410         .name           = "mmc5",
2411         .class          = &omap44xx_mmc_hwmod_class,
2412         .clkdm_name     = "l4_per_clkdm",
2413         .mpu_irqs       = omap44xx_mmc5_irqs,
2414         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2415         .main_clk       = "mmc5_fck",
2416         .prcm = {
2417                 .omap4 = {
2418                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2419                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2420                         .modulemode   = MODULEMODE_SWCTRL,
2421                 },
2422         },
2423 };
2424
2425 /*
2426  * 'mpu' class
2427  * mpu sub-system
2428  */
2429
2430 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2431         .name   = "mpu",
2432 };
2433
2434 /* mpu */
2435 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2436         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2437         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2438         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2439         { .irq = -1 }
2440 };
2441
2442 static struct omap_hwmod omap44xx_mpu_hwmod = {
2443         .name           = "mpu",
2444         .class          = &omap44xx_mpu_hwmod_class,
2445         .clkdm_name     = "mpuss_clkdm",
2446         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2447         .mpu_irqs       = omap44xx_mpu_irqs,
2448         .main_clk       = "dpll_mpu_m2_ck",
2449         .prcm = {
2450                 .omap4 = {
2451                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2452                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2453                 },
2454         },
2455 };
2456
2457 /*
2458  * 'ocmc_ram' class
2459  * top-level core on-chip ram
2460  */
2461
2462 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2463         .name   = "ocmc_ram",
2464 };
2465
2466 /* ocmc_ram */
2467 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2468         .name           = "ocmc_ram",
2469         .class          = &omap44xx_ocmc_ram_hwmod_class,
2470         .clkdm_name     = "l3_2_clkdm",
2471         .prcm = {
2472                 .omap4 = {
2473                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2474                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2475                 },
2476         },
2477 };
2478
2479 /*
2480  * 'ocp2scp' class
2481  * bridge to transform ocp interface protocol to scp (serial control port)
2482  * protocol
2483  */
2484
2485 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2486         .name   = "ocp2scp",
2487 };
2488
2489 /* ocp2scp_usb_phy */
2490 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2491         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2492 };
2493
2494 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2495         .name           = "ocp2scp_usb_phy",
2496         .class          = &omap44xx_ocp2scp_hwmod_class,
2497         .clkdm_name     = "l3_init_clkdm",
2498         .prcm = {
2499                 .omap4 = {
2500                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2501                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2502                         .modulemode   = MODULEMODE_HWCTRL,
2503                 },
2504         },
2505         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2506         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2507 };
2508
2509 /*
2510  * 'sl2if' class
2511  * shared level 2 memory interface
2512  */
2513
2514 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2515         .name   = "sl2if",
2516 };
2517
2518 /* sl2if */
2519 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2520         .name           = "sl2if",
2521         .class          = &omap44xx_sl2if_hwmod_class,
2522         .clkdm_name     = "ivahd_clkdm",
2523         .prcm = {
2524                 .omap4 = {
2525                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2526                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2527                         .modulemode   = MODULEMODE_HWCTRL,
2528                 },
2529         },
2530 };
2531
2532 /*
2533  * 'slimbus' class
2534  * bidirectional, multi-drop, multi-channel two-line serial interface between
2535  * the device and external components
2536  */
2537
2538 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2539         .rev_offs       = 0x0000,
2540         .sysc_offs      = 0x0010,
2541         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2542                            SYSC_HAS_SOFTRESET),
2543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2544                            SIDLE_SMART_WKUP),
2545         .sysc_fields    = &omap_hwmod_sysc_type2,
2546 };
2547
2548 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2549         .name   = "slimbus",
2550         .sysc   = &omap44xx_slimbus_sysc,
2551 };
2552
2553 /* slimbus1 */
2554 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2555         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2556         { .irq = -1 }
2557 };
2558
2559 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2560         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2561         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2562         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2563         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2564         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2565         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2566         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2567         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2568         { .dma_req = -1 }
2569 };
2570
2571 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2572         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2573         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2574         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2575         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2576 };
2577
2578 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2579         .name           = "slimbus1",
2580         .class          = &omap44xx_slimbus_hwmod_class,
2581         .clkdm_name     = "abe_clkdm",
2582         .mpu_irqs       = omap44xx_slimbus1_irqs,
2583         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2584         .prcm = {
2585                 .omap4 = {
2586                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2587                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2588                         .modulemode   = MODULEMODE_SWCTRL,
2589                 },
2590         },
2591         .opt_clks       = slimbus1_opt_clks,
2592         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2593 };
2594
2595 /* slimbus2 */
2596 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2597         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2598         { .irq = -1 }
2599 };
2600
2601 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2602         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2603         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2604         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2605         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2606         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2607         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2608         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2609         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2610         { .dma_req = -1 }
2611 };
2612
2613 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2614         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2615         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2616         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2617 };
2618
2619 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2620         .name           = "slimbus2",
2621         .class          = &omap44xx_slimbus_hwmod_class,
2622         .clkdm_name     = "l4_per_clkdm",
2623         .mpu_irqs       = omap44xx_slimbus2_irqs,
2624         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2625         .prcm = {
2626                 .omap4 = {
2627                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2628                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2629                         .modulemode   = MODULEMODE_SWCTRL,
2630                 },
2631         },
2632         .opt_clks       = slimbus2_opt_clks,
2633         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2634 };
2635
2636 /*
2637  * 'smartreflex' class
2638  * smartreflex module (monitor silicon performance and outputs a measure of
2639  * performance error)
2640  */
2641
2642 /* The IP is not compliant to type1 / type2 scheme */
2643 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2644         .sidle_shift    = 24,
2645         .enwkup_shift   = 26,
2646 };
2647
2648 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2649         .sysc_offs      = 0x0038,
2650         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2651         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2652                            SIDLE_SMART_WKUP),
2653         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2654 };
2655
2656 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2657         .name   = "smartreflex",
2658         .sysc   = &omap44xx_smartreflex_sysc,
2659         .rev    = 2,
2660 };
2661
2662 /* smartreflex_core */
2663 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2664         .sensor_voltdm_name   = "core",
2665 };
2666
2667 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2668         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2669         { .irq = -1 }
2670 };
2671
2672 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2673         .name           = "smartreflex_core",
2674         .class          = &omap44xx_smartreflex_hwmod_class,
2675         .clkdm_name     = "l4_ao_clkdm",
2676         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2677
2678         .main_clk       = "smartreflex_core_fck",
2679         .prcm = {
2680                 .omap4 = {
2681                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2682                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2683                         .modulemode   = MODULEMODE_SWCTRL,
2684                 },
2685         },
2686         .dev_attr       = &smartreflex_core_dev_attr,
2687 };
2688
2689 /* smartreflex_iva */
2690 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2691         .sensor_voltdm_name     = "iva",
2692 };
2693
2694 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2695         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2696         { .irq = -1 }
2697 };
2698
2699 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2700         .name           = "smartreflex_iva",
2701         .class          = &omap44xx_smartreflex_hwmod_class,
2702         .clkdm_name     = "l4_ao_clkdm",
2703         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2704         .main_clk       = "smartreflex_iva_fck",
2705         .prcm = {
2706                 .omap4 = {
2707                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2708                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2709                         .modulemode   = MODULEMODE_SWCTRL,
2710                 },
2711         },
2712         .dev_attr       = &smartreflex_iva_dev_attr,
2713 };
2714
2715 /* smartreflex_mpu */
2716 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2717         .sensor_voltdm_name     = "mpu",
2718 };
2719
2720 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2721         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2722         { .irq = -1 }
2723 };
2724
2725 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2726         .name           = "smartreflex_mpu",
2727         .class          = &omap44xx_smartreflex_hwmod_class,
2728         .clkdm_name     = "l4_ao_clkdm",
2729         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2730         .main_clk       = "smartreflex_mpu_fck",
2731         .prcm = {
2732                 .omap4 = {
2733                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2734                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2735                         .modulemode   = MODULEMODE_SWCTRL,
2736                 },
2737         },
2738         .dev_attr       = &smartreflex_mpu_dev_attr,
2739 };
2740
2741 /*
2742  * 'spinlock' class
2743  * spinlock provides hardware assistance for synchronizing the processes
2744  * running on multiple processors
2745  */
2746
2747 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2748         .rev_offs       = 0x0000,
2749         .sysc_offs      = 0x0010,
2750         .syss_offs      = 0x0014,
2751         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2752                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2753                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2755                            SIDLE_SMART_WKUP),
2756         .sysc_fields    = &omap_hwmod_sysc_type1,
2757 };
2758
2759 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2760         .name   = "spinlock",
2761         .sysc   = &omap44xx_spinlock_sysc,
2762 };
2763
2764 /* spinlock */
2765 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2766         .name           = "spinlock",
2767         .class          = &omap44xx_spinlock_hwmod_class,
2768         .clkdm_name     = "l4_cfg_clkdm",
2769         .prcm = {
2770                 .omap4 = {
2771                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2772                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2773                 },
2774         },
2775 };
2776
2777 /*
2778  * 'timer' class
2779  * general purpose timer module with accurate 1ms tick
2780  * This class contains several variants: ['timer_1ms', 'timer']
2781  */
2782
2783 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2784         .rev_offs       = 0x0000,
2785         .sysc_offs      = 0x0010,
2786         .syss_offs      = 0x0014,
2787         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2788                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2789                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2790                            SYSS_HAS_RESET_STATUS),
2791         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2792         .sysc_fields    = &omap_hwmod_sysc_type1,
2793 };
2794
2795 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2796         .name   = "timer",
2797         .sysc   = &omap44xx_timer_1ms_sysc,
2798 };
2799
2800 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2801         .rev_offs       = 0x0000,
2802         .sysc_offs      = 0x0010,
2803         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2804                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2805         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2806                            SIDLE_SMART_WKUP),
2807         .sysc_fields    = &omap_hwmod_sysc_type2,
2808 };
2809
2810 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2811         .name   = "timer",
2812         .sysc   = &omap44xx_timer_sysc,
2813 };
2814
2815 /* always-on timers dev attribute */
2816 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2817         .timer_capability       = OMAP_TIMER_ALWON,
2818 };
2819
2820 /* pwm timers dev attribute */
2821 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2822         .timer_capability       = OMAP_TIMER_HAS_PWM,
2823 };
2824
2825 /* timer1 */
2826 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2827         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2828         { .irq = -1 }
2829 };
2830
2831 static struct omap_hwmod omap44xx_timer1_hwmod = {
2832         .name           = "timer1",
2833         .class          = &omap44xx_timer_1ms_hwmod_class,
2834         .clkdm_name     = "l4_wkup_clkdm",
2835         .mpu_irqs       = omap44xx_timer1_irqs,
2836         .main_clk       = "timer1_fck",
2837         .prcm = {
2838                 .omap4 = {
2839                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2840                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2841                         .modulemode   = MODULEMODE_SWCTRL,
2842                 },
2843         },
2844         .dev_attr       = &capability_alwon_dev_attr,
2845 };
2846
2847 /* timer2 */
2848 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2849         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2850         { .irq = -1 }
2851 };
2852
2853 static struct omap_hwmod omap44xx_timer2_hwmod = {
2854         .name           = "timer2",
2855         .class          = &omap44xx_timer_1ms_hwmod_class,
2856         .clkdm_name     = "l4_per_clkdm",
2857         .mpu_irqs       = omap44xx_timer2_irqs,
2858         .main_clk       = "timer2_fck",
2859         .prcm = {
2860                 .omap4 = {
2861                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2862                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2863                         .modulemode   = MODULEMODE_SWCTRL,
2864                 },
2865         },
2866         .dev_attr       = &capability_alwon_dev_attr,
2867 };
2868
2869 /* timer3 */
2870 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2871         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2872         { .irq = -1 }
2873 };
2874
2875 static struct omap_hwmod omap44xx_timer3_hwmod = {
2876         .name           = "timer3",
2877         .class          = &omap44xx_timer_hwmod_class,
2878         .clkdm_name     = "l4_per_clkdm",
2879         .mpu_irqs       = omap44xx_timer3_irqs,
2880         .main_clk       = "timer3_fck",
2881         .prcm = {
2882                 .omap4 = {
2883                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2884                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2885                         .modulemode   = MODULEMODE_SWCTRL,
2886                 },
2887         },
2888         .dev_attr       = &capability_alwon_dev_attr,
2889 };
2890
2891 /* timer4 */
2892 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2893         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2894         { .irq = -1 }
2895 };
2896
2897 static struct omap_hwmod omap44xx_timer4_hwmod = {
2898         .name           = "timer4",
2899         .class          = &omap44xx_timer_hwmod_class,
2900         .clkdm_name     = "l4_per_clkdm",
2901         .mpu_irqs       = omap44xx_timer4_irqs,
2902         .main_clk       = "timer4_fck",
2903         .prcm = {
2904                 .omap4 = {
2905                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2906                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2907                         .modulemode   = MODULEMODE_SWCTRL,
2908                 },
2909         },
2910         .dev_attr       = &capability_alwon_dev_attr,
2911 };
2912
2913 /* timer5 */
2914 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2915         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2916         { .irq = -1 }
2917 };
2918
2919 static struct omap_hwmod omap44xx_timer5_hwmod = {
2920         .name           = "timer5",
2921         .class          = &omap44xx_timer_hwmod_class,
2922         .clkdm_name     = "abe_clkdm",
2923         .mpu_irqs       = omap44xx_timer5_irqs,
2924         .main_clk       = "timer5_fck",
2925         .prcm = {
2926                 .omap4 = {
2927                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2928                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2929                         .modulemode   = MODULEMODE_SWCTRL,
2930                 },
2931         },
2932         .dev_attr       = &capability_alwon_dev_attr,
2933 };
2934
2935 /* timer6 */
2936 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
2937         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
2938         { .irq = -1 }
2939 };
2940
2941 static struct omap_hwmod omap44xx_timer6_hwmod = {
2942         .name           = "timer6",
2943         .class          = &omap44xx_timer_hwmod_class,
2944         .clkdm_name     = "abe_clkdm",
2945         .mpu_irqs       = omap44xx_timer6_irqs,
2946
2947         .main_clk       = "timer6_fck",
2948         .prcm = {
2949                 .omap4 = {
2950                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2951                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2952                         .modulemode   = MODULEMODE_SWCTRL,
2953                 },
2954         },
2955         .dev_attr       = &capability_alwon_dev_attr,
2956 };
2957
2958 /* timer7 */
2959 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
2960         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
2961         { .irq = -1 }
2962 };
2963
2964 static struct omap_hwmod omap44xx_timer7_hwmod = {
2965         .name           = "timer7",
2966         .class          = &omap44xx_timer_hwmod_class,
2967         .clkdm_name     = "abe_clkdm",
2968         .mpu_irqs       = omap44xx_timer7_irqs,
2969         .main_clk       = "timer7_fck",
2970         .prcm = {
2971                 .omap4 = {
2972                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2973                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2974                         .modulemode   = MODULEMODE_SWCTRL,
2975                 },
2976         },
2977         .dev_attr       = &capability_alwon_dev_attr,
2978 };
2979
2980 /* timer8 */
2981 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
2982         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
2983         { .irq = -1 }
2984 };
2985
2986 static struct omap_hwmod omap44xx_timer8_hwmod = {
2987         .name           = "timer8",
2988         .class          = &omap44xx_timer_hwmod_class,
2989         .clkdm_name     = "abe_clkdm",
2990         .mpu_irqs       = omap44xx_timer8_irqs,
2991         .main_clk       = "timer8_fck",
2992         .prcm = {
2993                 .omap4 = {
2994                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2995                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2996                         .modulemode   = MODULEMODE_SWCTRL,
2997                 },
2998         },
2999         .dev_attr       = &capability_pwm_dev_attr,
3000 };
3001
3002 /* timer9 */
3003 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3004         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3005         { .irq = -1 }
3006 };
3007
3008 static struct omap_hwmod omap44xx_timer9_hwmod = {
3009         .name           = "timer9",
3010         .class          = &omap44xx_timer_hwmod_class,
3011         .clkdm_name     = "l4_per_clkdm",
3012         .mpu_irqs       = omap44xx_timer9_irqs,
3013         .main_clk       = "timer9_fck",
3014         .prcm = {
3015                 .omap4 = {
3016                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3017                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3018                         .modulemode   = MODULEMODE_SWCTRL,
3019                 },
3020         },
3021         .dev_attr       = &capability_pwm_dev_attr,
3022 };
3023
3024 /* timer10 */
3025 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3026         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3027         { .irq = -1 }
3028 };
3029
3030 static struct omap_hwmod omap44xx_timer10_hwmod = {
3031         .name           = "timer10",
3032         .class          = &omap44xx_timer_1ms_hwmod_class,
3033         .clkdm_name     = "l4_per_clkdm",
3034         .mpu_irqs       = omap44xx_timer10_irqs,
3035         .main_clk       = "timer10_fck",
3036         .prcm = {
3037                 .omap4 = {
3038                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3039                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3040                         .modulemode   = MODULEMODE_SWCTRL,
3041                 },
3042         },
3043         .dev_attr       = &capability_pwm_dev_attr,
3044 };
3045
3046 /* timer11 */
3047 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3048         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3049         { .irq = -1 }
3050 };
3051
3052 static struct omap_hwmod omap44xx_timer11_hwmod = {
3053         .name           = "timer11",
3054         .class          = &omap44xx_timer_hwmod_class,
3055         .clkdm_name     = "l4_per_clkdm",
3056         .mpu_irqs       = omap44xx_timer11_irqs,
3057         .main_clk       = "timer11_fck",
3058         .prcm = {
3059                 .omap4 = {
3060                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3061                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3062                         .modulemode   = MODULEMODE_SWCTRL,
3063                 },
3064         },
3065         .dev_attr       = &capability_pwm_dev_attr,
3066 };
3067
3068 /*
3069  * 'uart' class
3070  * universal asynchronous receiver/transmitter (uart)
3071  */
3072
3073 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3074         .rev_offs       = 0x0050,
3075         .sysc_offs      = 0x0054,
3076         .syss_offs      = 0x0058,
3077         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3078                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3079                            SYSS_HAS_RESET_STATUS),
3080         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3081                            SIDLE_SMART_WKUP),
3082         .sysc_fields    = &omap_hwmod_sysc_type1,
3083 };
3084
3085 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3086         .name   = "uart",
3087         .sysc   = &omap44xx_uart_sysc,
3088 };
3089
3090 /* uart1 */
3091 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3092         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3093         { .irq = -1 }
3094 };
3095
3096 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3097         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3098         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3099         { .dma_req = -1 }
3100 };
3101
3102 static struct omap_hwmod omap44xx_uart1_hwmod = {
3103         .name           = "uart1",
3104         .class          = &omap44xx_uart_hwmod_class,
3105         .clkdm_name     = "l4_per_clkdm",
3106         .mpu_irqs       = omap44xx_uart1_irqs,
3107         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3108         .main_clk       = "uart1_fck",
3109         .prcm = {
3110                 .omap4 = {
3111                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3112                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3113                         .modulemode   = MODULEMODE_SWCTRL,
3114                 },
3115         },
3116 };
3117
3118 /* uart2 */
3119 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3120         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3121         { .irq = -1 }
3122 };
3123
3124 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3125         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3126         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3127         { .dma_req = -1 }
3128 };
3129
3130 static struct omap_hwmod omap44xx_uart2_hwmod = {
3131         .name           = "uart2",
3132         .class          = &omap44xx_uart_hwmod_class,
3133         .clkdm_name     = "l4_per_clkdm",
3134         .mpu_irqs       = omap44xx_uart2_irqs,
3135         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3136         .main_clk       = "uart2_fck",
3137         .prcm = {
3138                 .omap4 = {
3139                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3140                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3141                         .modulemode   = MODULEMODE_SWCTRL,
3142                 },
3143         },
3144 };
3145
3146 /* uart3 */
3147 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3148         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3149         { .irq = -1 }
3150 };
3151
3152 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3153         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3154         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3155         { .dma_req = -1 }
3156 };
3157
3158 static struct omap_hwmod omap44xx_uart3_hwmod = {
3159         .name           = "uart3",
3160         .class          = &omap44xx_uart_hwmod_class,
3161         .clkdm_name     = "l4_per_clkdm",
3162         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3163         .mpu_irqs       = omap44xx_uart3_irqs,
3164         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3165         .main_clk       = "uart3_fck",
3166         .prcm = {
3167                 .omap4 = {
3168                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3169                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3170                         .modulemode   = MODULEMODE_SWCTRL,
3171                 },
3172         },
3173 };
3174
3175 /* uart4 */
3176 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3177         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3178         { .irq = -1 }
3179 };
3180
3181 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3182         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3183         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3184         { .dma_req = -1 }
3185 };
3186
3187 static struct omap_hwmod omap44xx_uart4_hwmod = {
3188         .name           = "uart4",
3189         .class          = &omap44xx_uart_hwmod_class,
3190         .clkdm_name     = "l4_per_clkdm",
3191         .mpu_irqs       = omap44xx_uart4_irqs,
3192         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3193         .main_clk       = "uart4_fck",
3194         .prcm = {
3195                 .omap4 = {
3196                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3197                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3198                         .modulemode   = MODULEMODE_SWCTRL,
3199                 },
3200         },
3201 };
3202
3203 /*
3204  * 'usb_host_fs' class
3205  * full-speed usb host controller
3206  */
3207
3208 /* The IP is not compliant to type1 / type2 scheme */
3209 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3210         .midle_shift    = 4,
3211         .sidle_shift    = 2,
3212         .srst_shift     = 1,
3213 };
3214
3215 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3216         .rev_offs       = 0x0000,
3217         .sysc_offs      = 0x0210,
3218         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3219                            SYSC_HAS_SOFTRESET),
3220         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3221                            SIDLE_SMART_WKUP),
3222         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3223 };
3224
3225 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3226         .name   = "usb_host_fs",
3227         .sysc   = &omap44xx_usb_host_fs_sysc,
3228 };
3229
3230 /* usb_host_fs */
3231 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3232         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3233         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3234         { .irq = -1 }
3235 };
3236
3237 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3238         .name           = "usb_host_fs",
3239         .class          = &omap44xx_usb_host_fs_hwmod_class,
3240         .clkdm_name     = "l3_init_clkdm",
3241         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3242         .main_clk       = "usb_host_fs_fck",
3243         .prcm = {
3244                 .omap4 = {
3245                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3246                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3247                         .modulemode   = MODULEMODE_SWCTRL,
3248                 },
3249         },
3250 };
3251
3252 /*
3253  * 'usb_host_hs' class
3254  * high-speed multi-port usb host controller
3255  */
3256
3257 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3258         .rev_offs       = 0x0000,
3259         .sysc_offs      = 0x0010,
3260         .syss_offs      = 0x0014,
3261         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3262                            SYSC_HAS_SOFTRESET),
3263         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3264                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3265                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3266         .sysc_fields    = &omap_hwmod_sysc_type2,
3267 };
3268
3269 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3270         .name   = "usb_host_hs",
3271         .sysc   = &omap44xx_usb_host_hs_sysc,
3272 };
3273
3274 /* usb_host_hs */
3275 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3276         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3277         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3278         { .irq = -1 }
3279 };
3280
3281 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3282         .name           = "usb_host_hs",
3283         .class          = &omap44xx_usb_host_hs_hwmod_class,
3284         .clkdm_name     = "l3_init_clkdm",
3285         .main_clk       = "usb_host_hs_fck",
3286         .prcm = {
3287                 .omap4 = {
3288                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3289                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3290                         .modulemode   = MODULEMODE_SWCTRL,
3291                 },
3292         },
3293         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3294
3295         /*
3296          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3297          * id: i660
3298          *
3299          * Description:
3300          * In the following configuration :
3301          * - USBHOST module is set to smart-idle mode
3302          * - PRCM asserts idle_req to the USBHOST module ( This typically
3303          *   happens when the system is going to a low power mode : all ports
3304          *   have been suspended, the master part of the USBHOST module has
3305          *   entered the standby state, and SW has cut the functional clocks)
3306          * - an USBHOST interrupt occurs before the module is able to answer
3307          *   idle_ack, typically a remote wakeup IRQ.
3308          * Then the USB HOST module will enter a deadlock situation where it
3309          * is no more accessible nor functional.
3310          *
3311          * Workaround:
3312          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3313          */
3314
3315         /*
3316          * Errata: USB host EHCI may stall when entering smart-standby mode
3317          * Id: i571
3318          *
3319          * Description:
3320          * When the USBHOST module is set to smart-standby mode, and when it is
3321          * ready to enter the standby state (i.e. all ports are suspended and
3322          * all attached devices are in suspend mode), then it can wrongly assert
3323          * the Mstandby signal too early while there are still some residual OCP
3324          * transactions ongoing. If this condition occurs, the internal state
3325          * machine may go to an undefined state and the USB link may be stuck
3326          * upon the next resume.
3327          *
3328          * Workaround:
3329          * Don't use smart standby; use only force standby,
3330          * hence HWMOD_SWSUP_MSTANDBY
3331          */
3332
3333         /*
3334          * During system boot; If the hwmod framework resets the module
3335          * the module will have smart idle settings; which can lead to deadlock
3336          * (above Errata Id:i660); so, dont reset the module during boot;
3337          * Use HWMOD_INIT_NO_RESET.
3338          */
3339
3340         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3341                           HWMOD_INIT_NO_RESET,
3342 };
3343
3344 /*
3345  * 'usb_otg_hs' class
3346  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3347  */
3348
3349 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3350         .rev_offs       = 0x0400,
3351         .sysc_offs      = 0x0404,
3352         .syss_offs      = 0x0408,
3353         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3354                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3355                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3356         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3357                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3358                            MSTANDBY_SMART),
3359         .sysc_fields    = &omap_hwmod_sysc_type1,
3360 };
3361
3362 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3363         .name   = "usb_otg_hs",
3364         .sysc   = &omap44xx_usb_otg_hs_sysc,
3365 };
3366
3367 /* usb_otg_hs */
3368 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3369         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3370         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3371         { .irq = -1 }
3372 };
3373
3374 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3375         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3376 };
3377
3378 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3379         .name           = "usb_otg_hs",
3380         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3381         .clkdm_name     = "l3_init_clkdm",
3382         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3383         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3384         .main_clk       = "usb_otg_hs_ick",
3385         .prcm = {
3386                 .omap4 = {
3387                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3388                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3389                         .modulemode   = MODULEMODE_HWCTRL,
3390                 },
3391         },
3392         .opt_clks       = usb_otg_hs_opt_clks,
3393         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3394 };
3395
3396 /*
3397  * 'usb_tll_hs' class
3398  * usb_tll_hs module is the adapter on the usb_host_hs ports
3399  */
3400
3401 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3402         .rev_offs       = 0x0000,
3403         .sysc_offs      = 0x0010,
3404         .syss_offs      = 0x0014,
3405         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3406                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3407                            SYSC_HAS_AUTOIDLE),
3408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3409         .sysc_fields    = &omap_hwmod_sysc_type1,
3410 };
3411
3412 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3413         .name   = "usb_tll_hs",
3414         .sysc   = &omap44xx_usb_tll_hs_sysc,
3415 };
3416
3417 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3418         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3419         { .irq = -1 }
3420 };
3421
3422 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3423         .name           = "usb_tll_hs",
3424         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3425         .clkdm_name     = "l3_init_clkdm",
3426         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3427         .main_clk       = "usb_tll_hs_ick",
3428         .prcm = {
3429                 .omap4 = {
3430                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3431                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3432                         .modulemode   = MODULEMODE_HWCTRL,
3433                 },
3434         },
3435 };
3436
3437 /*
3438  * 'wd_timer' class
3439  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3440  * overflow condition
3441  */
3442
3443 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3444         .rev_offs       = 0x0000,
3445         .sysc_offs      = 0x0010,
3446         .syss_offs      = 0x0014,
3447         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3448                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3449         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3450                            SIDLE_SMART_WKUP),
3451         .sysc_fields    = &omap_hwmod_sysc_type1,
3452 };
3453
3454 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3455         .name           = "wd_timer",
3456         .sysc           = &omap44xx_wd_timer_sysc,
3457         .pre_shutdown   = &omap2_wd_timer_disable,
3458 };
3459
3460 /* wd_timer2 */
3461 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3462         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3463         { .irq = -1 }
3464 };
3465
3466 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3467         .name           = "wd_timer2",
3468         .class          = &omap44xx_wd_timer_hwmod_class,
3469         .clkdm_name     = "l4_wkup_clkdm",
3470         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3471         .main_clk       = "wd_timer2_fck",
3472         .prcm = {
3473                 .omap4 = {
3474                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3475                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3476                         .modulemode   = MODULEMODE_SWCTRL,
3477                 },
3478         },
3479 };
3480
3481 /* wd_timer3 */
3482 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3483         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3484         { .irq = -1 }
3485 };
3486
3487 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3488         .name           = "wd_timer3",
3489         .class          = &omap44xx_wd_timer_hwmod_class,
3490         .clkdm_name     = "abe_clkdm",
3491         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3492         .main_clk       = "wd_timer3_fck",
3493         .prcm = {
3494                 .omap4 = {
3495                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3496                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3497                         .modulemode   = MODULEMODE_SWCTRL,
3498                 },
3499         },
3500 };
3501
3502
3503 /*
3504  * interfaces
3505  */
3506
3507 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3508         {
3509                 .pa_start       = 0x4a204000,
3510                 .pa_end         = 0x4a2040ff,
3511                 .flags          = ADDR_TYPE_RT
3512         },
3513         { }
3514 };
3515
3516 /* c2c -> c2c_target_fw */
3517 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3518         .master         = &omap44xx_c2c_hwmod,
3519         .slave          = &omap44xx_c2c_target_fw_hwmod,
3520         .clk            = "div_core_ck",
3521         .addr           = omap44xx_c2c_target_fw_addrs,
3522         .user           = OCP_USER_MPU,
3523 };
3524
3525 /* l4_cfg -> c2c_target_fw */
3526 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3527         .master         = &omap44xx_l4_cfg_hwmod,
3528         .slave          = &omap44xx_c2c_target_fw_hwmod,
3529         .clk            = "l4_div_ck",
3530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3532
3533 /* l3_main_1 -> dmm */
3534 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3535         .master         = &omap44xx_l3_main_1_hwmod,
3536         .slave          = &omap44xx_dmm_hwmod,
3537         .clk            = "l3_div_ck",
3538         .user           = OCP_USER_SDMA,
3539 };
3540
3541 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3542         {
3543                 .pa_start       = 0x4e000000,
3544                 .pa_end         = 0x4e0007ff,
3545                 .flags          = ADDR_TYPE_RT
3546         },
3547         { }
3548 };
3549
3550 /* mpu -> dmm */
3551 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3552         .master         = &omap44xx_mpu_hwmod,
3553         .slave          = &omap44xx_dmm_hwmod,
3554         .clk            = "l3_div_ck",
3555         .addr           = omap44xx_dmm_addrs,
3556         .user           = OCP_USER_MPU,
3557 };
3558
3559 /* c2c -> emif_fw */
3560 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3561         .master         = &omap44xx_c2c_hwmod,
3562         .slave          = &omap44xx_emif_fw_hwmod,
3563         .clk            = "div_core_ck",
3564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3565 };
3566
3567 /* dmm -> emif_fw */
3568 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3569         .master         = &omap44xx_dmm_hwmod,
3570         .slave          = &omap44xx_emif_fw_hwmod,
3571         .clk            = "l3_div_ck",
3572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3573 };
3574
3575 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3576         {
3577                 .pa_start       = 0x4a20c000,
3578                 .pa_end         = 0x4a20c0ff,
3579                 .flags          = ADDR_TYPE_RT
3580         },
3581         { }
3582 };
3583
3584 /* l4_cfg -> emif_fw */
3585 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3586         .master         = &omap44xx_l4_cfg_hwmod,
3587         .slave          = &omap44xx_emif_fw_hwmod,
3588         .clk            = "l4_div_ck",
3589         .addr           = omap44xx_emif_fw_addrs,
3590         .user           = OCP_USER_MPU,
3591 };
3592
3593 /* iva -> l3_instr */
3594 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3595         .master         = &omap44xx_iva_hwmod,
3596         .slave          = &omap44xx_l3_instr_hwmod,
3597         .clk            = "l3_div_ck",
3598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3599 };
3600
3601 /* l3_main_3 -> l3_instr */
3602 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3603         .master         = &omap44xx_l3_main_3_hwmod,
3604         .slave          = &omap44xx_l3_instr_hwmod,
3605         .clk            = "l3_div_ck",
3606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3607 };
3608
3609 /* ocp_wp_noc -> l3_instr */
3610 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3611         .master         = &omap44xx_ocp_wp_noc_hwmod,
3612         .slave          = &omap44xx_l3_instr_hwmod,
3613         .clk            = "l3_div_ck",
3614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3615 };
3616
3617 /* dsp -> l3_main_1 */
3618 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3619         .master         = &omap44xx_dsp_hwmod,
3620         .slave          = &omap44xx_l3_main_1_hwmod,
3621         .clk            = "l3_div_ck",
3622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3623 };
3624
3625 /* dss -> l3_main_1 */
3626 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3627         .master         = &omap44xx_dss_hwmod,
3628         .slave          = &omap44xx_l3_main_1_hwmod,
3629         .clk            = "l3_div_ck",
3630         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3631 };
3632
3633 /* l3_main_2 -> l3_main_1 */
3634 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3635         .master         = &omap44xx_l3_main_2_hwmod,
3636         .slave          = &omap44xx_l3_main_1_hwmod,
3637         .clk            = "l3_div_ck",
3638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3640
3641 /* l4_cfg -> l3_main_1 */
3642 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3643         .master         = &omap44xx_l4_cfg_hwmod,
3644         .slave          = &omap44xx_l3_main_1_hwmod,
3645         .clk            = "l4_div_ck",
3646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3647 };
3648
3649 /* mmc1 -> l3_main_1 */
3650 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3651         .master         = &omap44xx_mmc1_hwmod,
3652         .slave          = &omap44xx_l3_main_1_hwmod,
3653         .clk            = "l3_div_ck",
3654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3656
3657 /* mmc2 -> l3_main_1 */
3658 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3659         .master         = &omap44xx_mmc2_hwmod,
3660         .slave          = &omap44xx_l3_main_1_hwmod,
3661         .clk            = "l3_div_ck",
3662         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3663 };
3664
3665 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3666         {
3667                 .pa_start       = 0x44000000,
3668                 .pa_end         = 0x44000fff,
3669                 .flags          = ADDR_TYPE_RT
3670         },
3671         { }
3672 };
3673
3674 /* mpu -> l3_main_1 */
3675 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3676         .master         = &omap44xx_mpu_hwmod,
3677         .slave          = &omap44xx_l3_main_1_hwmod,
3678         .clk            = "l3_div_ck",
3679         .addr           = omap44xx_l3_main_1_addrs,
3680         .user           = OCP_USER_MPU,
3681 };
3682
3683 /* c2c_target_fw -> l3_main_2 */
3684 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3685         .master         = &omap44xx_c2c_target_fw_hwmod,
3686         .slave          = &omap44xx_l3_main_2_hwmod,
3687         .clk            = "l3_div_ck",
3688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* dma_system -> l3_main_2 */
3692 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3693         .master         = &omap44xx_dma_system_hwmod,
3694         .slave          = &omap44xx_l3_main_2_hwmod,
3695         .clk            = "l3_div_ck",
3696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3697 };
3698
3699 /* fdif -> l3_main_2 */
3700 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3701         .master         = &omap44xx_fdif_hwmod,
3702         .slave          = &omap44xx_l3_main_2_hwmod,
3703         .clk            = "l3_div_ck",
3704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3705 };
3706
3707 /* gpu -> l3_main_2 */
3708 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3709         .master         = &omap44xx_gpu_hwmod,
3710         .slave          = &omap44xx_l3_main_2_hwmod,
3711         .clk            = "l3_div_ck",
3712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3713 };
3714
3715 /* hsi -> l3_main_2 */
3716 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3717         .master         = &omap44xx_hsi_hwmod,
3718         .slave          = &omap44xx_l3_main_2_hwmod,
3719         .clk            = "l3_div_ck",
3720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3721 };
3722
3723 /* ipu -> l3_main_2 */
3724 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3725         .master         = &omap44xx_ipu_hwmod,
3726         .slave          = &omap44xx_l3_main_2_hwmod,
3727         .clk            = "l3_div_ck",
3728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3729 };
3730
3731 /* iss -> l3_main_2 */
3732 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3733         .master         = &omap44xx_iss_hwmod,
3734         .slave          = &omap44xx_l3_main_2_hwmod,
3735         .clk            = "l3_div_ck",
3736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3737 };
3738
3739 /* iva -> l3_main_2 */
3740 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3741         .master         = &omap44xx_iva_hwmod,
3742         .slave          = &omap44xx_l3_main_2_hwmod,
3743         .clk            = "l3_div_ck",
3744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3746
3747 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3748         {
3749                 .pa_start       = 0x44800000,
3750                 .pa_end         = 0x44801fff,
3751                 .flags          = ADDR_TYPE_RT
3752         },
3753         { }
3754 };
3755
3756 /* l3_main_1 -> l3_main_2 */
3757 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3758         .master         = &omap44xx_l3_main_1_hwmod,
3759         .slave          = &omap44xx_l3_main_2_hwmod,
3760         .clk            = "l3_div_ck",
3761         .addr           = omap44xx_l3_main_2_addrs,
3762         .user           = OCP_USER_MPU,
3763 };
3764
3765 /* l4_cfg -> l3_main_2 */
3766 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3767         .master         = &omap44xx_l4_cfg_hwmod,
3768         .slave          = &omap44xx_l3_main_2_hwmod,
3769         .clk            = "l4_div_ck",
3770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3772
3773 /* usb_host_fs -> l3_main_2 */
3774 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3775         .master         = &omap44xx_usb_host_fs_hwmod,
3776         .slave          = &omap44xx_l3_main_2_hwmod,
3777         .clk            = "l3_div_ck",
3778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3780
3781 /* usb_host_hs -> l3_main_2 */
3782 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3783         .master         = &omap44xx_usb_host_hs_hwmod,
3784         .slave          = &omap44xx_l3_main_2_hwmod,
3785         .clk            = "l3_div_ck",
3786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3788
3789 /* usb_otg_hs -> l3_main_2 */
3790 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3791         .master         = &omap44xx_usb_otg_hs_hwmod,
3792         .slave          = &omap44xx_l3_main_2_hwmod,
3793         .clk            = "l3_div_ck",
3794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3796
3797 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3798         {
3799                 .pa_start       = 0x45000000,
3800                 .pa_end         = 0x45000fff,
3801                 .flags          = ADDR_TYPE_RT
3802         },
3803         { }
3804 };
3805
3806 /* l3_main_1 -> l3_main_3 */
3807 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3808         .master         = &omap44xx_l3_main_1_hwmod,
3809         .slave          = &omap44xx_l3_main_3_hwmod,
3810         .clk            = "l3_div_ck",
3811         .addr           = omap44xx_l3_main_3_addrs,
3812         .user           = OCP_USER_MPU,
3813 };
3814
3815 /* l3_main_2 -> l3_main_3 */
3816 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3817         .master         = &omap44xx_l3_main_2_hwmod,
3818         .slave          = &omap44xx_l3_main_3_hwmod,
3819         .clk            = "l3_div_ck",
3820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3821 };
3822
3823 /* l4_cfg -> l3_main_3 */
3824 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3825         .master         = &omap44xx_l4_cfg_hwmod,
3826         .slave          = &omap44xx_l3_main_3_hwmod,
3827         .clk            = "l4_div_ck",
3828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3829 };
3830
3831 /* aess -> l4_abe */
3832 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3833         .master         = &omap44xx_aess_hwmod,
3834         .slave          = &omap44xx_l4_abe_hwmod,
3835         .clk            = "ocp_abe_iclk",
3836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3837 };
3838
3839 /* dsp -> l4_abe */
3840 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3841         .master         = &omap44xx_dsp_hwmod,
3842         .slave          = &omap44xx_l4_abe_hwmod,
3843         .clk            = "ocp_abe_iclk",
3844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3845 };
3846
3847 /* l3_main_1 -> l4_abe */
3848 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3849         .master         = &omap44xx_l3_main_1_hwmod,
3850         .slave          = &omap44xx_l4_abe_hwmod,
3851         .clk            = "l3_div_ck",
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* mpu -> l4_abe */
3856 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3857         .master         = &omap44xx_mpu_hwmod,
3858         .slave          = &omap44xx_l4_abe_hwmod,
3859         .clk            = "ocp_abe_iclk",
3860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3861 };
3862
3863 /* l3_main_1 -> l4_cfg */
3864 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3865         .master         = &omap44xx_l3_main_1_hwmod,
3866         .slave          = &omap44xx_l4_cfg_hwmod,
3867         .clk            = "l3_div_ck",
3868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3870
3871 /* l3_main_2 -> l4_per */
3872 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3873         .master         = &omap44xx_l3_main_2_hwmod,
3874         .slave          = &omap44xx_l4_per_hwmod,
3875         .clk            = "l3_div_ck",
3876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3877 };
3878
3879 /* l4_cfg -> l4_wkup */
3880 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3881         .master         = &omap44xx_l4_cfg_hwmod,
3882         .slave          = &omap44xx_l4_wkup_hwmod,
3883         .clk            = "l4_div_ck",
3884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3885 };
3886
3887 /* mpu -> mpu_private */
3888 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3889         .master         = &omap44xx_mpu_hwmod,
3890         .slave          = &omap44xx_mpu_private_hwmod,
3891         .clk            = "l3_div_ck",
3892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3893 };
3894
3895 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3896         {
3897                 .pa_start       = 0x4a102000,
3898                 .pa_end         = 0x4a10207f,
3899                 .flags          = ADDR_TYPE_RT
3900         },
3901         { }
3902 };
3903
3904 /* l4_cfg -> ocp_wp_noc */
3905 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3906         .master         = &omap44xx_l4_cfg_hwmod,
3907         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3908         .clk            = "l4_div_ck",
3909         .addr           = omap44xx_ocp_wp_noc_addrs,
3910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3911 };
3912
3913 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3914         {
3915                 .pa_start       = 0x401f1000,
3916                 .pa_end         = 0x401f13ff,
3917                 .flags          = ADDR_TYPE_RT
3918         },
3919         { }
3920 };
3921
3922 /* l4_abe -> aess */
3923 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
3924         .master         = &omap44xx_l4_abe_hwmod,
3925         .slave          = &omap44xx_aess_hwmod,
3926         .clk            = "ocp_abe_iclk",
3927         .addr           = omap44xx_aess_addrs,
3928         .user           = OCP_USER_MPU,
3929 };
3930
3931 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3932         {
3933                 .pa_start       = 0x490f1000,
3934                 .pa_end         = 0x490f13ff,
3935                 .flags          = ADDR_TYPE_RT
3936         },
3937         { }
3938 };
3939
3940 /* l4_abe -> aess (dma) */
3941 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
3942         .master         = &omap44xx_l4_abe_hwmod,
3943         .slave          = &omap44xx_aess_hwmod,
3944         .clk            = "ocp_abe_iclk",
3945         .addr           = omap44xx_aess_dma_addrs,
3946         .user           = OCP_USER_SDMA,
3947 };
3948
3949 /* l3_main_2 -> c2c */
3950 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3951         .master         = &omap44xx_l3_main_2_hwmod,
3952         .slave          = &omap44xx_c2c_hwmod,
3953         .clk            = "l3_div_ck",
3954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3955 };
3956
3957 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
3958         {
3959                 .pa_start       = 0x4a304000,
3960                 .pa_end         = 0x4a30401f,
3961                 .flags          = ADDR_TYPE_RT
3962         },
3963         { }
3964 };
3965
3966 /* l4_wkup -> counter_32k */
3967 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3968         .master         = &omap44xx_l4_wkup_hwmod,
3969         .slave          = &omap44xx_counter_32k_hwmod,
3970         .clk            = "l4_wkup_clk_mux_ck",
3971         .addr           = omap44xx_counter_32k_addrs,
3972         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3973 };
3974
3975 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3976         {
3977                 .pa_start       = 0x4a002000,
3978                 .pa_end         = 0x4a0027ff,
3979                 .flags          = ADDR_TYPE_RT
3980         },
3981         { }
3982 };
3983
3984 /* l4_cfg -> ctrl_module_core */
3985 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3986         .master         = &omap44xx_l4_cfg_hwmod,
3987         .slave          = &omap44xx_ctrl_module_core_hwmod,
3988         .clk            = "l4_div_ck",
3989         .addr           = omap44xx_ctrl_module_core_addrs,
3990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3991 };
3992
3993 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3994         {
3995                 .pa_start       = 0x4a100000,
3996                 .pa_end         = 0x4a1007ff,
3997                 .flags          = ADDR_TYPE_RT
3998         },
3999         { }
4000 };
4001
4002 /* l4_cfg -> ctrl_module_pad_core */
4003 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4004         .master         = &omap44xx_l4_cfg_hwmod,
4005         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4006         .clk            = "l4_div_ck",
4007         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4009 };
4010
4011 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4012         {
4013                 .pa_start       = 0x4a30c000,
4014                 .pa_end         = 0x4a30c7ff,
4015                 .flags          = ADDR_TYPE_RT
4016         },
4017         { }
4018 };
4019
4020 /* l4_wkup -> ctrl_module_wkup */
4021 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4022         .master         = &omap44xx_l4_wkup_hwmod,
4023         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4024         .clk            = "l4_wkup_clk_mux_ck",
4025         .addr           = omap44xx_ctrl_module_wkup_addrs,
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4030         {
4031                 .pa_start       = 0x4a31e000,
4032                 .pa_end         = 0x4a31e7ff,
4033                 .flags          = ADDR_TYPE_RT
4034         },
4035         { }
4036 };
4037
4038 /* l4_wkup -> ctrl_module_pad_wkup */
4039 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4040         .master         = &omap44xx_l4_wkup_hwmod,
4041         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4042         .clk            = "l4_wkup_clk_mux_ck",
4043         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4048         {
4049                 .pa_start       = 0x4a056000,
4050                 .pa_end         = 0x4a056fff,
4051                 .flags          = ADDR_TYPE_RT
4052         },
4053         { }
4054 };
4055
4056 /* l4_cfg -> dma_system */
4057 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4058         .master         = &omap44xx_l4_cfg_hwmod,
4059         .slave          = &omap44xx_dma_system_hwmod,
4060         .clk            = "l4_div_ck",
4061         .addr           = omap44xx_dma_system_addrs,
4062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4063 };
4064
4065 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4066         {
4067                 .name           = "mpu",
4068                 .pa_start       = 0x4012e000,
4069                 .pa_end         = 0x4012e07f,
4070                 .flags          = ADDR_TYPE_RT
4071         },
4072         { }
4073 };
4074
4075 /* l4_abe -> dmic */
4076 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4077         .master         = &omap44xx_l4_abe_hwmod,
4078         .slave          = &omap44xx_dmic_hwmod,
4079         .clk            = "ocp_abe_iclk",
4080         .addr           = omap44xx_dmic_addrs,
4081         .user           = OCP_USER_MPU,
4082 };
4083
4084 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4085         {
4086                 .name           = "dma",
4087                 .pa_start       = 0x4902e000,
4088                 .pa_end         = 0x4902e07f,
4089                 .flags          = ADDR_TYPE_RT
4090         },
4091         { }
4092 };
4093
4094 /* l4_abe -> dmic (dma) */
4095 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4096         .master         = &omap44xx_l4_abe_hwmod,
4097         .slave          = &omap44xx_dmic_hwmod,
4098         .clk            = "ocp_abe_iclk",
4099         .addr           = omap44xx_dmic_dma_addrs,
4100         .user           = OCP_USER_SDMA,
4101 };
4102
4103 /* dsp -> iva */
4104 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4105         .master         = &omap44xx_dsp_hwmod,
4106         .slave          = &omap44xx_iva_hwmod,
4107         .clk            = "dpll_iva_m5x2_ck",
4108         .user           = OCP_USER_DSP,
4109 };
4110
4111 /* dsp -> sl2if */
4112 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4113         .master         = &omap44xx_dsp_hwmod,
4114         .slave          = &omap44xx_sl2if_hwmod,
4115         .clk            = "dpll_iva_m5x2_ck",
4116         .user           = OCP_USER_DSP,
4117 };
4118
4119 /* l4_cfg -> dsp */
4120 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4121         .master         = &omap44xx_l4_cfg_hwmod,
4122         .slave          = &omap44xx_dsp_hwmod,
4123         .clk            = "l4_div_ck",
4124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4125 };
4126
4127 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4128         {
4129                 .pa_start       = 0x58000000,
4130                 .pa_end         = 0x5800007f,
4131                 .flags          = ADDR_TYPE_RT
4132         },
4133         { }
4134 };
4135
4136 /* l3_main_2 -> dss */
4137 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4138         .master         = &omap44xx_l3_main_2_hwmod,
4139         .slave          = &omap44xx_dss_hwmod,
4140         .clk            = "dss_fck",
4141         .addr           = omap44xx_dss_dma_addrs,
4142         .user           = OCP_USER_SDMA,
4143 };
4144
4145 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4146         {
4147                 .pa_start       = 0x48040000,
4148                 .pa_end         = 0x4804007f,
4149                 .flags          = ADDR_TYPE_RT
4150         },
4151         { }
4152 };
4153
4154 /* l4_per -> dss */
4155 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4156         .master         = &omap44xx_l4_per_hwmod,
4157         .slave          = &omap44xx_dss_hwmod,
4158         .clk            = "l4_div_ck",
4159         .addr           = omap44xx_dss_addrs,
4160         .user           = OCP_USER_MPU,
4161 };
4162
4163 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4164         {
4165                 .pa_start       = 0x58001000,
4166                 .pa_end         = 0x58001fff,
4167                 .flags          = ADDR_TYPE_RT
4168         },
4169         { }
4170 };
4171
4172 /* l3_main_2 -> dss_dispc */
4173 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4174         .master         = &omap44xx_l3_main_2_hwmod,
4175         .slave          = &omap44xx_dss_dispc_hwmod,
4176         .clk            = "dss_fck",
4177         .addr           = omap44xx_dss_dispc_dma_addrs,
4178         .user           = OCP_USER_SDMA,
4179 };
4180
4181 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4182         {
4183                 .pa_start       = 0x48041000,
4184                 .pa_end         = 0x48041fff,
4185                 .flags          = ADDR_TYPE_RT
4186         },
4187         { }
4188 };
4189
4190 /* l4_per -> dss_dispc */
4191 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4192         .master         = &omap44xx_l4_per_hwmod,
4193         .slave          = &omap44xx_dss_dispc_hwmod,
4194         .clk            = "l4_div_ck",
4195         .addr           = omap44xx_dss_dispc_addrs,
4196         .user           = OCP_USER_MPU,
4197 };
4198
4199 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4200         {
4201                 .pa_start       = 0x58004000,
4202                 .pa_end         = 0x580041ff,
4203                 .flags          = ADDR_TYPE_RT
4204         },
4205         { }
4206 };
4207
4208 /* l3_main_2 -> dss_dsi1 */
4209 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4210         .master         = &omap44xx_l3_main_2_hwmod,
4211         .slave          = &omap44xx_dss_dsi1_hwmod,
4212         .clk            = "dss_fck",
4213         .addr           = omap44xx_dss_dsi1_dma_addrs,
4214         .user           = OCP_USER_SDMA,
4215 };
4216
4217 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4218         {
4219                 .pa_start       = 0x48044000,
4220                 .pa_end         = 0x480441ff,
4221                 .flags          = ADDR_TYPE_RT
4222         },
4223         { }
4224 };
4225
4226 /* l4_per -> dss_dsi1 */
4227 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4228         .master         = &omap44xx_l4_per_hwmod,
4229         .slave          = &omap44xx_dss_dsi1_hwmod,
4230         .clk            = "l4_div_ck",
4231         .addr           = omap44xx_dss_dsi1_addrs,
4232         .user           = OCP_USER_MPU,
4233 };
4234
4235 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4236         {
4237                 .pa_start       = 0x58005000,
4238                 .pa_end         = 0x580051ff,
4239                 .flags          = ADDR_TYPE_RT
4240         },
4241         { }
4242 };
4243
4244 /* l3_main_2 -> dss_dsi2 */
4245 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4246         .master         = &omap44xx_l3_main_2_hwmod,
4247         .slave          = &omap44xx_dss_dsi2_hwmod,
4248         .clk            = "dss_fck",
4249         .addr           = omap44xx_dss_dsi2_dma_addrs,
4250         .user           = OCP_USER_SDMA,
4251 };
4252
4253 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4254         {
4255                 .pa_start       = 0x48045000,
4256                 .pa_end         = 0x480451ff,
4257                 .flags          = ADDR_TYPE_RT
4258         },
4259         { }
4260 };
4261
4262 /* l4_per -> dss_dsi2 */
4263 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4264         .master         = &omap44xx_l4_per_hwmod,
4265         .slave          = &omap44xx_dss_dsi2_hwmod,
4266         .clk            = "l4_div_ck",
4267         .addr           = omap44xx_dss_dsi2_addrs,
4268         .user           = OCP_USER_MPU,
4269 };
4270
4271 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4272         {
4273                 .pa_start       = 0x58006000,
4274                 .pa_end         = 0x58006fff,
4275                 .flags          = ADDR_TYPE_RT
4276         },
4277         { }
4278 };
4279
4280 /* l3_main_2 -> dss_hdmi */
4281 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4282         .master         = &omap44xx_l3_main_2_hwmod,
4283         .slave          = &omap44xx_dss_hdmi_hwmod,
4284         .clk            = "dss_fck",
4285         .addr           = omap44xx_dss_hdmi_dma_addrs,
4286         .user           = OCP_USER_SDMA,
4287 };
4288
4289 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4290         {
4291                 .pa_start       = 0x48046000,
4292                 .pa_end         = 0x48046fff,
4293                 .flags          = ADDR_TYPE_RT
4294         },
4295         { }
4296 };
4297
4298 /* l4_per -> dss_hdmi */
4299 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4300         .master         = &omap44xx_l4_per_hwmod,
4301         .slave          = &omap44xx_dss_hdmi_hwmod,
4302         .clk            = "l4_div_ck",
4303         .addr           = omap44xx_dss_hdmi_addrs,
4304         .user           = OCP_USER_MPU,
4305 };
4306
4307 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4308         {
4309                 .pa_start       = 0x58002000,
4310                 .pa_end         = 0x580020ff,
4311                 .flags          = ADDR_TYPE_RT
4312         },
4313         { }
4314 };
4315
4316 /* l3_main_2 -> dss_rfbi */
4317 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4318         .master         = &omap44xx_l3_main_2_hwmod,
4319         .slave          = &omap44xx_dss_rfbi_hwmod,
4320         .clk            = "dss_fck",
4321         .addr           = omap44xx_dss_rfbi_dma_addrs,
4322         .user           = OCP_USER_SDMA,
4323 };
4324
4325 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4326         {
4327                 .pa_start       = 0x48042000,
4328                 .pa_end         = 0x480420ff,
4329                 .flags          = ADDR_TYPE_RT
4330         },
4331         { }
4332 };
4333
4334 /* l4_per -> dss_rfbi */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4336         .master         = &omap44xx_l4_per_hwmod,
4337         .slave          = &omap44xx_dss_rfbi_hwmod,
4338         .clk            = "l4_div_ck",
4339         .addr           = omap44xx_dss_rfbi_addrs,
4340         .user           = OCP_USER_MPU,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4344         {
4345                 .pa_start       = 0x58003000,
4346                 .pa_end         = 0x580030ff,
4347                 .flags          = ADDR_TYPE_RT
4348         },
4349         { }
4350 };
4351
4352 /* l3_main_2 -> dss_venc */
4353 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4354         .master         = &omap44xx_l3_main_2_hwmod,
4355         .slave          = &omap44xx_dss_venc_hwmod,
4356         .clk            = "dss_fck",
4357         .addr           = omap44xx_dss_venc_dma_addrs,
4358         .user           = OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4362         {
4363                 .pa_start       = 0x48043000,
4364                 .pa_end         = 0x480430ff,
4365                 .flags          = ADDR_TYPE_RT
4366         },
4367         { }
4368 };
4369
4370 /* l4_per -> dss_venc */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4372         .master         = &omap44xx_l4_per_hwmod,
4373         .slave          = &omap44xx_dss_venc_hwmod,
4374         .clk            = "l4_div_ck",
4375         .addr           = omap44xx_dss_venc_addrs,
4376         .user           = OCP_USER_MPU,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4380         {
4381                 .pa_start       = 0x48078000,
4382                 .pa_end         = 0x48078fff,
4383                 .flags          = ADDR_TYPE_RT
4384         },
4385         { }
4386 };
4387
4388 /* l4_per -> elm */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4390         .master         = &omap44xx_l4_per_hwmod,
4391         .slave          = &omap44xx_elm_hwmod,
4392         .clk            = "l4_div_ck",
4393         .addr           = omap44xx_elm_addrs,
4394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4398         {
4399                 .pa_start       = 0x4c000000,
4400                 .pa_end         = 0x4c0000ff,
4401                 .flags          = ADDR_TYPE_RT
4402         },
4403         { }
4404 };
4405
4406 /* emif_fw -> emif1 */
4407 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4408         .master         = &omap44xx_emif_fw_hwmod,
4409         .slave          = &omap44xx_emif1_hwmod,
4410         .clk            = "l3_div_ck",
4411         .addr           = omap44xx_emif1_addrs,
4412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4416         {
4417                 .pa_start       = 0x4d000000,
4418                 .pa_end         = 0x4d0000ff,
4419                 .flags          = ADDR_TYPE_RT
4420         },
4421         { }
4422 };
4423
4424 /* emif_fw -> emif2 */
4425 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4426         .master         = &omap44xx_emif_fw_hwmod,
4427         .slave          = &omap44xx_emif2_hwmod,
4428         .clk            = "l3_div_ck",
4429         .addr           = omap44xx_emif2_addrs,
4430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4431 };
4432
4433 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4434         {
4435                 .pa_start       = 0x4a10a000,
4436                 .pa_end         = 0x4a10a1ff,
4437                 .flags          = ADDR_TYPE_RT
4438         },
4439         { }
4440 };
4441
4442 /* l4_cfg -> fdif */
4443 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4444         .master         = &omap44xx_l4_cfg_hwmod,
4445         .slave          = &omap44xx_fdif_hwmod,
4446         .clk            = "l4_div_ck",
4447         .addr           = omap44xx_fdif_addrs,
4448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4449 };
4450
4451 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4452         {
4453                 .pa_start       = 0x4a310000,
4454                 .pa_end         = 0x4a3101ff,
4455                 .flags          = ADDR_TYPE_RT
4456         },
4457         { }
4458 };
4459
4460 /* l4_wkup -> gpio1 */
4461 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4462         .master         = &omap44xx_l4_wkup_hwmod,
4463         .slave          = &omap44xx_gpio1_hwmod,
4464         .clk            = "l4_wkup_clk_mux_ck",
4465         .addr           = omap44xx_gpio1_addrs,
4466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4467 };
4468
4469 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4470         {
4471                 .pa_start       = 0x48055000,
4472                 .pa_end         = 0x480551ff,
4473                 .flags          = ADDR_TYPE_RT
4474         },
4475         { }
4476 };
4477
4478 /* l4_per -> gpio2 */
4479 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4480         .master         = &omap44xx_l4_per_hwmod,
4481         .slave          = &omap44xx_gpio2_hwmod,
4482         .clk            = "l4_div_ck",
4483         .addr           = omap44xx_gpio2_addrs,
4484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4485 };
4486
4487 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4488         {
4489                 .pa_start       = 0x48057000,
4490                 .pa_end         = 0x480571ff,
4491                 .flags          = ADDR_TYPE_RT
4492         },
4493         { }
4494 };
4495
4496 /* l4_per -> gpio3 */
4497 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4498         .master         = &omap44xx_l4_per_hwmod,
4499         .slave          = &omap44xx_gpio3_hwmod,
4500         .clk            = "l4_div_ck",
4501         .addr           = omap44xx_gpio3_addrs,
4502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4503 };
4504
4505 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4506         {
4507                 .pa_start       = 0x48059000,
4508                 .pa_end         = 0x480591ff,
4509                 .flags          = ADDR_TYPE_RT
4510         },
4511         { }
4512 };
4513
4514 /* l4_per -> gpio4 */
4515 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4516         .master         = &omap44xx_l4_per_hwmod,
4517         .slave          = &omap44xx_gpio4_hwmod,
4518         .clk            = "l4_div_ck",
4519         .addr           = omap44xx_gpio4_addrs,
4520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4521 };
4522
4523 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4524         {
4525                 .pa_start       = 0x4805b000,
4526                 .pa_end         = 0x4805b1ff,
4527                 .flags          = ADDR_TYPE_RT
4528         },
4529         { }
4530 };
4531
4532 /* l4_per -> gpio5 */
4533 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4534         .master         = &omap44xx_l4_per_hwmod,
4535         .slave          = &omap44xx_gpio5_hwmod,
4536         .clk            = "l4_div_ck",
4537         .addr           = omap44xx_gpio5_addrs,
4538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4539 };
4540
4541 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4542         {
4543                 .pa_start       = 0x4805d000,
4544                 .pa_end         = 0x4805d1ff,
4545                 .flags          = ADDR_TYPE_RT
4546         },
4547         { }
4548 };
4549
4550 /* l4_per -> gpio6 */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4552         .master         = &omap44xx_l4_per_hwmod,
4553         .slave          = &omap44xx_gpio6_hwmod,
4554         .clk            = "l4_div_ck",
4555         .addr           = omap44xx_gpio6_addrs,
4556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4557 };
4558
4559 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4560         {
4561                 .pa_start       = 0x50000000,
4562                 .pa_end         = 0x500003ff,
4563                 .flags          = ADDR_TYPE_RT
4564         },
4565         { }
4566 };
4567
4568 /* l3_main_2 -> gpmc */
4569 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4570         .master         = &omap44xx_l3_main_2_hwmod,
4571         .slave          = &omap44xx_gpmc_hwmod,
4572         .clk            = "l3_div_ck",
4573         .addr           = omap44xx_gpmc_addrs,
4574         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4575 };
4576
4577 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4578         {
4579                 .pa_start       = 0x56000000,
4580                 .pa_end         = 0x5600ffff,
4581                 .flags          = ADDR_TYPE_RT
4582         },
4583         { }
4584 };
4585
4586 /* l3_main_2 -> gpu */
4587 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4588         .master         = &omap44xx_l3_main_2_hwmod,
4589         .slave          = &omap44xx_gpu_hwmod,
4590         .clk            = "l3_div_ck",
4591         .addr           = omap44xx_gpu_addrs,
4592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4593 };
4594
4595 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4596         {
4597                 .pa_start       = 0x480b2000,
4598                 .pa_end         = 0x480b201f,
4599                 .flags          = ADDR_TYPE_RT
4600         },
4601         { }
4602 };
4603
4604 /* l4_per -> hdq1w */
4605 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4606         .master         = &omap44xx_l4_per_hwmod,
4607         .slave          = &omap44xx_hdq1w_hwmod,
4608         .clk            = "l4_div_ck",
4609         .addr           = omap44xx_hdq1w_addrs,
4610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4611 };
4612
4613 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4614         {
4615                 .pa_start       = 0x4a058000,
4616                 .pa_end         = 0x4a05bfff,
4617                 .flags          = ADDR_TYPE_RT
4618         },
4619         { }
4620 };
4621
4622 /* l4_cfg -> hsi */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4624         .master         = &omap44xx_l4_cfg_hwmod,
4625         .slave          = &omap44xx_hsi_hwmod,
4626         .clk            = "l4_div_ck",
4627         .addr           = omap44xx_hsi_addrs,
4628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4629 };
4630
4631 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4632         {
4633                 .pa_start       = 0x48070000,
4634                 .pa_end         = 0x480700ff,
4635                 .flags          = ADDR_TYPE_RT
4636         },
4637         { }
4638 };
4639
4640 /* l4_per -> i2c1 */
4641 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4642         .master         = &omap44xx_l4_per_hwmod,
4643         .slave          = &omap44xx_i2c1_hwmod,
4644         .clk            = "l4_div_ck",
4645         .addr           = omap44xx_i2c1_addrs,
4646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4647 };
4648
4649 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4650         {
4651                 .pa_start       = 0x48072000,
4652                 .pa_end         = 0x480720ff,
4653                 .flags          = ADDR_TYPE_RT
4654         },
4655         { }
4656 };
4657
4658 /* l4_per -> i2c2 */
4659 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4660         .master         = &omap44xx_l4_per_hwmod,
4661         .slave          = &omap44xx_i2c2_hwmod,
4662         .clk            = "l4_div_ck",
4663         .addr           = omap44xx_i2c2_addrs,
4664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4665 };
4666
4667 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4668         {
4669                 .pa_start       = 0x48060000,
4670                 .pa_end         = 0x480600ff,
4671                 .flags          = ADDR_TYPE_RT
4672         },
4673         { }
4674 };
4675
4676 /* l4_per -> i2c3 */
4677 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4678         .master         = &omap44xx_l4_per_hwmod,
4679         .slave          = &omap44xx_i2c3_hwmod,
4680         .clk            = "l4_div_ck",
4681         .addr           = omap44xx_i2c3_addrs,
4682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4683 };
4684
4685 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4686         {
4687                 .pa_start       = 0x48350000,
4688                 .pa_end         = 0x483500ff,
4689                 .flags          = ADDR_TYPE_RT
4690         },
4691         { }
4692 };
4693
4694 /* l4_per -> i2c4 */
4695 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4696         .master         = &omap44xx_l4_per_hwmod,
4697         .slave          = &omap44xx_i2c4_hwmod,
4698         .clk            = "l4_div_ck",
4699         .addr           = omap44xx_i2c4_addrs,
4700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4701 };
4702
4703 /* l3_main_2 -> ipu */
4704 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4705         .master         = &omap44xx_l3_main_2_hwmod,
4706         .slave          = &omap44xx_ipu_hwmod,
4707         .clk            = "l3_div_ck",
4708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4709 };
4710
4711 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4712         {
4713                 .pa_start       = 0x52000000,
4714                 .pa_end         = 0x520000ff,
4715                 .flags          = ADDR_TYPE_RT
4716         },
4717         { }
4718 };
4719
4720 /* l3_main_2 -> iss */
4721 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4722         .master         = &omap44xx_l3_main_2_hwmod,
4723         .slave          = &omap44xx_iss_hwmod,
4724         .clk            = "l3_div_ck",
4725         .addr           = omap44xx_iss_addrs,
4726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4727 };
4728
4729 /* iva -> sl2if */
4730 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4731         .master         = &omap44xx_iva_hwmod,
4732         .slave          = &omap44xx_sl2if_hwmod,
4733         .clk            = "dpll_iva_m5x2_ck",
4734         .user           = OCP_USER_IVA,
4735 };
4736
4737 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4738         {
4739                 .pa_start       = 0x5a000000,
4740                 .pa_end         = 0x5a07ffff,
4741                 .flags          = ADDR_TYPE_RT
4742         },
4743         { }
4744 };
4745
4746 /* l3_main_2 -> iva */
4747 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4748         .master         = &omap44xx_l3_main_2_hwmod,
4749         .slave          = &omap44xx_iva_hwmod,
4750         .clk            = "l3_div_ck",
4751         .addr           = omap44xx_iva_addrs,
4752         .user           = OCP_USER_MPU,
4753 };
4754
4755 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4756         {
4757                 .pa_start       = 0x4a31c000,
4758                 .pa_end         = 0x4a31c07f,
4759                 .flags          = ADDR_TYPE_RT
4760         },
4761         { }
4762 };
4763
4764 /* l4_wkup -> kbd */
4765 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4766         .master         = &omap44xx_l4_wkup_hwmod,
4767         .slave          = &omap44xx_kbd_hwmod,
4768         .clk            = "l4_wkup_clk_mux_ck",
4769         .addr           = omap44xx_kbd_addrs,
4770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4771 };
4772
4773 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4774         {
4775                 .pa_start       = 0x4a0f4000,
4776                 .pa_end         = 0x4a0f41ff,
4777                 .flags          = ADDR_TYPE_RT
4778         },
4779         { }
4780 };
4781
4782 /* l4_cfg -> mailbox */
4783 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4784         .master         = &omap44xx_l4_cfg_hwmod,
4785         .slave          = &omap44xx_mailbox_hwmod,
4786         .clk            = "l4_div_ck",
4787         .addr           = omap44xx_mailbox_addrs,
4788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4789 };
4790
4791 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4792         {
4793                 .pa_start       = 0x40128000,
4794                 .pa_end         = 0x401283ff,
4795                 .flags          = ADDR_TYPE_RT
4796         },
4797         { }
4798 };
4799
4800 /* l4_abe -> mcasp */
4801 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4802         .master         = &omap44xx_l4_abe_hwmod,
4803         .slave          = &omap44xx_mcasp_hwmod,
4804         .clk            = "ocp_abe_iclk",
4805         .addr           = omap44xx_mcasp_addrs,
4806         .user           = OCP_USER_MPU,
4807 };
4808
4809 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4810         {
4811                 .pa_start       = 0x49028000,
4812                 .pa_end         = 0x490283ff,
4813                 .flags          = ADDR_TYPE_RT
4814         },
4815         { }
4816 };
4817
4818 /* l4_abe -> mcasp (dma) */
4819 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4820         .master         = &omap44xx_l4_abe_hwmod,
4821         .slave          = &omap44xx_mcasp_hwmod,
4822         .clk            = "ocp_abe_iclk",
4823         .addr           = omap44xx_mcasp_dma_addrs,
4824         .user           = OCP_USER_SDMA,
4825 };
4826
4827 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4828         {
4829                 .name           = "mpu",
4830                 .pa_start       = 0x40122000,
4831                 .pa_end         = 0x401220ff,
4832                 .flags          = ADDR_TYPE_RT
4833         },
4834         { }
4835 };
4836
4837 /* l4_abe -> mcbsp1 */
4838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4839         .master         = &omap44xx_l4_abe_hwmod,
4840         .slave          = &omap44xx_mcbsp1_hwmod,
4841         .clk            = "ocp_abe_iclk",
4842         .addr           = omap44xx_mcbsp1_addrs,
4843         .user           = OCP_USER_MPU,
4844 };
4845
4846 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4847         {
4848                 .name           = "dma",
4849                 .pa_start       = 0x49022000,
4850                 .pa_end         = 0x490220ff,
4851                 .flags          = ADDR_TYPE_RT
4852         },
4853         { }
4854 };
4855
4856 /* l4_abe -> mcbsp1 (dma) */
4857 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4858         .master         = &omap44xx_l4_abe_hwmod,
4859         .slave          = &omap44xx_mcbsp1_hwmod,
4860         .clk            = "ocp_abe_iclk",
4861         .addr           = omap44xx_mcbsp1_dma_addrs,
4862         .user           = OCP_USER_SDMA,
4863 };
4864
4865 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4866         {
4867                 .name           = "mpu",
4868                 .pa_start       = 0x40124000,
4869                 .pa_end         = 0x401240ff,
4870                 .flags          = ADDR_TYPE_RT
4871         },
4872         { }
4873 };
4874
4875 /* l4_abe -> mcbsp2 */
4876 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4877         .master         = &omap44xx_l4_abe_hwmod,
4878         .slave          = &omap44xx_mcbsp2_hwmod,
4879         .clk            = "ocp_abe_iclk",
4880         .addr           = omap44xx_mcbsp2_addrs,
4881         .user           = OCP_USER_MPU,
4882 };
4883
4884 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4885         {
4886                 .name           = "dma",
4887                 .pa_start       = 0x49024000,
4888                 .pa_end         = 0x490240ff,
4889                 .flags          = ADDR_TYPE_RT
4890         },
4891         { }
4892 };
4893
4894 /* l4_abe -> mcbsp2 (dma) */
4895 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4896         .master         = &omap44xx_l4_abe_hwmod,
4897         .slave          = &omap44xx_mcbsp2_hwmod,
4898         .clk            = "ocp_abe_iclk",
4899         .addr           = omap44xx_mcbsp2_dma_addrs,
4900         .user           = OCP_USER_SDMA,
4901 };
4902
4903 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
4904         {
4905                 .name           = "mpu",
4906                 .pa_start       = 0x40126000,
4907                 .pa_end         = 0x401260ff,
4908                 .flags          = ADDR_TYPE_RT
4909         },
4910         { }
4911 };
4912
4913 /* l4_abe -> mcbsp3 */
4914 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4915         .master         = &omap44xx_l4_abe_hwmod,
4916         .slave          = &omap44xx_mcbsp3_hwmod,
4917         .clk            = "ocp_abe_iclk",
4918         .addr           = omap44xx_mcbsp3_addrs,
4919         .user           = OCP_USER_MPU,
4920 };
4921
4922 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
4923         {
4924                 .name           = "dma",
4925                 .pa_start       = 0x49026000,
4926                 .pa_end         = 0x490260ff,
4927                 .flags          = ADDR_TYPE_RT
4928         },
4929         { }
4930 };
4931
4932 /* l4_abe -> mcbsp3 (dma) */
4933 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
4934         .master         = &omap44xx_l4_abe_hwmod,
4935         .slave          = &omap44xx_mcbsp3_hwmod,
4936         .clk            = "ocp_abe_iclk",
4937         .addr           = omap44xx_mcbsp3_dma_addrs,
4938         .user           = OCP_USER_SDMA,
4939 };
4940
4941 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
4942         {
4943                 .pa_start       = 0x48096000,
4944                 .pa_end         = 0x480960ff,
4945                 .flags          = ADDR_TYPE_RT
4946         },
4947         { }
4948 };
4949
4950 /* l4_per -> mcbsp4 */
4951 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4952         .master         = &omap44xx_l4_per_hwmod,
4953         .slave          = &omap44xx_mcbsp4_hwmod,
4954         .clk            = "l4_div_ck",
4955         .addr           = omap44xx_mcbsp4_addrs,
4956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4957 };
4958
4959 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
4960         {
4961                 .pa_start       = 0x40132000,
4962                 .pa_end         = 0x4013207f,
4963                 .flags          = ADDR_TYPE_RT
4964         },
4965         { }
4966 };
4967
4968 /* l4_abe -> mcpdm */
4969 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4970         .master         = &omap44xx_l4_abe_hwmod,
4971         .slave          = &omap44xx_mcpdm_hwmod,
4972         .clk            = "ocp_abe_iclk",
4973         .addr           = omap44xx_mcpdm_addrs,
4974         .user           = OCP_USER_MPU,
4975 };
4976
4977 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
4978         {
4979                 .pa_start       = 0x49032000,
4980                 .pa_end         = 0x4903207f,
4981                 .flags          = ADDR_TYPE_RT
4982         },
4983         { }
4984 };
4985
4986 /* l4_abe -> mcpdm (dma) */
4987 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
4988         .master         = &omap44xx_l4_abe_hwmod,
4989         .slave          = &omap44xx_mcpdm_hwmod,
4990         .clk            = "ocp_abe_iclk",
4991         .addr           = omap44xx_mcpdm_dma_addrs,
4992         .user           = OCP_USER_SDMA,
4993 };
4994
4995 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
4996         {
4997                 .pa_start       = 0x48098000,
4998                 .pa_end         = 0x480981ff,
4999                 .flags          = ADDR_TYPE_RT
5000         },
5001         { }
5002 };
5003
5004 /* l4_per -> mcspi1 */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5006         .master         = &omap44xx_l4_per_hwmod,
5007         .slave          = &omap44xx_mcspi1_hwmod,
5008         .clk            = "l4_div_ck",
5009         .addr           = omap44xx_mcspi1_addrs,
5010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5011 };
5012
5013 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5014         {
5015                 .pa_start       = 0x4809a000,
5016                 .pa_end         = 0x4809a1ff,
5017                 .flags          = ADDR_TYPE_RT
5018         },
5019         { }
5020 };
5021
5022 /* l4_per -> mcspi2 */
5023 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5024         .master         = &omap44xx_l4_per_hwmod,
5025         .slave          = &omap44xx_mcspi2_hwmod,
5026         .clk            = "l4_div_ck",
5027         .addr           = omap44xx_mcspi2_addrs,
5028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5029 };
5030
5031 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5032         {
5033                 .pa_start       = 0x480b8000,
5034                 .pa_end         = 0x480b81ff,
5035                 .flags          = ADDR_TYPE_RT
5036         },
5037         { }
5038 };
5039
5040 /* l4_per -> mcspi3 */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5042         .master         = &omap44xx_l4_per_hwmod,
5043         .slave          = &omap44xx_mcspi3_hwmod,
5044         .clk            = "l4_div_ck",
5045         .addr           = omap44xx_mcspi3_addrs,
5046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5047 };
5048
5049 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5050         {
5051                 .pa_start       = 0x480ba000,
5052                 .pa_end         = 0x480ba1ff,
5053                 .flags          = ADDR_TYPE_RT
5054         },
5055         { }
5056 };
5057
5058 /* l4_per -> mcspi4 */
5059 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5060         .master         = &omap44xx_l4_per_hwmod,
5061         .slave          = &omap44xx_mcspi4_hwmod,
5062         .clk            = "l4_div_ck",
5063         .addr           = omap44xx_mcspi4_addrs,
5064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5065 };
5066
5067 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5068         {
5069                 .pa_start       = 0x4809c000,
5070                 .pa_end         = 0x4809c3ff,
5071                 .flags          = ADDR_TYPE_RT
5072         },
5073         { }
5074 };
5075
5076 /* l4_per -> mmc1 */
5077 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5078         .master         = &omap44xx_l4_per_hwmod,
5079         .slave          = &omap44xx_mmc1_hwmod,
5080         .clk            = "l4_div_ck",
5081         .addr           = omap44xx_mmc1_addrs,
5082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5083 };
5084
5085 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5086         {
5087                 .pa_start       = 0x480b4000,
5088                 .pa_end         = 0x480b43ff,
5089                 .flags          = ADDR_TYPE_RT
5090         },
5091         { }
5092 };
5093
5094 /* l4_per -> mmc2 */
5095 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5096         .master         = &omap44xx_l4_per_hwmod,
5097         .slave          = &omap44xx_mmc2_hwmod,
5098         .clk            = "l4_div_ck",
5099         .addr           = omap44xx_mmc2_addrs,
5100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5101 };
5102
5103 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5104         {
5105                 .pa_start       = 0x480ad000,
5106                 .pa_end         = 0x480ad3ff,
5107                 .flags          = ADDR_TYPE_RT
5108         },
5109         { }
5110 };
5111
5112 /* l4_per -> mmc3 */
5113 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5114         .master         = &omap44xx_l4_per_hwmod,
5115         .slave          = &omap44xx_mmc3_hwmod,
5116         .clk            = "l4_div_ck",
5117         .addr           = omap44xx_mmc3_addrs,
5118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5119 };
5120
5121 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5122         {
5123                 .pa_start       = 0x480d1000,
5124                 .pa_end         = 0x480d13ff,
5125                 .flags          = ADDR_TYPE_RT
5126         },
5127         { }
5128 };
5129
5130 /* l4_per -> mmc4 */
5131 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5132         .master         = &omap44xx_l4_per_hwmod,
5133         .slave          = &omap44xx_mmc4_hwmod,
5134         .clk            = "l4_div_ck",
5135         .addr           = omap44xx_mmc4_addrs,
5136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5137 };
5138
5139 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5140         {
5141                 .pa_start       = 0x480d5000,
5142                 .pa_end         = 0x480d53ff,
5143                 .flags          = ADDR_TYPE_RT
5144         },
5145         { }
5146 };
5147
5148 /* l4_per -> mmc5 */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5150         .master         = &omap44xx_l4_per_hwmod,
5151         .slave          = &omap44xx_mmc5_hwmod,
5152         .clk            = "l4_div_ck",
5153         .addr           = omap44xx_mmc5_addrs,
5154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5155 };
5156
5157 /* l3_main_2 -> ocmc_ram */
5158 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5159         .master         = &omap44xx_l3_main_2_hwmod,
5160         .slave          = &omap44xx_ocmc_ram_hwmod,
5161         .clk            = "l3_div_ck",
5162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5163 };
5164
5165 /* l4_cfg -> ocp2scp_usb_phy */
5166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5167         .master         = &omap44xx_l4_cfg_hwmod,
5168         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5169         .clk            = "l4_div_ck",
5170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5171 };
5172
5173 /* l3_main_2 -> sl2if */
5174 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5175         .master         = &omap44xx_l3_main_2_hwmod,
5176         .slave          = &omap44xx_sl2if_hwmod,
5177         .clk            = "l3_div_ck",
5178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5179 };
5180
5181 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5182         {
5183                 .pa_start       = 0x4012c000,
5184                 .pa_end         = 0x4012c3ff,
5185                 .flags          = ADDR_TYPE_RT
5186         },
5187         { }
5188 };
5189
5190 /* l4_abe -> slimbus1 */
5191 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5192         .master         = &omap44xx_l4_abe_hwmod,
5193         .slave          = &omap44xx_slimbus1_hwmod,
5194         .clk            = "ocp_abe_iclk",
5195         .addr           = omap44xx_slimbus1_addrs,
5196         .user           = OCP_USER_MPU,
5197 };
5198
5199 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5200         {
5201                 .pa_start       = 0x4902c000,
5202                 .pa_end         = 0x4902c3ff,
5203                 .flags          = ADDR_TYPE_RT
5204         },
5205         { }
5206 };
5207
5208 /* l4_abe -> slimbus1 (dma) */
5209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5210         .master         = &omap44xx_l4_abe_hwmod,
5211         .slave          = &omap44xx_slimbus1_hwmod,
5212         .clk            = "ocp_abe_iclk",
5213         .addr           = omap44xx_slimbus1_dma_addrs,
5214         .user           = OCP_USER_SDMA,
5215 };
5216
5217 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5218         {
5219                 .pa_start       = 0x48076000,
5220                 .pa_end         = 0x480763ff,
5221                 .flags          = ADDR_TYPE_RT
5222         },
5223         { }
5224 };
5225
5226 /* l4_per -> slimbus2 */
5227 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5228         .master         = &omap44xx_l4_per_hwmod,
5229         .slave          = &omap44xx_slimbus2_hwmod,
5230         .clk            = "l4_div_ck",
5231         .addr           = omap44xx_slimbus2_addrs,
5232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5233 };
5234
5235 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5236         {
5237                 .pa_start       = 0x4a0dd000,
5238                 .pa_end         = 0x4a0dd03f,
5239                 .flags          = ADDR_TYPE_RT
5240         },
5241         { }
5242 };
5243
5244 /* l4_cfg -> smartreflex_core */
5245 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5246         .master         = &omap44xx_l4_cfg_hwmod,
5247         .slave          = &omap44xx_smartreflex_core_hwmod,
5248         .clk            = "l4_div_ck",
5249         .addr           = omap44xx_smartreflex_core_addrs,
5250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5251 };
5252
5253 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5254         {
5255                 .pa_start       = 0x4a0db000,
5256                 .pa_end         = 0x4a0db03f,
5257                 .flags          = ADDR_TYPE_RT
5258         },
5259         { }
5260 };
5261
5262 /* l4_cfg -> smartreflex_iva */
5263 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5264         .master         = &omap44xx_l4_cfg_hwmod,
5265         .slave          = &omap44xx_smartreflex_iva_hwmod,
5266         .clk            = "l4_div_ck",
5267         .addr           = omap44xx_smartreflex_iva_addrs,
5268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5269 };
5270
5271 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5272         {
5273                 .pa_start       = 0x4a0d9000,
5274                 .pa_end         = 0x4a0d903f,
5275                 .flags          = ADDR_TYPE_RT
5276         },
5277         { }
5278 };
5279
5280 /* l4_cfg -> smartreflex_mpu */
5281 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5282         .master         = &omap44xx_l4_cfg_hwmod,
5283         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5284         .clk            = "l4_div_ck",
5285         .addr           = omap44xx_smartreflex_mpu_addrs,
5286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5287 };
5288
5289 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5290         {
5291                 .pa_start       = 0x4a0f6000,
5292                 .pa_end         = 0x4a0f6fff,
5293                 .flags          = ADDR_TYPE_RT
5294         },
5295         { }
5296 };
5297
5298 /* l4_cfg -> spinlock */
5299 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5300         .master         = &omap44xx_l4_cfg_hwmod,
5301         .slave          = &omap44xx_spinlock_hwmod,
5302         .clk            = "l4_div_ck",
5303         .addr           = omap44xx_spinlock_addrs,
5304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5305 };
5306
5307 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5308         {
5309                 .pa_start       = 0x4a318000,
5310                 .pa_end         = 0x4a31807f,
5311                 .flags          = ADDR_TYPE_RT
5312         },
5313         { }
5314 };
5315
5316 /* l4_wkup -> timer1 */
5317 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5318         .master         = &omap44xx_l4_wkup_hwmod,
5319         .slave          = &omap44xx_timer1_hwmod,
5320         .clk            = "l4_wkup_clk_mux_ck",
5321         .addr           = omap44xx_timer1_addrs,
5322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5323 };
5324
5325 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5326         {
5327                 .pa_start       = 0x48032000,
5328                 .pa_end         = 0x4803207f,
5329                 .flags          = ADDR_TYPE_RT
5330         },
5331         { }
5332 };
5333
5334 /* l4_per -> timer2 */
5335 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5336         .master         = &omap44xx_l4_per_hwmod,
5337         .slave          = &omap44xx_timer2_hwmod,
5338         .clk            = "l4_div_ck",
5339         .addr           = omap44xx_timer2_addrs,
5340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5341 };
5342
5343 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5344         {
5345                 .pa_start       = 0x48034000,
5346                 .pa_end         = 0x4803407f,
5347                 .flags          = ADDR_TYPE_RT
5348         },
5349         { }
5350 };
5351
5352 /* l4_per -> timer3 */
5353 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5354         .master         = &omap44xx_l4_per_hwmod,
5355         .slave          = &omap44xx_timer3_hwmod,
5356         .clk            = "l4_div_ck",
5357         .addr           = omap44xx_timer3_addrs,
5358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5359 };
5360
5361 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5362         {
5363                 .pa_start       = 0x48036000,
5364                 .pa_end         = 0x4803607f,
5365                 .flags          = ADDR_TYPE_RT
5366         },
5367         { }
5368 };
5369
5370 /* l4_per -> timer4 */
5371 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5372         .master         = &omap44xx_l4_per_hwmod,
5373         .slave          = &omap44xx_timer4_hwmod,
5374         .clk            = "l4_div_ck",
5375         .addr           = omap44xx_timer4_addrs,
5376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5377 };
5378
5379 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5380         {
5381                 .pa_start       = 0x40138000,
5382                 .pa_end         = 0x4013807f,
5383                 .flags          = ADDR_TYPE_RT
5384         },
5385         { }
5386 };
5387
5388 /* l4_abe -> timer5 */
5389 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5390         .master         = &omap44xx_l4_abe_hwmod,
5391         .slave          = &omap44xx_timer5_hwmod,
5392         .clk            = "ocp_abe_iclk",
5393         .addr           = omap44xx_timer5_addrs,
5394         .user           = OCP_USER_MPU,
5395 };
5396
5397 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5398         {
5399                 .pa_start       = 0x49038000,
5400                 .pa_end         = 0x4903807f,
5401                 .flags          = ADDR_TYPE_RT
5402         },
5403         { }
5404 };
5405
5406 /* l4_abe -> timer5 (dma) */
5407 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5408         .master         = &omap44xx_l4_abe_hwmod,
5409         .slave          = &omap44xx_timer5_hwmod,
5410         .clk            = "ocp_abe_iclk",
5411         .addr           = omap44xx_timer5_dma_addrs,
5412         .user           = OCP_USER_SDMA,
5413 };
5414
5415 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5416         {
5417                 .pa_start       = 0x4013a000,
5418                 .pa_end         = 0x4013a07f,
5419                 .flags          = ADDR_TYPE_RT
5420         },
5421         { }
5422 };
5423
5424 /* l4_abe -> timer6 */
5425 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5426         .master         = &omap44xx_l4_abe_hwmod,
5427         .slave          = &omap44xx_timer6_hwmod,
5428         .clk            = "ocp_abe_iclk",
5429         .addr           = omap44xx_timer6_addrs,
5430         .user           = OCP_USER_MPU,
5431 };
5432
5433 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5434         {
5435                 .pa_start       = 0x4903a000,
5436                 .pa_end         = 0x4903a07f,
5437                 .flags          = ADDR_TYPE_RT
5438         },
5439         { }
5440 };
5441
5442 /* l4_abe -> timer6 (dma) */
5443 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5444         .master         = &omap44xx_l4_abe_hwmod,
5445         .slave          = &omap44xx_timer6_hwmod,
5446         .clk            = "ocp_abe_iclk",
5447         .addr           = omap44xx_timer6_dma_addrs,
5448         .user           = OCP_USER_SDMA,
5449 };
5450
5451 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5452         {
5453                 .pa_start       = 0x4013c000,
5454                 .pa_end         = 0x4013c07f,
5455                 .flags          = ADDR_TYPE_RT
5456         },
5457         { }
5458 };
5459
5460 /* l4_abe -> timer7 */
5461 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5462         .master         = &omap44xx_l4_abe_hwmod,
5463         .slave          = &omap44xx_timer7_hwmod,
5464         .clk            = "ocp_abe_iclk",
5465         .addr           = omap44xx_timer7_addrs,
5466         .user           = OCP_USER_MPU,
5467 };
5468
5469 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5470         {
5471                 .pa_start       = 0x4903c000,
5472                 .pa_end         = 0x4903c07f,
5473                 .flags          = ADDR_TYPE_RT
5474         },
5475         { }
5476 };
5477
5478 /* l4_abe -> timer7 (dma) */
5479 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5480         .master         = &omap44xx_l4_abe_hwmod,
5481         .slave          = &omap44xx_timer7_hwmod,
5482         .clk            = "ocp_abe_iclk",
5483         .addr           = omap44xx_timer7_dma_addrs,
5484         .user           = OCP_USER_SDMA,
5485 };
5486
5487 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5488         {
5489                 .pa_start       = 0x4013e000,
5490                 .pa_end         = 0x4013e07f,
5491                 .flags          = ADDR_TYPE_RT
5492         },
5493         { }
5494 };
5495
5496 /* l4_abe -> timer8 */
5497 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5498         .master         = &omap44xx_l4_abe_hwmod,
5499         .slave          = &omap44xx_timer8_hwmod,
5500         .clk            = "ocp_abe_iclk",
5501         .addr           = omap44xx_timer8_addrs,
5502         .user           = OCP_USER_MPU,
5503 };
5504
5505 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5506         {
5507                 .pa_start       = 0x4903e000,
5508                 .pa_end         = 0x4903e07f,
5509                 .flags          = ADDR_TYPE_RT
5510         },
5511         { }
5512 };
5513
5514 /* l4_abe -> timer8 (dma) */
5515 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5516         .master         = &omap44xx_l4_abe_hwmod,
5517         .slave          = &omap44xx_timer8_hwmod,
5518         .clk            = "ocp_abe_iclk",
5519         .addr           = omap44xx_timer8_dma_addrs,
5520         .user           = OCP_USER_SDMA,
5521 };
5522
5523 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5524         {
5525                 .pa_start       = 0x4803e000,
5526                 .pa_end         = 0x4803e07f,
5527                 .flags          = ADDR_TYPE_RT
5528         },
5529         { }
5530 };
5531
5532 /* l4_per -> timer9 */
5533 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5534         .master         = &omap44xx_l4_per_hwmod,
5535         .slave          = &omap44xx_timer9_hwmod,
5536         .clk            = "l4_div_ck",
5537         .addr           = omap44xx_timer9_addrs,
5538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5539 };
5540
5541 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5542         {
5543                 .pa_start       = 0x48086000,
5544                 .pa_end         = 0x4808607f,
5545                 .flags          = ADDR_TYPE_RT
5546         },
5547         { }
5548 };
5549
5550 /* l4_per -> timer10 */
5551 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5552         .master         = &omap44xx_l4_per_hwmod,
5553         .slave          = &omap44xx_timer10_hwmod,
5554         .clk            = "l4_div_ck",
5555         .addr           = omap44xx_timer10_addrs,
5556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5557 };
5558
5559 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5560         {
5561                 .pa_start       = 0x48088000,
5562                 .pa_end         = 0x4808807f,
5563                 .flags          = ADDR_TYPE_RT
5564         },
5565         { }
5566 };
5567
5568 /* l4_per -> timer11 */
5569 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5570         .master         = &omap44xx_l4_per_hwmod,
5571         .slave          = &omap44xx_timer11_hwmod,
5572         .clk            = "l4_div_ck",
5573         .addr           = omap44xx_timer11_addrs,
5574         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5575 };
5576
5577 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5578         {
5579                 .pa_start       = 0x4806a000,
5580                 .pa_end         = 0x4806a0ff,
5581                 .flags          = ADDR_TYPE_RT
5582         },
5583         { }
5584 };
5585
5586 /* l4_per -> uart1 */
5587 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5588         .master         = &omap44xx_l4_per_hwmod,
5589         .slave          = &omap44xx_uart1_hwmod,
5590         .clk            = "l4_div_ck",
5591         .addr           = omap44xx_uart1_addrs,
5592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5593 };
5594
5595 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5596         {
5597                 .pa_start       = 0x4806c000,
5598                 .pa_end         = 0x4806c0ff,
5599                 .flags          = ADDR_TYPE_RT
5600         },
5601         { }
5602 };
5603
5604 /* l4_per -> uart2 */
5605 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5606         .master         = &omap44xx_l4_per_hwmod,
5607         .slave          = &omap44xx_uart2_hwmod,
5608         .clk            = "l4_div_ck",
5609         .addr           = omap44xx_uart2_addrs,
5610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5611 };
5612
5613 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5614         {
5615                 .pa_start       = 0x48020000,
5616                 .pa_end         = 0x480200ff,
5617                 .flags          = ADDR_TYPE_RT
5618         },
5619         { }
5620 };
5621
5622 /* l4_per -> uart3 */
5623 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5624         .master         = &omap44xx_l4_per_hwmod,
5625         .slave          = &omap44xx_uart3_hwmod,
5626         .clk            = "l4_div_ck",
5627         .addr           = omap44xx_uart3_addrs,
5628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5629 };
5630
5631 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5632         {
5633                 .pa_start       = 0x4806e000,
5634                 .pa_end         = 0x4806e0ff,
5635                 .flags          = ADDR_TYPE_RT
5636         },
5637         { }
5638 };
5639
5640 /* l4_per -> uart4 */
5641 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5642         .master         = &omap44xx_l4_per_hwmod,
5643         .slave          = &omap44xx_uart4_hwmod,
5644         .clk            = "l4_div_ck",
5645         .addr           = omap44xx_uart4_addrs,
5646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5647 };
5648
5649 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5650         {
5651                 .pa_start       = 0x4a0a9000,
5652                 .pa_end         = 0x4a0a93ff,
5653                 .flags          = ADDR_TYPE_RT
5654         },
5655         { }
5656 };
5657
5658 /* l4_cfg -> usb_host_fs */
5659 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5660         .master         = &omap44xx_l4_cfg_hwmod,
5661         .slave          = &omap44xx_usb_host_fs_hwmod,
5662         .clk            = "l4_div_ck",
5663         .addr           = omap44xx_usb_host_fs_addrs,
5664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5665 };
5666
5667 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5668         {
5669                 .name           = "uhh",
5670                 .pa_start       = 0x4a064000,
5671                 .pa_end         = 0x4a0647ff,
5672                 .flags          = ADDR_TYPE_RT
5673         },
5674         {
5675                 .name           = "ohci",
5676                 .pa_start       = 0x4a064800,
5677                 .pa_end         = 0x4a064bff,
5678         },
5679         {
5680                 .name           = "ehci",
5681                 .pa_start       = 0x4a064c00,
5682                 .pa_end         = 0x4a064fff,
5683         },
5684         {}
5685 };
5686
5687 /* l4_cfg -> usb_host_hs */
5688 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5689         .master         = &omap44xx_l4_cfg_hwmod,
5690         .slave          = &omap44xx_usb_host_hs_hwmod,
5691         .clk            = "l4_div_ck",
5692         .addr           = omap44xx_usb_host_hs_addrs,
5693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5694 };
5695
5696 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5697         {
5698                 .pa_start       = 0x4a0ab000,
5699                 .pa_end         = 0x4a0ab003,
5700                 .flags          = ADDR_TYPE_RT
5701         },
5702         { }
5703 };
5704
5705 /* l4_cfg -> usb_otg_hs */
5706 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5707         .master         = &omap44xx_l4_cfg_hwmod,
5708         .slave          = &omap44xx_usb_otg_hs_hwmod,
5709         .clk            = "l4_div_ck",
5710         .addr           = omap44xx_usb_otg_hs_addrs,
5711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5712 };
5713
5714 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5715         {
5716                 .name           = "tll",
5717                 .pa_start       = 0x4a062000,
5718                 .pa_end         = 0x4a063fff,
5719                 .flags          = ADDR_TYPE_RT
5720         },
5721         {}
5722 };
5723
5724 /* l4_cfg -> usb_tll_hs */
5725 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5726         .master         = &omap44xx_l4_cfg_hwmod,
5727         .slave          = &omap44xx_usb_tll_hs_hwmod,
5728         .clk            = "l4_div_ck",
5729         .addr           = omap44xx_usb_tll_hs_addrs,
5730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5731 };
5732
5733 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5734         {
5735                 .pa_start       = 0x4a314000,
5736                 .pa_end         = 0x4a31407f,
5737                 .flags          = ADDR_TYPE_RT
5738         },
5739         { }
5740 };
5741
5742 /* l4_wkup -> wd_timer2 */
5743 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5744         .master         = &omap44xx_l4_wkup_hwmod,
5745         .slave          = &omap44xx_wd_timer2_hwmod,
5746         .clk            = "l4_wkup_clk_mux_ck",
5747         .addr           = omap44xx_wd_timer2_addrs,
5748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5749 };
5750
5751 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5752         {
5753                 .pa_start       = 0x40130000,
5754                 .pa_end         = 0x4013007f,
5755                 .flags          = ADDR_TYPE_RT
5756         },
5757         { }
5758 };
5759
5760 /* l4_abe -> wd_timer3 */
5761 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5762         .master         = &omap44xx_l4_abe_hwmod,
5763         .slave          = &omap44xx_wd_timer3_hwmod,
5764         .clk            = "ocp_abe_iclk",
5765         .addr           = omap44xx_wd_timer3_addrs,
5766         .user           = OCP_USER_MPU,
5767 };
5768
5769 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5770         {
5771                 .pa_start       = 0x49030000,
5772                 .pa_end         = 0x4903007f,
5773                 .flags          = ADDR_TYPE_RT
5774         },
5775         { }
5776 };
5777
5778 /* l4_abe -> wd_timer3 (dma) */
5779 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5780         .master         = &omap44xx_l4_abe_hwmod,
5781         .slave          = &omap44xx_wd_timer3_hwmod,
5782         .clk            = "ocp_abe_iclk",
5783         .addr           = omap44xx_wd_timer3_dma_addrs,
5784         .user           = OCP_USER_SDMA,
5785 };
5786
5787 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5788         &omap44xx_c2c__c2c_target_fw,
5789         &omap44xx_l4_cfg__c2c_target_fw,
5790         &omap44xx_l3_main_1__dmm,
5791         &omap44xx_mpu__dmm,
5792         &omap44xx_c2c__emif_fw,
5793         &omap44xx_dmm__emif_fw,
5794         &omap44xx_l4_cfg__emif_fw,
5795         &omap44xx_iva__l3_instr,
5796         &omap44xx_l3_main_3__l3_instr,
5797         &omap44xx_ocp_wp_noc__l3_instr,
5798         &omap44xx_dsp__l3_main_1,
5799         &omap44xx_dss__l3_main_1,
5800         &omap44xx_l3_main_2__l3_main_1,
5801         &omap44xx_l4_cfg__l3_main_1,
5802         &omap44xx_mmc1__l3_main_1,
5803         &omap44xx_mmc2__l3_main_1,
5804         &omap44xx_mpu__l3_main_1,
5805         &omap44xx_c2c_target_fw__l3_main_2,
5806         &omap44xx_dma_system__l3_main_2,
5807         &omap44xx_fdif__l3_main_2,
5808         &omap44xx_gpu__l3_main_2,
5809         &omap44xx_hsi__l3_main_2,
5810         &omap44xx_ipu__l3_main_2,
5811         &omap44xx_iss__l3_main_2,
5812         &omap44xx_iva__l3_main_2,
5813         &omap44xx_l3_main_1__l3_main_2,
5814         &omap44xx_l4_cfg__l3_main_2,
5815         &omap44xx_usb_host_fs__l3_main_2,
5816         &omap44xx_usb_host_hs__l3_main_2,
5817         &omap44xx_usb_otg_hs__l3_main_2,
5818         &omap44xx_l3_main_1__l3_main_3,
5819         &omap44xx_l3_main_2__l3_main_3,
5820         &omap44xx_l4_cfg__l3_main_3,
5821         &omap44xx_aess__l4_abe,
5822         &omap44xx_dsp__l4_abe,
5823         &omap44xx_l3_main_1__l4_abe,
5824         &omap44xx_mpu__l4_abe,
5825         &omap44xx_l3_main_1__l4_cfg,
5826         &omap44xx_l3_main_2__l4_per,
5827         &omap44xx_l4_cfg__l4_wkup,
5828         &omap44xx_mpu__mpu_private,
5829         &omap44xx_l4_cfg__ocp_wp_noc,
5830         &omap44xx_l4_abe__aess,
5831         &omap44xx_l4_abe__aess_dma,
5832         &omap44xx_l3_main_2__c2c,
5833         &omap44xx_l4_wkup__counter_32k,
5834         &omap44xx_l4_cfg__ctrl_module_core,
5835         &omap44xx_l4_cfg__ctrl_module_pad_core,
5836         &omap44xx_l4_wkup__ctrl_module_wkup,
5837         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
5838         &omap44xx_l4_cfg__dma_system,
5839         &omap44xx_l4_abe__dmic,
5840         &omap44xx_l4_abe__dmic_dma,
5841         &omap44xx_dsp__iva,
5842         &omap44xx_dsp__sl2if,
5843         &omap44xx_l4_cfg__dsp,
5844         &omap44xx_l3_main_2__dss,
5845         &omap44xx_l4_per__dss,
5846         &omap44xx_l3_main_2__dss_dispc,
5847         &omap44xx_l4_per__dss_dispc,
5848         &omap44xx_l3_main_2__dss_dsi1,
5849         &omap44xx_l4_per__dss_dsi1,
5850         &omap44xx_l3_main_2__dss_dsi2,
5851         &omap44xx_l4_per__dss_dsi2,
5852         &omap44xx_l3_main_2__dss_hdmi,
5853         &omap44xx_l4_per__dss_hdmi,
5854         &omap44xx_l3_main_2__dss_rfbi,
5855         &omap44xx_l4_per__dss_rfbi,
5856         &omap44xx_l3_main_2__dss_venc,
5857         &omap44xx_l4_per__dss_venc,
5858         &omap44xx_l4_per__elm,
5859         &omap44xx_emif_fw__emif1,
5860         &omap44xx_emif_fw__emif2,
5861         &omap44xx_l4_cfg__fdif,
5862         &omap44xx_l4_wkup__gpio1,
5863         &omap44xx_l4_per__gpio2,
5864         &omap44xx_l4_per__gpio3,
5865         &omap44xx_l4_per__gpio4,
5866         &omap44xx_l4_per__gpio5,
5867         &omap44xx_l4_per__gpio6,
5868         &omap44xx_l3_main_2__gpmc,
5869         &omap44xx_l3_main_2__gpu,
5870         &omap44xx_l4_per__hdq1w,
5871         &omap44xx_l4_cfg__hsi,
5872         &omap44xx_l4_per__i2c1,
5873         &omap44xx_l4_per__i2c2,
5874         &omap44xx_l4_per__i2c3,
5875         &omap44xx_l4_per__i2c4,
5876         &omap44xx_l3_main_2__ipu,
5877         &omap44xx_l3_main_2__iss,
5878         &omap44xx_iva__sl2if,
5879         &omap44xx_l3_main_2__iva,
5880         &omap44xx_l4_wkup__kbd,
5881         &omap44xx_l4_cfg__mailbox,
5882         &omap44xx_l4_abe__mcasp,
5883         &omap44xx_l4_abe__mcasp_dma,
5884         &omap44xx_l4_abe__mcbsp1,
5885         &omap44xx_l4_abe__mcbsp1_dma,
5886         &omap44xx_l4_abe__mcbsp2,
5887         &omap44xx_l4_abe__mcbsp2_dma,
5888         &omap44xx_l4_abe__mcbsp3,
5889         &omap44xx_l4_abe__mcbsp3_dma,
5890         &omap44xx_l4_per__mcbsp4,
5891         &omap44xx_l4_abe__mcpdm,
5892         &omap44xx_l4_abe__mcpdm_dma,
5893         &omap44xx_l4_per__mcspi1,
5894         &omap44xx_l4_per__mcspi2,
5895         &omap44xx_l4_per__mcspi3,
5896         &omap44xx_l4_per__mcspi4,
5897         &omap44xx_l4_per__mmc1,
5898         &omap44xx_l4_per__mmc2,
5899         &omap44xx_l4_per__mmc3,
5900         &omap44xx_l4_per__mmc4,
5901         &omap44xx_l4_per__mmc5,
5902         &omap44xx_l3_main_2__ocmc_ram,
5903         &omap44xx_l4_cfg__ocp2scp_usb_phy,
5904         &omap44xx_l3_main_2__sl2if,
5905         &omap44xx_l4_abe__slimbus1,
5906         &omap44xx_l4_abe__slimbus1_dma,
5907         &omap44xx_l4_per__slimbus2,
5908         &omap44xx_l4_cfg__smartreflex_core,
5909         &omap44xx_l4_cfg__smartreflex_iva,
5910         &omap44xx_l4_cfg__smartreflex_mpu,
5911         &omap44xx_l4_cfg__spinlock,
5912         &omap44xx_l4_wkup__timer1,
5913         &omap44xx_l4_per__timer2,
5914         &omap44xx_l4_per__timer3,
5915         &omap44xx_l4_per__timer4,
5916         &omap44xx_l4_abe__timer5,
5917         &omap44xx_l4_abe__timer5_dma,
5918         &omap44xx_l4_abe__timer6,
5919         &omap44xx_l4_abe__timer6_dma,
5920         &omap44xx_l4_abe__timer7,
5921         &omap44xx_l4_abe__timer7_dma,
5922         &omap44xx_l4_abe__timer8,
5923         &omap44xx_l4_abe__timer8_dma,
5924         &omap44xx_l4_per__timer9,
5925         &omap44xx_l4_per__timer10,
5926         &omap44xx_l4_per__timer11,
5927         &omap44xx_l4_per__uart1,
5928         &omap44xx_l4_per__uart2,
5929         &omap44xx_l4_per__uart3,
5930         &omap44xx_l4_per__uart4,
5931         &omap44xx_l4_cfg__usb_host_fs,
5932         &omap44xx_l4_cfg__usb_host_hs,
5933         &omap44xx_l4_cfg__usb_otg_hs,
5934         &omap44xx_l4_cfg__usb_tll_hs,
5935         &omap44xx_l4_wkup__wd_timer2,
5936         &omap44xx_l4_abe__wd_timer3,
5937         &omap44xx_l4_abe__wd_timer3_dma,
5938         NULL,
5939 };
5940
5941 int __init omap44xx_hwmod_init(void)
5942 {
5943         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
5944 }
5945