arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'l3' class
  53  * instance(s): l3_instr, l3_main_1, l3_main_2
  54  */
  55 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  56         .name   = "l3",
  57 };
  58
  59 /* l3_instr */
  60 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &dra7xx_l3_hwmod_class,
  63         .clkdm_name     = "l3instr_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  68                         .modulemode   = MODULEMODE_HWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /* l3_main_1 */
  74 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  75         .name           = "l3_main_1",
  76         .class          = &dra7xx_l3_hwmod_class,
  77         .clkdm_name     = "l3main1_clkdm",
  78         .prcm = {
  79                 .omap4 = {
  80                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  81                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  82                 },
  83         },
  84 };
  85
  86 /* l3_main_2 */
  87 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  88         .name           = "l3_main_2",
  89         .class          = &dra7xx_l3_hwmod_class,
  90         .clkdm_name     = "l3instr_clkdm",
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  94                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  95                         .modulemode   = MODULEMODE_HWCTRL,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'l4' class
 102  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 103  */
 104 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 105         .name   = "l4",
 106 };
 107
 108 /* l4_cfg */
 109 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 110         .name           = "l4_cfg",
 111         .class          = &dra7xx_l4_hwmod_class,
 112         .clkdm_name     = "l4cfg_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 116                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 117                 },
 118         },
 119 };
 120
 121 /* l4_per1 */
 122 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 123         .name           = "l4_per1",
 124         .class          = &dra7xx_l4_hwmod_class,
 125         .clkdm_name     = "l4per_clkdm",
 126         .prcm = {
 127                 .omap4 = {
 128                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 129                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 130                 },
 131         },
 132 };
 133
 134 /* l4_per2 */
 135 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 136         .name           = "l4_per2",
 137         .class          = &dra7xx_l4_hwmod_class,
 138         .clkdm_name     = "l4per2_clkdm",
 139         .prcm = {
 140                 .omap4 = {
 141                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 142                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 143                 },
 144         },
 145 };
 146
 147 /* l4_per3 */
 148 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 149         .name           = "l4_per3",
 150         .class          = &dra7xx_l4_hwmod_class,
 151         .clkdm_name     = "l4per3_clkdm",
 152         .prcm = {
 153                 .omap4 = {
 154                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 155                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_wkup */
 161 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 162         .name           = "l4_wkup",
 163         .class          = &dra7xx_l4_hwmod_class,
 164         .clkdm_name     = "wkupaon_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 168                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /*
 174  * 'atl' class
 175  *
 176  */
 177
 178 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 179         .name   = "atl",
 180 };
 181
 182 /* atl */
 183 static struct omap_hwmod dra7xx_atl_hwmod = {
 184         .name           = "atl",
 185         .class          = &dra7xx_atl_hwmod_class,
 186         .clkdm_name     = "atl_clkdm",
 187         .main_clk       = "atl_gfclk_mux",
 188         .prcm = {
 189                 .omap4 = {
 190                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 191                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 192                         .modulemode   = MODULEMODE_SWCTRL,
 193                 },
 194         },
 195 };
 196
 197 /*
 198  * 'bb2d' class
 199  *
 200  */
 201
 202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 203         .name   = "bb2d",
 204 };
 205
 206 /* bb2d */
 207 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 208         .name           = "bb2d",
 209         .class          = &dra7xx_bb2d_hwmod_class,
 210         .clkdm_name     = "dss_clkdm",
 211         .main_clk       = "dpll_core_h24x2_ck",
 212         .prcm = {
 213                 .omap4 = {
 214                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 215                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 216                         .modulemode   = MODULEMODE_SWCTRL,
 217                 },
 218         },
 219 };
 220
 221 /*
 222  * 'counter' class
 223  *
 224  */
 225
 226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 227         .rev_offs       = 0x0000,
 228         .sysc_offs      = 0x0010,
 229         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 230         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 231                            SIDLE_SMART_WKUP),
 232         .sysc_fields    = &omap_hwmod_sysc_type1,
 233 };
 234
 235 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 236         .name   = "counter",
 237         .sysc   = &dra7xx_counter_sysc,
 238 };
 239
 240 /* counter_32k */
 241 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 242         .name           = "counter_32k",
 243         .class          = &dra7xx_counter_hwmod_class,
 244         .clkdm_name     = "wkupaon_clkdm",
 245         .flags          = HWMOD_SWSUP_SIDLE,
 246         .main_clk       = "wkupaon_iclk_mux",
 247         .prcm = {
 248                 .omap4 = {
 249                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 250                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 251                 },
 252         },
 253 };
 254
 255 /*
 256  * 'ctrl_module' class
 257  *
 258  */
 259
 260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 261         .name   = "ctrl_module",
 262 };
 263
 264 /* ctrl_module_wkup */
 265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 266         .name           = "ctrl_module_wkup",
 267         .class          = &dra7xx_ctrl_module_hwmod_class,
 268         .clkdm_name     = "wkupaon_clkdm",
 269         .prcm = {
 270                 .omap4 = {
 271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'gmac' class
 278  * cpsw/gmac sub system
 279  */
 280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 281         .rev_offs       = 0x0,
 282         .sysc_offs      = 0x8,
 283         .syss_offs      = 0x4,
 284         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 285                            SYSS_HAS_RESET_STATUS),
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 287                            MSTANDBY_NO),
 288         .sysc_fields    = &omap_hwmod_sysc_type3,
 289 };
 290
 291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 292         .name           = "gmac",
 293         .sysc           = &dra7xx_gmac_sysc,
 294 };
 295
 296 static struct omap_hwmod dra7xx_gmac_hwmod = {
 297         .name           = "gmac",
 298         .class          = &dra7xx_gmac_hwmod_class,
 299         .clkdm_name     = "gmac_clkdm",
 300         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 301         .main_clk       = "dpll_gmac_ck",
 302         .mpu_rt_idx     = 1,
 303         .prcm           = {
 304                 .omap4  = {
 305                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 306                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 307                         .modulemode     = MODULEMODE_SWCTRL,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'mdio' class
 314  */
 315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 316         .name           = "davinci_mdio",
 317 };
 318
 319 static struct omap_hwmod dra7xx_mdio_hwmod = {
 320         .name           = "davinci_mdio",
 321         .class          = &dra7xx_mdio_hwmod_class,
 322         .clkdm_name     = "gmac_clkdm",
 323         .main_clk       = "dpll_gmac_ck",
 324 };
 325
 326 /*
 327  * 'dcan' class
 328  *
 329  */
 330
 331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 332         .name   = "dcan",
 333 };
 334
 335 /* dcan1 */
 336 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 337         .name           = "dcan1",
 338         .class          = &dra7xx_dcan_hwmod_class,
 339         .clkdm_name     = "wkupaon_clkdm",
 340         .main_clk       = "dcan1_sys_clk_mux",
 341         .prcm = {
 342                 .omap4 = {
 343                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 344                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 345                         .modulemode   = MODULEMODE_SWCTRL,
 346                 },
 347         },
 348 };
 349
 350 /* dcan2 */
 351 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 352         .name           = "dcan2",
 353         .class          = &dra7xx_dcan_hwmod_class,
 354         .clkdm_name     = "l4per2_clkdm",
 355         .main_clk       = "sys_clkin1",
 356         .prcm = {
 357                 .omap4 = {
 358                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 359                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 360                         .modulemode   = MODULEMODE_SWCTRL,
 361                 },
 362         },
 363 };
 364
 365 /*
 366  * 'dma' class
 367  *
 368  */
 369
 370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 371         .rev_offs       = 0x0000,
 372         .sysc_offs      = 0x002c,
 373         .syss_offs      = 0x0028,
 374         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 375                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 376                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 377                            SYSS_HAS_RESET_STATUS),
 378         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 379                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 380                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 381         .sysc_fields    = &omap_hwmod_sysc_type1,
 382 };
 383
 384 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 385         .name   = "dma",
 386         .sysc   = &dra7xx_dma_sysc,
 387 };
 388
 389 /* dma dev_attr */
 390 static struct omap_dma_dev_attr dma_dev_attr = {
 391         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 392                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 393         .lch_count      = 32,
 394 };
 395
 396 /* dma_system */
 397 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 398         .name           = "dma_system",
 399         .class          = &dra7xx_dma_hwmod_class,
 400         .clkdm_name     = "dma_clkdm",
 401         .main_clk       = "l3_iclk_div",
 402         .prcm = {
 403                 .omap4 = {
 404                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 405                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 406                 },
 407         },
 408         .dev_attr       = &dma_dev_attr,
 409 };
 410
 411 /*
 412  * 'dss' class
 413  *
 414  */
 415
 416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 417         .rev_offs       = 0x0000,
 418         .syss_offs      = 0x0014,
 419         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 420 };
 421
 422 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 423         .name   = "dss",
 424         .sysc   = &dra7xx_dss_sysc,
 425         .reset  = omap_dss_reset,
 426 };
 427
 428 /* dss */
 429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 430         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 431         { .dma_req = -1 }
 432 };
 433
 434 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 435         { .role = "dss_clk", .clk = "dss_dss_clk" },
 436         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 437         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 438         { .role = "video2_clk", .clk = "dss_video2_clk" },
 439         { .role = "video1_clk", .clk = "dss_video1_clk" },
 440         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 441 };
 442
 443 static struct omap_hwmod dra7xx_dss_hwmod = {
 444         .name           = "dss_core",
 445         .class          = &dra7xx_dss_hwmod_class,
 446         .clkdm_name     = "dss_clkdm",
 447         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 448         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 449         .main_clk       = "dss_dss_clk",
 450         .prcm = {
 451                 .omap4 = {
 452                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 453                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 454                         .modulemode   = MODULEMODE_SWCTRL,
 455                 },
 456         },
 457         .opt_clks       = dss_opt_clks,
 458         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 459 };
 460
 461 /*
 462  * 'dispc' class
 463  * display controller
 464  */
 465
 466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 467         .rev_offs       = 0x0000,
 468         .sysc_offs      = 0x0010,
 469         .syss_offs      = 0x0014,
 470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 471                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 472                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 473                            SYSS_HAS_RESET_STATUS),
 474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 475                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 476         .sysc_fields    = &omap_hwmod_sysc_type1,
 477 };
 478
 479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 480         .name   = "dispc",
 481         .sysc   = &dra7xx_dispc_sysc,
 482 };
 483
 484 /* dss_dispc */
 485 /* dss_dispc dev_attr */
 486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 487         .has_framedonetv_irq    = 1,
 488         .manager_count          = 4,
 489 };
 490
 491 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 492         .name           = "dss_dispc",
 493         .class          = &dra7xx_dispc_hwmod_class,
 494         .clkdm_name     = "dss_clkdm",
 495         .main_clk       = "dss_dss_clk",
 496         .prcm = {
 497                 .omap4 = {
 498                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502         .dev_attr       = &dss_dispc_dev_attr,
 503 };
 504
 505 /*
 506  * 'hdmi' class
 507  * hdmi controller
 508  */
 509
 510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 511         .rev_offs       = 0x0000,
 512         .sysc_offs      = 0x0010,
 513         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 514                            SYSC_HAS_SOFTRESET),
 515         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 516                            SIDLE_SMART_WKUP),
 517         .sysc_fields    = &omap_hwmod_sysc_type2,
 518 };
 519
 520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 521         .name   = "hdmi",
 522         .sysc   = &dra7xx_hdmi_sysc,
 523 };
 524
 525 /* dss_hdmi */
 526
 527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 528         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 529 };
 530
 531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 532         .name           = "dss_hdmi",
 533         .class          = &dra7xx_hdmi_hwmod_class,
 534         .clkdm_name     = "dss_clkdm",
 535         .main_clk       = "dss_48mhz_clk",
 536         .prcm = {
 537                 .omap4 = {
 538                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 539                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 540                 },
 541         },
 542         .opt_clks       = dss_hdmi_opt_clks,
 543         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 544 };
 545
 546 /*
 547  * 'elm' class
 548  *
 549  */
 550
 551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 556                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 557                            SYSS_HAS_RESET_STATUS),
 558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 559                            SIDLE_SMART_WKUP),
 560         .sysc_fields    = &omap_hwmod_sysc_type1,
 561 };
 562
 563 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 564         .name   = "elm",
 565         .sysc   = &dra7xx_elm_sysc,
 566 };
 567
 568 /* elm */
 569
 570 static struct omap_hwmod dra7xx_elm_hwmod = {
 571         .name           = "elm",
 572         .class          = &dra7xx_elm_hwmod_class,
 573         .clkdm_name     = "l4per_clkdm",
 574         .main_clk       = "l3_iclk_div",
 575         .prcm = {
 576                 .omap4 = {
 577                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 578                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 579                 },
 580         },
 581 };
 582
 583 /*
 584  * 'gpio' class
 585  *
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .syss_offs      = 0x0114,
 592         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 594                            SYSS_HAS_RESET_STATUS),
 595         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 596                            SIDLE_SMART_WKUP),
 597         .sysc_fields    = &omap_hwmod_sysc_type1,
 598 };
 599
 600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 601         .name   = "gpio",
 602         .sysc   = &dra7xx_gpio_sysc,
 603         .rev    = 2,
 604 };
 605
 606 /* gpio dev_attr */
 607 static struct omap_gpio_dev_attr gpio_dev_attr = {
 608         .bank_width     = 32,
 609         .dbck_flag      = true,
 610 };
 611
 612 /* gpio1 */
 613 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 614         { .role = "dbclk", .clk = "gpio1_dbclk" },
 615 };
 616
 617 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 618         .name           = "gpio1",
 619         .class          = &dra7xx_gpio_hwmod_class,
 620         .clkdm_name     = "wkupaon_clkdm",
 621         .main_clk       = "wkupaon_iclk_mux",
 622         .prcm = {
 623                 .omap4 = {
 624                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 625                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 626                         .modulemode   = MODULEMODE_HWCTRL,
 627                 },
 628         },
 629         .opt_clks       = gpio1_opt_clks,
 630         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 631         .dev_attr       = &gpio_dev_attr,
 632 };
 633
 634 /* gpio2 */
 635 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 636         { .role = "dbclk", .clk = "gpio2_dbclk" },
 637 };
 638
 639 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 640         .name           = "gpio2",
 641         .class          = &dra7xx_gpio_hwmod_class,
 642         .clkdm_name     = "l4per_clkdm",
 643         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 644         .main_clk       = "l3_iclk_div",
 645         .prcm = {
 646                 .omap4 = {
 647                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 648                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 649                         .modulemode   = MODULEMODE_HWCTRL,
 650                 },
 651         },
 652         .opt_clks       = gpio2_opt_clks,
 653         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 654         .dev_attr       = &gpio_dev_attr,
 655 };
 656
 657 /* gpio3 */
 658 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 659         { .role = "dbclk", .clk = "gpio3_dbclk" },
 660 };
 661
 662 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 663         .name           = "gpio3",
 664         .class          = &dra7xx_gpio_hwmod_class,
 665         .clkdm_name     = "l4per_clkdm",
 666         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 667         .main_clk       = "l3_iclk_div",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 671                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 672                         .modulemode   = MODULEMODE_HWCTRL,
 673                 },
 674         },
 675         .opt_clks       = gpio3_opt_clks,
 676         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 677         .dev_attr       = &gpio_dev_attr,
 678 };
 679
 680 /* gpio4 */
 681 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 682         { .role = "dbclk", .clk = "gpio4_dbclk" },
 683 };
 684
 685 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 686         .name           = "gpio4",
 687         .class          = &dra7xx_gpio_hwmod_class,
 688         .clkdm_name     = "l4per_clkdm",
 689         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 690         .main_clk       = "l3_iclk_div",
 691         .prcm = {
 692                 .omap4 = {
 693                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 694                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 695                         .modulemode   = MODULEMODE_HWCTRL,
 696                 },
 697         },
 698         .opt_clks       = gpio4_opt_clks,
 699         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 700         .dev_attr       = &gpio_dev_attr,
 701 };
 702
 703 /* gpio5 */
 704 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 705         { .role = "dbclk", .clk = "gpio5_dbclk" },
 706 };
 707
 708 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 709         .name           = "gpio5",
 710         .class          = &dra7xx_gpio_hwmod_class,
 711         .clkdm_name     = "l4per_clkdm",
 712         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 713         .main_clk       = "l3_iclk_div",
 714         .prcm = {
 715                 .omap4 = {
 716                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 717                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 718                         .modulemode   = MODULEMODE_HWCTRL,
 719                 },
 720         },
 721         .opt_clks       = gpio5_opt_clks,
 722         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 723         .dev_attr       = &gpio_dev_attr,
 724 };
 725
 726 /* gpio6 */
 727 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 728         { .role = "dbclk", .clk = "gpio6_dbclk" },
 729 };
 730
 731 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 732         .name           = "gpio6",
 733         .class          = &dra7xx_gpio_hwmod_class,
 734         .clkdm_name     = "l4per_clkdm",
 735         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 736         .main_clk       = "l3_iclk_div",
 737         .prcm = {
 738                 .omap4 = {
 739                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 740                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 741                         .modulemode   = MODULEMODE_HWCTRL,
 742                 },
 743         },
 744         .opt_clks       = gpio6_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 746         .dev_attr       = &gpio_dev_attr,
 747 };
 748
 749 /* gpio7 */
 750 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 751         { .role = "dbclk", .clk = "gpio7_dbclk" },
 752 };
 753
 754 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 755         .name           = "gpio7",
 756         .class          = &dra7xx_gpio_hwmod_class,
 757         .clkdm_name     = "l4per_clkdm",
 758         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 759         .main_clk       = "l3_iclk_div",
 760         .prcm = {
 761                 .omap4 = {
 762                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 763                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 764                         .modulemode   = MODULEMODE_HWCTRL,
 765                 },
 766         },
 767         .opt_clks       = gpio7_opt_clks,
 768         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 769         .dev_attr       = &gpio_dev_attr,
 770 };
 771
 772 /* gpio8 */
 773 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 774         { .role = "dbclk", .clk = "gpio8_dbclk" },
 775 };
 776
 777 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 778         .name           = "gpio8",
 779         .class          = &dra7xx_gpio_hwmod_class,
 780         .clkdm_name     = "l4per_clkdm",
 781         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 782         .main_clk       = "l3_iclk_div",
 783         .prcm = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 786                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 787                         .modulemode   = MODULEMODE_HWCTRL,
 788                 },
 789         },
 790         .opt_clks       = gpio8_opt_clks,
 791         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 792         .dev_attr       = &gpio_dev_attr,
 793 };
 794
 795 /*
 796  * 'gpmc' class
 797  *
 798  */
 799
 800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 801         .rev_offs       = 0x0000,
 802         .sysc_offs      = 0x0010,
 803         .syss_offs      = 0x0014,
 804         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 805                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 807                            SIDLE_SMART_WKUP),
 808         .sysc_fields    = &omap_hwmod_sysc_type1,
 809 };
 810
 811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 812         .name   = "gpmc",
 813         .sysc   = &dra7xx_gpmc_sysc,
 814 };
 815
 816 /* gpmc */
 817
 818 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 819         .name           = "gpmc",
 820         .class          = &dra7xx_gpmc_hwmod_class,
 821         .clkdm_name     = "l3main1_clkdm",
 822         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 823                            HWMOD_SWSUP_SIDLE),
 824         .main_clk       = "l3_iclk_div",
 825         .prcm = {
 826                 .omap4 = {
 827                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 828                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 829                         .modulemode   = MODULEMODE_HWCTRL,
 830                 },
 831         },
 832 };
 833
 834 /*
 835  * 'hdq1w' class
 836  *
 837  */
 838
 839 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 840         .rev_offs       = 0x0000,
 841         .sysc_offs      = 0x0014,
 842         .syss_offs      = 0x0018,
 843         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 844                            SYSS_HAS_RESET_STATUS),
 845         .sysc_fields    = &omap_hwmod_sysc_type1,
 846 };
 847
 848 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 849         .name   = "hdq1w",
 850         .sysc   = &dra7xx_hdq1w_sysc,
 851 };
 852
 853 /* hdq1w */
 854
 855 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 856         .name           = "hdq1w",
 857         .class          = &dra7xx_hdq1w_hwmod_class,
 858         .clkdm_name     = "l4per_clkdm",
 859         .flags          = HWMOD_INIT_NO_RESET,
 860         .main_clk       = "func_12m_fclk",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 864                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 865                         .modulemode   = MODULEMODE_SWCTRL,
 866                 },
 867         },
 868 };
 869
 870 /*
 871  * 'i2c' class
 872  *
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
 876         .sysc_offs      = 0x0010,
 877         .syss_offs      = 0x0090,
 878         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 879                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 880                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 881         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 882                            SIDLE_SMART_WKUP),
 883         .clockact       = CLOCKACT_TEST_ICLK,
 884         .sysc_fields    = &omap_hwmod_sysc_type1,
 885 };
 886
 887 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
 888         .name   = "i2c",
 889         .sysc   = &dra7xx_i2c_sysc,
 890         .reset  = &omap_i2c_reset,
 891         .rev    = OMAP_I2C_IP_VERSION_2,
 892 };
 893
 894 /* i2c dev_attr */
 895 static struct omap_i2c_dev_attr i2c_dev_attr = {
 896         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 897 };
 898
 899 /* i2c1 */
 900 static struct omap_hwmod dra7xx_i2c1_hwmod = {
 901         .name           = "i2c1",
 902         .class          = &dra7xx_i2c_hwmod_class,
 903         .clkdm_name     = "l4per_clkdm",
 904         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 905         .main_clk       = "func_96m_fclk",
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 909                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 910                         .modulemode   = MODULEMODE_SWCTRL,
 911                 },
 912         },
 913         .dev_attr       = &i2c_dev_attr,
 914 };
 915
 916 /* i2c2 */
 917 static struct omap_hwmod dra7xx_i2c2_hwmod = {
 918         .name           = "i2c2",
 919         .class          = &dra7xx_i2c_hwmod_class,
 920         .clkdm_name     = "l4per_clkdm",
 921         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 922         .main_clk       = "func_96m_fclk",
 923         .prcm = {
 924                 .omap4 = {
 925                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 926                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 927                         .modulemode   = MODULEMODE_SWCTRL,
 928                 },
 929         },
 930         .dev_attr       = &i2c_dev_attr,
 931 };
 932
 933 /* i2c3 */
 934 static struct omap_hwmod dra7xx_i2c3_hwmod = {
 935         .name           = "i2c3",
 936         .class          = &dra7xx_i2c_hwmod_class,
 937         .clkdm_name     = "l4per_clkdm",
 938         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 939         .main_clk       = "func_96m_fclk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 943                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 944                         .modulemode   = MODULEMODE_SWCTRL,
 945                 },
 946         },
 947         .dev_attr       = &i2c_dev_attr,
 948 };
 949
 950 /* i2c4 */
 951 static struct omap_hwmod dra7xx_i2c4_hwmod = {
 952         .name           = "i2c4",
 953         .class          = &dra7xx_i2c_hwmod_class,
 954         .clkdm_name     = "l4per_clkdm",
 955         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 956         .main_clk       = "func_96m_fclk",
 957         .prcm = {
 958                 .omap4 = {
 959                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 960                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 961                         .modulemode   = MODULEMODE_SWCTRL,
 962                 },
 963         },
 964         .dev_attr       = &i2c_dev_attr,
 965 };
 966
 967 /* i2c5 */
 968 static struct omap_hwmod dra7xx_i2c5_hwmod = {
 969         .name           = "i2c5",
 970         .class          = &dra7xx_i2c_hwmod_class,
 971         .clkdm_name     = "ipu_clkdm",
 972         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 973         .main_clk       = "func_96m_fclk",
 974         .prcm = {
 975                 .omap4 = {
 976                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
 977                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
 978                         .modulemode   = MODULEMODE_SWCTRL,
 979                 },
 980         },
 981         .dev_attr       = &i2c_dev_attr,
 982 };
 983
 984 /*
 985  * 'mailbox' class
 986  *
 987  */
 988
 989 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 993                            SYSC_HAS_SOFTRESET),
 994         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 995         .sysc_fields    = &omap_hwmod_sysc_type2,
 996 };
 997
 998 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
 999         .name   = "mailbox",
1000         .sysc   = &dra7xx_mailbox_sysc,
1001 };
1002
1003 /* mailbox1 */
1004 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1005         .name           = "mailbox1",
1006         .class          = &dra7xx_mailbox_hwmod_class,
1007         .clkdm_name     = "l4cfg_clkdm",
1008         .prcm = {
1009                 .omap4 = {
1010                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1011                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1012                 },
1013         },
1014 };
1015
1016 /* mailbox2 */
1017 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1018         .name           = "mailbox2",
1019         .class          = &dra7xx_mailbox_hwmod_class,
1020         .clkdm_name     = "l4cfg_clkdm",
1021         .prcm = {
1022                 .omap4 = {
1023                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1024                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1025                 },
1026         },
1027 };
1028
1029 /* mailbox3 */
1030 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1031         .name           = "mailbox3",
1032         .class          = &dra7xx_mailbox_hwmod_class,
1033         .clkdm_name     = "l4cfg_clkdm",
1034         .prcm = {
1035                 .omap4 = {
1036                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1037                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1038                 },
1039         },
1040 };
1041
1042 /* mailbox4 */
1043 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1044         .name           = "mailbox4",
1045         .class          = &dra7xx_mailbox_hwmod_class,
1046         .clkdm_name     = "l4cfg_clkdm",
1047         .prcm = {
1048                 .omap4 = {
1049                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1050                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1051                 },
1052         },
1053 };
1054
1055 /* mailbox5 */
1056 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1057         .name           = "mailbox5",
1058         .class          = &dra7xx_mailbox_hwmod_class,
1059         .clkdm_name     = "l4cfg_clkdm",
1060         .prcm = {
1061                 .omap4 = {
1062                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1063                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1064                 },
1065         },
1066 };
1067
1068 /* mailbox6 */
1069 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1070         .name           = "mailbox6",
1071         .class          = &dra7xx_mailbox_hwmod_class,
1072         .clkdm_name     = "l4cfg_clkdm",
1073         .prcm = {
1074                 .omap4 = {
1075                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1076                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1077                 },
1078         },
1079 };
1080
1081 /* mailbox7 */
1082 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1083         .name           = "mailbox7",
1084         .class          = &dra7xx_mailbox_hwmod_class,
1085         .clkdm_name     = "l4cfg_clkdm",
1086         .prcm = {
1087                 .omap4 = {
1088                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1089                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1090                 },
1091         },
1092 };
1093
1094 /* mailbox8 */
1095 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1096         .name           = "mailbox8",
1097         .class          = &dra7xx_mailbox_hwmod_class,
1098         .clkdm_name     = "l4cfg_clkdm",
1099         .prcm = {
1100                 .omap4 = {
1101                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1102                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1103                 },
1104         },
1105 };
1106
1107 /* mailbox9 */
1108 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1109         .name           = "mailbox9",
1110         .class          = &dra7xx_mailbox_hwmod_class,
1111         .clkdm_name     = "l4cfg_clkdm",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1115                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1116                 },
1117         },
1118 };
1119
1120 /* mailbox10 */
1121 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1122         .name           = "mailbox10",
1123         .class          = &dra7xx_mailbox_hwmod_class,
1124         .clkdm_name     = "l4cfg_clkdm",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1128                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1129                 },
1130         },
1131 };
1132
1133 /* mailbox11 */
1134 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1135         .name           = "mailbox11",
1136         .class          = &dra7xx_mailbox_hwmod_class,
1137         .clkdm_name     = "l4cfg_clkdm",
1138         .prcm = {
1139                 .omap4 = {
1140                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1141                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1142                 },
1143         },
1144 };
1145
1146 /* mailbox12 */
1147 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1148         .name           = "mailbox12",
1149         .class          = &dra7xx_mailbox_hwmod_class,
1150         .clkdm_name     = "l4cfg_clkdm",
1151         .prcm = {
1152                 .omap4 = {
1153                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1154                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1155                 },
1156         },
1157 };
1158
1159 /* mailbox13 */
1160 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1161         .name           = "mailbox13",
1162         .class          = &dra7xx_mailbox_hwmod_class,
1163         .clkdm_name     = "l4cfg_clkdm",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1167                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1168                 },
1169         },
1170 };
1171
1172 /*
1173  * 'mcspi' class
1174  *
1175  */
1176
1177 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1178         .rev_offs       = 0x0000,
1179         .sysc_offs      = 0x0010,
1180         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1181                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1183                            SIDLE_SMART_WKUP),
1184         .sysc_fields    = &omap_hwmod_sysc_type2,
1185 };
1186
1187 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1188         .name   = "mcspi",
1189         .sysc   = &dra7xx_mcspi_sysc,
1190         .rev    = OMAP4_MCSPI_REV,
1191 };
1192
1193 /* mcspi1 */
1194 /* mcspi1 dev_attr */
1195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1196         .num_chipselect = 4,
1197 };
1198
1199 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1200         .name           = "mcspi1",
1201         .class          = &dra7xx_mcspi_hwmod_class,
1202         .clkdm_name     = "l4per_clkdm",
1203         .main_clk       = "func_48m_fclk",
1204         .prcm = {
1205                 .omap4 = {
1206                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1207                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1208                         .modulemode   = MODULEMODE_SWCTRL,
1209                 },
1210         },
1211         .dev_attr       = &mcspi1_dev_attr,
1212 };
1213
1214 /* mcspi2 */
1215 /* mcspi2 dev_attr */
1216 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1217         .num_chipselect = 2,
1218 };
1219
1220 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1221         .name           = "mcspi2",
1222         .class          = &dra7xx_mcspi_hwmod_class,
1223         .clkdm_name     = "l4per_clkdm",
1224         .main_clk       = "func_48m_fclk",
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1228                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1229                         .modulemode   = MODULEMODE_SWCTRL,
1230                 },
1231         },
1232         .dev_attr       = &mcspi2_dev_attr,
1233 };
1234
1235 /* mcspi3 */
1236 /* mcspi3 dev_attr */
1237 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1238         .num_chipselect = 2,
1239 };
1240
1241 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1242         .name           = "mcspi3",
1243         .class          = &dra7xx_mcspi_hwmod_class,
1244         .clkdm_name     = "l4per_clkdm",
1245         .main_clk       = "func_48m_fclk",
1246         .prcm = {
1247                 .omap4 = {
1248                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1249                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1250                         .modulemode   = MODULEMODE_SWCTRL,
1251                 },
1252         },
1253         .dev_attr       = &mcspi3_dev_attr,
1254 };
1255
1256 /* mcspi4 */
1257 /* mcspi4 dev_attr */
1258 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1259         .num_chipselect = 1,
1260 };
1261
1262 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1263         .name           = "mcspi4",
1264         .class          = &dra7xx_mcspi_hwmod_class,
1265         .clkdm_name     = "l4per_clkdm",
1266         .main_clk       = "func_48m_fclk",
1267         .prcm = {
1268                 .omap4 = {
1269                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1270                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1271                         .modulemode   = MODULEMODE_SWCTRL,
1272                 },
1273         },
1274         .dev_attr       = &mcspi4_dev_attr,
1275 };
1276
1277 /*
1278  * 'mmc' class
1279  *
1280  */
1281
1282 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1283         .rev_offs       = 0x0000,
1284         .sysc_offs      = 0x0010,
1285         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1286                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1287                            SYSC_HAS_SOFTRESET),
1288         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1289                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1290                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1291         .sysc_fields    = &omap_hwmod_sysc_type2,
1292 };
1293
1294 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1295         .name   = "mmc",
1296         .sysc   = &dra7xx_mmc_sysc,
1297 };
1298
1299 /* mmc1 */
1300 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1301         { .role = "clk32k", .clk = "mmc1_clk32k" },
1302 };
1303
1304 /* mmc1 dev_attr */
1305 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1306         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1307 };
1308
1309 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1310         .name           = "mmc1",
1311         .class          = &dra7xx_mmc_hwmod_class,
1312         .clkdm_name     = "l3init_clkdm",
1313         .main_clk       = "mmc1_fclk_div",
1314         .prcm = {
1315                 .omap4 = {
1316                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1317                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1318                         .modulemode   = MODULEMODE_SWCTRL,
1319                 },
1320         },
1321         .opt_clks       = mmc1_opt_clks,
1322         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1323         .dev_attr       = &mmc1_dev_attr,
1324 };
1325
1326 /* mmc2 */
1327 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1328         { .role = "clk32k", .clk = "mmc2_clk32k" },
1329 };
1330
1331 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1332         .name           = "mmc2",
1333         .class          = &dra7xx_mmc_hwmod_class,
1334         .clkdm_name     = "l3init_clkdm",
1335         .main_clk       = "mmc2_fclk_div",
1336         .prcm = {
1337                 .omap4 = {
1338                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1339                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1340                         .modulemode   = MODULEMODE_SWCTRL,
1341                 },
1342         },
1343         .opt_clks       = mmc2_opt_clks,
1344         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1345 };
1346
1347 /* mmc3 */
1348 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1349         { .role = "clk32k", .clk = "mmc3_clk32k" },
1350 };
1351
1352 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1353         .name           = "mmc3",
1354         .class          = &dra7xx_mmc_hwmod_class,
1355         .clkdm_name     = "l4per_clkdm",
1356         .main_clk       = "mmc3_gfclk_div",
1357         .prcm = {
1358                 .omap4 = {
1359                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1360                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1361                         .modulemode   = MODULEMODE_SWCTRL,
1362                 },
1363         },
1364         .opt_clks       = mmc3_opt_clks,
1365         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1366 };
1367
1368 /* mmc4 */
1369 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1370         { .role = "clk32k", .clk = "mmc4_clk32k" },
1371 };
1372
1373 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1374         .name           = "mmc4",
1375         .class          = &dra7xx_mmc_hwmod_class,
1376         .clkdm_name     = "l4per_clkdm",
1377         .main_clk       = "mmc4_gfclk_div",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1381                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1382                         .modulemode   = MODULEMODE_SWCTRL,
1383                 },
1384         },
1385         .opt_clks       = mmc4_opt_clks,
1386         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1387 };
1388
1389 /*
1390  * 'mpu' class
1391  *
1392  */
1393
1394 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1395         .name   = "mpu",
1396 };
1397
1398 /* mpu */
1399 static struct omap_hwmod dra7xx_mpu_hwmod = {
1400         .name           = "mpu",
1401         .class          = &dra7xx_mpu_hwmod_class,
1402         .clkdm_name     = "mpu_clkdm",
1403         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1404         .main_clk       = "dpll_mpu_m2_ck",
1405         .prcm = {
1406                 .omap4 = {
1407                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1408                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1409                 },
1410         },
1411 };
1412
1413 /*
1414  * 'ocp2scp' class
1415  *
1416  */
1417
1418 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1419         .rev_offs       = 0x0000,
1420         .sysc_offs      = 0x0010,
1421         .syss_offs      = 0x0014,
1422         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1423                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1424         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1425                            SIDLE_SMART_WKUP),
1426         .sysc_fields    = &omap_hwmod_sysc_type1,
1427 };
1428
1429 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1430         .name   = "ocp2scp",
1431         .sysc   = &dra7xx_ocp2scp_sysc,
1432 };
1433
1434 /* ocp2scp1 */
1435 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1436         .name           = "ocp2scp1",
1437         .class          = &dra7xx_ocp2scp_hwmod_class,
1438         .clkdm_name     = "l3init_clkdm",
1439         .main_clk       = "l4_root_clk_div",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1443                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1444                         .modulemode   = MODULEMODE_HWCTRL,
1445                 },
1446         },
1447 };
1448
1449 /* ocp2scp3 */
1450 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1451         .name           = "ocp2scp3",
1452         .class          = &dra7xx_ocp2scp_hwmod_class,
1453         .clkdm_name     = "l3init_clkdm",
1454         .main_clk       = "l4_root_clk_div",
1455         .prcm = {
1456                 .omap4 = {
1457                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1458                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1459                         .modulemode   = MODULEMODE_HWCTRL,
1460                 },
1461         },
1462 };
1463
1464 /*
1465  * 'PCIE' class
1466  *
1467  */
1468
1469 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1470         .name   = "pcie",
1471 };
1472
1473 /* pcie1 */
1474 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1475         .name           = "pcie1",
1476         .class          = &dra7xx_pciess_hwmod_class,
1477         .clkdm_name     = "pcie_clkdm",
1478         .main_clk       = "l4_root_clk_div",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1482                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1483                         .modulemode   = MODULEMODE_SWCTRL,
1484                 },
1485         },
1486 };
1487
1488 /* pcie2 */
1489 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1490         .name           = "pcie2",
1491         .class          = &dra7xx_pciess_hwmod_class,
1492         .clkdm_name     = "pcie_clkdm",
1493         .main_clk       = "l4_root_clk_div",
1494         .prcm = {
1495                 .omap4 = {
1496                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1497                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1498                         .modulemode   = MODULEMODE_SWCTRL,
1499                 },
1500         },
1501 };
1502
1503 /*
1504  * 'qspi' class
1505  *
1506  */
1507
1508 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1509         .sysc_offs      = 0x0010,
1510         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1511         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1512                            SIDLE_SMART_WKUP),
1513         .sysc_fields    = &omap_hwmod_sysc_type2,
1514 };
1515
1516 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1517         .name   = "qspi",
1518         .sysc   = &dra7xx_qspi_sysc,
1519 };
1520
1521 /* qspi */
1522 static struct omap_hwmod dra7xx_qspi_hwmod = {
1523         .name           = "qspi",
1524         .class          = &dra7xx_qspi_hwmod_class,
1525         .clkdm_name     = "l4per2_clkdm",
1526         .main_clk       = "qspi_gfclk_div",
1527         .prcm = {
1528                 .omap4 = {
1529                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1530                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1531                         .modulemode   = MODULEMODE_SWCTRL,
1532                 },
1533         },
1534 };
1535
1536 /*
1537  * 'rtcss' class
1538  *
1539  */
1540 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1541         .sysc_offs      = 0x0078,
1542         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1544                            SIDLE_SMART_WKUP),
1545         .sysc_fields    = &omap_hwmod_sysc_type3,
1546 };
1547
1548 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1549         .name   = "rtcss",
1550         .sysc   = &dra7xx_rtcss_sysc,
1551 };
1552
1553 /* rtcss */
1554 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1555         .name           = "rtcss",
1556         .class          = &dra7xx_rtcss_hwmod_class,
1557         .clkdm_name     = "rtc_clkdm",
1558         .main_clk       = "sys_32k_ck",
1559         .prcm = {
1560                 .omap4 = {
1561                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1562                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1563                         .modulemode   = MODULEMODE_SWCTRL,
1564                 },
1565         },
1566 };
1567
1568 /*
1569  * 'sata' class
1570  *
1571  */
1572
1573 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1574         .sysc_offs      = 0x0000,
1575         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1576         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1577                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1578                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1579         .sysc_fields    = &omap_hwmod_sysc_type2,
1580 };
1581
1582 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1583         .name   = "sata",
1584         .sysc   = &dra7xx_sata_sysc,
1585 };
1586
1587 /* sata */
1588
1589 static struct omap_hwmod dra7xx_sata_hwmod = {
1590         .name           = "sata",
1591         .class          = &dra7xx_sata_hwmod_class,
1592         .clkdm_name     = "l3init_clkdm",
1593         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1594         .main_clk       = "func_48m_fclk",
1595         .mpu_rt_idx     = 1,
1596         .prcm = {
1597                 .omap4 = {
1598                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1599                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1600                         .modulemode   = MODULEMODE_SWCTRL,
1601                 },
1602         },
1603 };
1604
1605 /*
1606  * 'smartreflex' class
1607  *
1608  */
1609
1610 /* The IP is not compliant to type1 / type2 scheme */
1611 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1612         .sidle_shift    = 24,
1613         .enwkup_shift   = 26,
1614 };
1615
1616 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1617         .sysc_offs      = 0x0038,
1618         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1619         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1620                            SIDLE_SMART_WKUP),
1621         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1622 };
1623
1624 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1625         .name   = "smartreflex",
1626         .sysc   = &dra7xx_smartreflex_sysc,
1627         .rev    = 2,
1628 };
1629
1630 /* smartreflex_core */
1631 /* smartreflex_core dev_attr */
1632 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1633         .sensor_voltdm_name     = "core",
1634 };
1635
1636 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1637         .name           = "smartreflex_core",
1638         .class          = &dra7xx_smartreflex_hwmod_class,
1639         .clkdm_name     = "coreaon_clkdm",
1640         .main_clk       = "wkupaon_iclk_mux",
1641         .prcm = {
1642                 .omap4 = {
1643                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1644                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1645                         .modulemode   = MODULEMODE_SWCTRL,
1646                 },
1647         },
1648         .dev_attr       = &smartreflex_core_dev_attr,
1649 };
1650
1651 /* smartreflex_mpu */
1652 /* smartreflex_mpu dev_attr */
1653 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1654         .sensor_voltdm_name     = "mpu",
1655 };
1656
1657 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1658         .name           = "smartreflex_mpu",
1659         .class          = &dra7xx_smartreflex_hwmod_class,
1660         .clkdm_name     = "coreaon_clkdm",
1661         .main_clk       = "wkupaon_iclk_mux",
1662         .prcm = {
1663                 .omap4 = {
1664                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1665                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1666                         .modulemode   = MODULEMODE_SWCTRL,
1667                 },
1668         },
1669         .dev_attr       = &smartreflex_mpu_dev_attr,
1670 };
1671
1672 /*
1673  * 'spinlock' class
1674  *
1675  */
1676
1677 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1678         .rev_offs       = 0x0000,
1679         .sysc_offs      = 0x0010,
1680         .syss_offs      = 0x0014,
1681         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1682                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1683                            SYSS_HAS_RESET_STATUS),
1684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1685         .sysc_fields    = &omap_hwmod_sysc_type1,
1686 };
1687
1688 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1689         .name   = "spinlock",
1690         .sysc   = &dra7xx_spinlock_sysc,
1691 };
1692
1693 /* spinlock */
1694 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1695         .name           = "spinlock",
1696         .class          = &dra7xx_spinlock_hwmod_class,
1697         .clkdm_name     = "l4cfg_clkdm",
1698         .main_clk       = "l3_iclk_div",
1699         .prcm = {
1700                 .omap4 = {
1701                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1702                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1703                 },
1704         },
1705 };
1706
1707 /*
1708  * 'timer' class
1709  *
1710  * This class contains several variants: ['timer_1ms', 'timer_secure',
1711  * 'timer']
1712  */
1713
1714 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1715         .rev_offs       = 0x0000,
1716         .sysc_offs      = 0x0010,
1717         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1720                            SIDLE_SMART_WKUP),
1721         .sysc_fields    = &omap_hwmod_sysc_type2,
1722 };
1723
1724 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1725         .name   = "timer",
1726         .sysc   = &dra7xx_timer_1ms_sysc,
1727 };
1728
1729 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1730         .rev_offs       = 0x0000,
1731         .sysc_offs      = 0x0010,
1732         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1733                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1735                            SIDLE_SMART_WKUP),
1736         .sysc_fields    = &omap_hwmod_sysc_type2,
1737 };
1738
1739 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1740         .name   = "timer",
1741         .sysc   = &dra7xx_timer_secure_sysc,
1742 };
1743
1744 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1745         .rev_offs       = 0x0000,
1746         .sysc_offs      = 0x0010,
1747         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1748                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1749         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1750                            SIDLE_SMART_WKUP),
1751         .sysc_fields    = &omap_hwmod_sysc_type2,
1752 };
1753
1754 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1755         .name   = "timer",
1756         .sysc   = &dra7xx_timer_sysc,
1757 };
1758
1759 /* timer1 */
1760 static struct omap_hwmod dra7xx_timer1_hwmod = {
1761         .name           = "timer1",
1762         .class          = &dra7xx_timer_1ms_hwmod_class,
1763         .clkdm_name     = "wkupaon_clkdm",
1764         .main_clk       = "timer1_gfclk_mux",
1765         .prcm = {
1766                 .omap4 = {
1767                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1768                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1769                         .modulemode   = MODULEMODE_SWCTRL,
1770                 },
1771         },
1772 };
1773
1774 /* timer2 */
1775 static struct omap_hwmod dra7xx_timer2_hwmod = {
1776         .name           = "timer2",
1777         .class          = &dra7xx_timer_1ms_hwmod_class,
1778         .clkdm_name     = "l4per_clkdm",
1779         .main_clk       = "timer2_gfclk_mux",
1780         .prcm = {
1781                 .omap4 = {
1782                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1783                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1784                         .modulemode   = MODULEMODE_SWCTRL,
1785                 },
1786         },
1787 };
1788
1789 /* timer3 */
1790 static struct omap_hwmod dra7xx_timer3_hwmod = {
1791         .name           = "timer3",
1792         .class          = &dra7xx_timer_hwmod_class,
1793         .clkdm_name     = "l4per_clkdm",
1794         .main_clk       = "timer3_gfclk_mux",
1795         .prcm = {
1796                 .omap4 = {
1797                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1798                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1799                         .modulemode   = MODULEMODE_SWCTRL,
1800                 },
1801         },
1802 };
1803
1804 /* timer4 */
1805 static struct omap_hwmod dra7xx_timer4_hwmod = {
1806         .name           = "timer4",
1807         .class          = &dra7xx_timer_secure_hwmod_class,
1808         .clkdm_name     = "l4per_clkdm",
1809         .main_clk       = "timer4_gfclk_mux",
1810         .prcm = {
1811                 .omap4 = {
1812                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1813                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1814                         .modulemode   = MODULEMODE_SWCTRL,
1815                 },
1816         },
1817 };
1818
1819 /* timer5 */
1820 static struct omap_hwmod dra7xx_timer5_hwmod = {
1821         .name           = "timer5",
1822         .class          = &dra7xx_timer_hwmod_class,
1823         .clkdm_name     = "ipu_clkdm",
1824         .main_clk       = "timer5_gfclk_mux",
1825         .prcm = {
1826                 .omap4 = {
1827                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1828                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1829                         .modulemode   = MODULEMODE_SWCTRL,
1830                 },
1831         },
1832 };
1833
1834 /* timer6 */
1835 static struct omap_hwmod dra7xx_timer6_hwmod = {
1836         .name           = "timer6",
1837         .class          = &dra7xx_timer_hwmod_class,
1838         .clkdm_name     = "ipu_clkdm",
1839         .main_clk       = "timer6_gfclk_mux",
1840         .prcm = {
1841                 .omap4 = {
1842                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1843                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1844                         .modulemode   = MODULEMODE_SWCTRL,
1845                 },
1846         },
1847 };
1848
1849 /* timer7 */
1850 static struct omap_hwmod dra7xx_timer7_hwmod = {
1851         .name           = "timer7",
1852         .class          = &dra7xx_timer_hwmod_class,
1853         .clkdm_name     = "ipu_clkdm",
1854         .main_clk       = "timer7_gfclk_mux",
1855         .prcm = {
1856                 .omap4 = {
1857                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1858                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1859                         .modulemode   = MODULEMODE_SWCTRL,
1860                 },
1861         },
1862 };
1863
1864 /* timer8 */
1865 static struct omap_hwmod dra7xx_timer8_hwmod = {
1866         .name           = "timer8",
1867         .class          = &dra7xx_timer_hwmod_class,
1868         .clkdm_name     = "ipu_clkdm",
1869         .main_clk       = "timer8_gfclk_mux",
1870         .prcm = {
1871                 .omap4 = {
1872                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1873                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1874                         .modulemode   = MODULEMODE_SWCTRL,
1875                 },
1876         },
1877 };
1878
1879 /* timer9 */
1880 static struct omap_hwmod dra7xx_timer9_hwmod = {
1881         .name           = "timer9",
1882         .class          = &dra7xx_timer_hwmod_class,
1883         .clkdm_name     = "l4per_clkdm",
1884         .main_clk       = "timer9_gfclk_mux",
1885         .prcm = {
1886                 .omap4 = {
1887                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1888                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1889                         .modulemode   = MODULEMODE_SWCTRL,
1890                 },
1891         },
1892 };
1893
1894 /* timer10 */
1895 static struct omap_hwmod dra7xx_timer10_hwmod = {
1896         .name           = "timer10",
1897         .class          = &dra7xx_timer_1ms_hwmod_class,
1898         .clkdm_name     = "l4per_clkdm",
1899         .main_clk       = "timer10_gfclk_mux",
1900         .prcm = {
1901                 .omap4 = {
1902                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1903                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1904                         .modulemode   = MODULEMODE_SWCTRL,
1905                 },
1906         },
1907 };
1908
1909 /* timer11 */
1910 static struct omap_hwmod dra7xx_timer11_hwmod = {
1911         .name           = "timer11",
1912         .class          = &dra7xx_timer_hwmod_class,
1913         .clkdm_name     = "l4per_clkdm",
1914         .main_clk       = "timer11_gfclk_mux",
1915         .prcm = {
1916                 .omap4 = {
1917                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1918                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1919                         .modulemode   = MODULEMODE_SWCTRL,
1920                 },
1921         },
1922 };
1923
1924 /*
1925  * 'uart' class
1926  *
1927  */
1928
1929 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1930         .rev_offs       = 0x0050,
1931         .sysc_offs      = 0x0054,
1932         .syss_offs      = 0x0058,
1933         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1934                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1935                            SYSS_HAS_RESET_STATUS),
1936         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937                            SIDLE_SMART_WKUP),
1938         .sysc_fields    = &omap_hwmod_sysc_type1,
1939 };
1940
1941 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1942         .name   = "uart",
1943         .sysc   = &dra7xx_uart_sysc,
1944 };
1945
1946 /* uart1 */
1947 static struct omap_hwmod dra7xx_uart1_hwmod = {
1948         .name           = "uart1",
1949         .class          = &dra7xx_uart_hwmod_class,
1950         .clkdm_name     = "l4per_clkdm",
1951         .main_clk       = "uart1_gfclk_mux",
1952         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1953         .prcm = {
1954                 .omap4 = {
1955                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1956                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1957                         .modulemode   = MODULEMODE_SWCTRL,
1958                 },
1959         },
1960 };
1961
1962 /* uart2 */
1963 static struct omap_hwmod dra7xx_uart2_hwmod = {
1964         .name           = "uart2",
1965         .class          = &dra7xx_uart_hwmod_class,
1966         .clkdm_name     = "l4per_clkdm",
1967         .main_clk       = "uart2_gfclk_mux",
1968         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1969         .prcm = {
1970                 .omap4 = {
1971                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1972                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1973                         .modulemode   = MODULEMODE_SWCTRL,
1974                 },
1975         },
1976 };
1977
1978 /* uart3 */
1979 static struct omap_hwmod dra7xx_uart3_hwmod = {
1980         .name           = "uart3",
1981         .class          = &dra7xx_uart_hwmod_class,
1982         .clkdm_name     = "l4per_clkdm",
1983         .main_clk       = "uart3_gfclk_mux",
1984         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
1985         .prcm = {
1986                 .omap4 = {
1987                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1988                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1989                         .modulemode   = MODULEMODE_SWCTRL,
1990                 },
1991         },
1992 };
1993
1994 /* uart4 */
1995 static struct omap_hwmod dra7xx_uart4_hwmod = {
1996         .name           = "uart4",
1997         .class          = &dra7xx_uart_hwmod_class,
1998         .clkdm_name     = "l4per_clkdm",
1999         .main_clk       = "uart4_gfclk_mux",
2000         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2001         .prcm = {
2002                 .omap4 = {
2003                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2004                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2005                         .modulemode   = MODULEMODE_SWCTRL,
2006                 },
2007         },
2008 };
2009
2010 /* uart5 */
2011 static struct omap_hwmod dra7xx_uart5_hwmod = {
2012         .name           = "uart5",
2013         .class          = &dra7xx_uart_hwmod_class,
2014         .clkdm_name     = "l4per_clkdm",
2015         .main_clk       = "uart5_gfclk_mux",
2016         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2017         .prcm = {
2018                 .omap4 = {
2019                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2020                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2021                         .modulemode   = MODULEMODE_SWCTRL,
2022                 },
2023         },
2024 };
2025
2026 /* uart6 */
2027 static struct omap_hwmod dra7xx_uart6_hwmod = {
2028         .name           = "uart6",
2029         .class          = &dra7xx_uart_hwmod_class,
2030         .clkdm_name     = "ipu_clkdm",
2031         .main_clk       = "uart6_gfclk_mux",
2032         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2033         .prcm = {
2034                 .omap4 = {
2035                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2036                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2037                         .modulemode   = MODULEMODE_SWCTRL,
2038                 },
2039         },
2040 };
2041
2042 /* uart7 */
2043 static struct omap_hwmod dra7xx_uart7_hwmod = {
2044         .name           = "uart7",
2045         .class          = &dra7xx_uart_hwmod_class,
2046         .clkdm_name     = "l4per2_clkdm",
2047         .main_clk       = "uart7_gfclk_mux",
2048         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2049         .prcm = {
2050                 .omap4 = {
2051                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2052                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2053                         .modulemode   = MODULEMODE_SWCTRL,
2054                 },
2055         },
2056 };
2057
2058 /* uart8 */
2059 static struct omap_hwmod dra7xx_uart8_hwmod = {
2060         .name           = "uart8",
2061         .class          = &dra7xx_uart_hwmod_class,
2062         .clkdm_name     = "l4per2_clkdm",
2063         .main_clk       = "uart8_gfclk_mux",
2064         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2065         .prcm = {
2066                 .omap4 = {
2067                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2068                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2069                         .modulemode   = MODULEMODE_SWCTRL,
2070                 },
2071         },
2072 };
2073
2074 /* uart9 */
2075 static struct omap_hwmod dra7xx_uart9_hwmod = {
2076         .name           = "uart9",
2077         .class          = &dra7xx_uart_hwmod_class,
2078         .clkdm_name     = "l4per2_clkdm",
2079         .main_clk       = "uart9_gfclk_mux",
2080         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2084                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088 };
2089
2090 /* uart10 */
2091 static struct omap_hwmod dra7xx_uart10_hwmod = {
2092         .name           = "uart10",
2093         .class          = &dra7xx_uart_hwmod_class,
2094         .clkdm_name     = "wkupaon_clkdm",
2095         .main_clk       = "uart10_gfclk_mux",
2096         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2097         .prcm = {
2098                 .omap4 = {
2099                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2100                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2101                         .modulemode   = MODULEMODE_SWCTRL,
2102                 },
2103         },
2104 };
2105
2106 /*
2107  * 'usb_otg_ss' class
2108  *
2109  */
2110
2111 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2112         .rev_offs       = 0x0000,
2113         .sysc_offs      = 0x0010,
2114         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2115                            SYSC_HAS_SIDLEMODE),
2116         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2117                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2118                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2119         .sysc_fields    = &omap_hwmod_sysc_type2,
2120 };
2121
2122 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2123         .name   = "usb_otg_ss",
2124         .sysc   = &dra7xx_usb_otg_ss_sysc,
2125 };
2126
2127 /* usb_otg_ss1 */
2128 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2129         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2130 };
2131
2132 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2133         .name           = "usb_otg_ss1",
2134         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2135         .clkdm_name     = "l3init_clkdm",
2136         .main_clk       = "dpll_core_h13x2_ck",
2137         .prcm = {
2138                 .omap4 = {
2139                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2140                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2141                         .modulemode   = MODULEMODE_HWCTRL,
2142                 },
2143         },
2144         .opt_clks       = usb_otg_ss1_opt_clks,
2145         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2146 };
2147
2148 /* usb_otg_ss2 */
2149 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2150         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2151 };
2152
2153 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2154         .name           = "usb_otg_ss2",
2155         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2156         .clkdm_name     = "l3init_clkdm",
2157         .main_clk       = "dpll_core_h13x2_ck",
2158         .prcm = {
2159                 .omap4 = {
2160                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2161                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2162                         .modulemode   = MODULEMODE_HWCTRL,
2163                 },
2164         },
2165         .opt_clks       = usb_otg_ss2_opt_clks,
2166         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2167 };
2168
2169 /* usb_otg_ss3 */
2170 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2171         .name           = "usb_otg_ss3",
2172         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2173         .clkdm_name     = "l3init_clkdm",
2174         .main_clk       = "dpll_core_h13x2_ck",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2178                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2179                         .modulemode   = MODULEMODE_HWCTRL,
2180                 },
2181         },
2182 };
2183
2184 /* usb_otg_ss4 */
2185 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2186         .name           = "usb_otg_ss4",
2187         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2188         .clkdm_name     = "l3init_clkdm",
2189         .main_clk       = "dpll_core_h13x2_ck",
2190         .prcm = {
2191                 .omap4 = {
2192                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2193                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2194                         .modulemode   = MODULEMODE_HWCTRL,
2195                 },
2196         },
2197 };
2198
2199 /*
2200  * 'vcp' class
2201  *
2202  */
2203
2204 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2205         .name   = "vcp",
2206 };
2207
2208 /* vcp1 */
2209 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2210         .name           = "vcp1",
2211         .class          = &dra7xx_vcp_hwmod_class,
2212         .clkdm_name     = "l3main1_clkdm",
2213         .main_clk       = "l3_iclk_div",
2214         .prcm = {
2215                 .omap4 = {
2216                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2217                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2218                 },
2219         },
2220 };
2221
2222 /* vcp2 */
2223 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2224         .name           = "vcp2",
2225         .class          = &dra7xx_vcp_hwmod_class,
2226         .clkdm_name     = "l3main1_clkdm",
2227         .main_clk       = "l3_iclk_div",
2228         .prcm = {
2229                 .omap4 = {
2230                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2231                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2232                 },
2233         },
2234 };
2235
2236 /*
2237  * 'wd_timer' class
2238  *
2239  */
2240
2241 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2242         .rev_offs       = 0x0000,
2243         .sysc_offs      = 0x0010,
2244         .syss_offs      = 0x0014,
2245         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2246                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2247         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2248                            SIDLE_SMART_WKUP),
2249         .sysc_fields    = &omap_hwmod_sysc_type1,
2250 };
2251
2252 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2253         .name           = "wd_timer",
2254         .sysc           = &dra7xx_wd_timer_sysc,
2255         .pre_shutdown   = &omap2_wd_timer_disable,
2256         .reset          = &omap2_wd_timer_reset,
2257 };
2258
2259 /* wd_timer2 */
2260 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2261         .name           = "wd_timer2",
2262         .class          = &dra7xx_wd_timer_hwmod_class,
2263         .clkdm_name     = "wkupaon_clkdm",
2264         .main_clk       = "sys_32k_ck",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2268                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272 };
2273
2274
2275 /*
2276  * Interfaces
2277  */
2278
2279 /* l3_main_2 -> l3_instr */
2280 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2281         .master         = &dra7xx_l3_main_2_hwmod,
2282         .slave          = &dra7xx_l3_instr_hwmod,
2283         .clk            = "l3_iclk_div",
2284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2285 };
2286
2287 /* l4_cfg -> l3_main_1 */
2288 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2289         .master         = &dra7xx_l4_cfg_hwmod,
2290         .slave          = &dra7xx_l3_main_1_hwmod,
2291         .clk            = "l3_iclk_div",
2292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2293 };
2294
2295 /* mpu -> l3_main_1 */
2296 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2297         .master         = &dra7xx_mpu_hwmod,
2298         .slave          = &dra7xx_l3_main_1_hwmod,
2299         .clk            = "l3_iclk_div",
2300         .user           = OCP_USER_MPU,
2301 };
2302
2303 /* l3_main_1 -> l3_main_2 */
2304 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2305         .master         = &dra7xx_l3_main_1_hwmod,
2306         .slave          = &dra7xx_l3_main_2_hwmod,
2307         .clk            = "l3_iclk_div",
2308         .user           = OCP_USER_MPU,
2309 };
2310
2311 /* l4_cfg -> l3_main_2 */
2312 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2313         .master         = &dra7xx_l4_cfg_hwmod,
2314         .slave          = &dra7xx_l3_main_2_hwmod,
2315         .clk            = "l3_iclk_div",
2316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2317 };
2318
2319 /* l3_main_1 -> l4_cfg */
2320 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2321         .master         = &dra7xx_l3_main_1_hwmod,
2322         .slave          = &dra7xx_l4_cfg_hwmod,
2323         .clk            = "l3_iclk_div",
2324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2325 };
2326
2327 /* l3_main_1 -> l4_per1 */
2328 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2329         .master         = &dra7xx_l3_main_1_hwmod,
2330         .slave          = &dra7xx_l4_per1_hwmod,
2331         .clk            = "l3_iclk_div",
2332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2333 };
2334
2335 /* l3_main_1 -> l4_per2 */
2336 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2337         .master         = &dra7xx_l3_main_1_hwmod,
2338         .slave          = &dra7xx_l4_per2_hwmod,
2339         .clk            = "l3_iclk_div",
2340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2341 };
2342
2343 /* l3_main_1 -> l4_per3 */
2344 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2345         .master         = &dra7xx_l3_main_1_hwmod,
2346         .slave          = &dra7xx_l4_per3_hwmod,
2347         .clk            = "l3_iclk_div",
2348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2349 };
2350
2351 /* l3_main_1 -> l4_wkup */
2352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2353         .master         = &dra7xx_l3_main_1_hwmod,
2354         .slave          = &dra7xx_l4_wkup_hwmod,
2355         .clk            = "wkupaon_iclk_mux",
2356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2357 };
2358
2359 /* l4_per2 -> atl */
2360 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2361         .master         = &dra7xx_l4_per2_hwmod,
2362         .slave          = &dra7xx_atl_hwmod,
2363         .clk            = "l3_iclk_div",
2364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2365 };
2366
2367 /* l3_main_1 -> bb2d */
2368 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2369         .master         = &dra7xx_l3_main_1_hwmod,
2370         .slave          = &dra7xx_bb2d_hwmod,
2371         .clk            = "l3_iclk_div",
2372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2373 };
2374
2375 /* l4_wkup -> counter_32k */
2376 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2377         .master         = &dra7xx_l4_wkup_hwmod,
2378         .slave          = &dra7xx_counter_32k_hwmod,
2379         .clk            = "wkupaon_iclk_mux",
2380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2381 };
2382
2383 /* l4_wkup -> ctrl_module_wkup */
2384 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2385         .master         = &dra7xx_l4_wkup_hwmod,
2386         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2387         .clk            = "wkupaon_iclk_mux",
2388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2389 };
2390
2391 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2392         .master         = &dra7xx_l4_per2_hwmod,
2393         .slave          = &dra7xx_gmac_hwmod,
2394         .clk            = "dpll_gmac_ck",
2395         .user           = OCP_USER_MPU,
2396 };
2397
2398 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2399         .master         = &dra7xx_gmac_hwmod,
2400         .slave          = &dra7xx_mdio_hwmod,
2401         .user           = OCP_USER_MPU,
2402 };
2403
2404 /* l4_wkup -> dcan1 */
2405 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2406         .master         = &dra7xx_l4_wkup_hwmod,
2407         .slave          = &dra7xx_dcan1_hwmod,
2408         .clk            = "wkupaon_iclk_mux",
2409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* l4_per2 -> dcan2 */
2413 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2414         .master         = &dra7xx_l4_per2_hwmod,
2415         .slave          = &dra7xx_dcan2_hwmod,
2416         .clk            = "l3_iclk_div",
2417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2421         {
2422                 .pa_start       = 0x4a056000,
2423                 .pa_end         = 0x4a056fff,
2424                 .flags          = ADDR_TYPE_RT
2425         },
2426         { }
2427 };
2428
2429 /* l4_cfg -> dma_system */
2430 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2431         .master         = &dra7xx_l4_cfg_hwmod,
2432         .slave          = &dra7xx_dma_system_hwmod,
2433         .clk            = "l3_iclk_div",
2434         .addr           = dra7xx_dma_system_addrs,
2435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2436 };
2437
2438 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2439         {
2440                 .name           = "family",
2441                 .pa_start       = 0x58000000,
2442                 .pa_end         = 0x5800007f,
2443                 .flags          = ADDR_TYPE_RT
2444         },
2445 };
2446
2447 /* l3_main_1 -> dss */
2448 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2449         .master         = &dra7xx_l3_main_1_hwmod,
2450         .slave          = &dra7xx_dss_hwmod,
2451         .clk            = "l3_iclk_div",
2452         .addr           = dra7xx_dss_addrs,
2453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2454 };
2455
2456 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2457         {
2458                 .name           = "dispc",
2459                 .pa_start       = 0x58001000,
2460                 .pa_end         = 0x58001fff,
2461                 .flags          = ADDR_TYPE_RT
2462         },
2463 };
2464
2465 /* l3_main_1 -> dispc */
2466 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2467         .master         = &dra7xx_l3_main_1_hwmod,
2468         .slave          = &dra7xx_dss_dispc_hwmod,
2469         .clk            = "l3_iclk_div",
2470         .addr           = dra7xx_dss_dispc_addrs,
2471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2472 };
2473
2474 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2475         {
2476                 .name           = "hdmi_wp",
2477                 .pa_start       = 0x58040000,
2478                 .pa_end         = 0x580400ff,
2479                 .flags          = ADDR_TYPE_RT
2480         },
2481         { }
2482 };
2483
2484 /* l3_main_1 -> dispc */
2485 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2486         .master         = &dra7xx_l3_main_1_hwmod,
2487         .slave          = &dra7xx_dss_hdmi_hwmod,
2488         .clk            = "l3_iclk_div",
2489         .addr           = dra7xx_dss_hdmi_addrs,
2490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2491 };
2492
2493 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2494         {
2495                 .pa_start       = 0x48078000,
2496                 .pa_end         = 0x48078fff,
2497                 .flags          = ADDR_TYPE_RT
2498         },
2499         { }
2500 };
2501
2502 /* l4_per1 -> elm */
2503 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2504         .master         = &dra7xx_l4_per1_hwmod,
2505         .slave          = &dra7xx_elm_hwmod,
2506         .clk            = "l3_iclk_div",
2507         .addr           = dra7xx_elm_addrs,
2508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 /* l4_wkup -> gpio1 */
2512 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2513         .master         = &dra7xx_l4_wkup_hwmod,
2514         .slave          = &dra7xx_gpio1_hwmod,
2515         .clk            = "wkupaon_iclk_mux",
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* l4_per1 -> gpio2 */
2520 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2521         .master         = &dra7xx_l4_per1_hwmod,
2522         .slave          = &dra7xx_gpio2_hwmod,
2523         .clk            = "l3_iclk_div",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* l4_per1 -> gpio3 */
2528 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2529         .master         = &dra7xx_l4_per1_hwmod,
2530         .slave          = &dra7xx_gpio3_hwmod,
2531         .clk            = "l3_iclk_div",
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 /* l4_per1 -> gpio4 */
2536 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2537         .master         = &dra7xx_l4_per1_hwmod,
2538         .slave          = &dra7xx_gpio4_hwmod,
2539         .clk            = "l3_iclk_div",
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 /* l4_per1 -> gpio5 */
2544 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2545         .master         = &dra7xx_l4_per1_hwmod,
2546         .slave          = &dra7xx_gpio5_hwmod,
2547         .clk            = "l3_iclk_div",
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 /* l4_per1 -> gpio6 */
2552 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2553         .master         = &dra7xx_l4_per1_hwmod,
2554         .slave          = &dra7xx_gpio6_hwmod,
2555         .clk            = "l3_iclk_div",
2556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2557 };
2558
2559 /* l4_per1 -> gpio7 */
2560 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2561         .master         = &dra7xx_l4_per1_hwmod,
2562         .slave          = &dra7xx_gpio7_hwmod,
2563         .clk            = "l3_iclk_div",
2564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2565 };
2566
2567 /* l4_per1 -> gpio8 */
2568 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2569         .master         = &dra7xx_l4_per1_hwmod,
2570         .slave          = &dra7xx_gpio8_hwmod,
2571         .clk            = "l3_iclk_div",
2572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2573 };
2574
2575 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2576         {
2577                 .pa_start       = 0x50000000,
2578                 .pa_end         = 0x500003ff,
2579                 .flags          = ADDR_TYPE_RT
2580         },
2581         { }
2582 };
2583
2584 /* l3_main_1 -> gpmc */
2585 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2586         .master         = &dra7xx_l3_main_1_hwmod,
2587         .slave          = &dra7xx_gpmc_hwmod,
2588         .clk            = "l3_iclk_div",
2589         .addr           = dra7xx_gpmc_addrs,
2590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2591 };
2592
2593 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2594         {
2595                 .pa_start       = 0x480b2000,
2596                 .pa_end         = 0x480b201f,
2597                 .flags          = ADDR_TYPE_RT
2598         },
2599         { }
2600 };
2601
2602 /* l4_per1 -> hdq1w */
2603 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2604         .master         = &dra7xx_l4_per1_hwmod,
2605         .slave          = &dra7xx_hdq1w_hwmod,
2606         .clk            = "l3_iclk_div",
2607         .addr           = dra7xx_hdq1w_addrs,
2608         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2609 };
2610
2611 /* l4_per1 -> i2c1 */
2612 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2613         .master         = &dra7xx_l4_per1_hwmod,
2614         .slave          = &dra7xx_i2c1_hwmod,
2615         .clk            = "l3_iclk_div",
2616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2617 };
2618
2619 /* l4_per1 -> i2c2 */
2620 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2621         .master         = &dra7xx_l4_per1_hwmod,
2622         .slave          = &dra7xx_i2c2_hwmod,
2623         .clk            = "l3_iclk_div",
2624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2625 };
2626
2627 /* l4_per1 -> i2c3 */
2628 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2629         .master         = &dra7xx_l4_per1_hwmod,
2630         .slave          = &dra7xx_i2c3_hwmod,
2631         .clk            = "l3_iclk_div",
2632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2633 };
2634
2635 /* l4_per1 -> i2c4 */
2636 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2637         .master         = &dra7xx_l4_per1_hwmod,
2638         .slave          = &dra7xx_i2c4_hwmod,
2639         .clk            = "l3_iclk_div",
2640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642
2643 /* l4_per1 -> i2c5 */
2644 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2645         .master         = &dra7xx_l4_per1_hwmod,
2646         .slave          = &dra7xx_i2c5_hwmod,
2647         .clk            = "l3_iclk_div",
2648         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2649 };
2650
2651 /* l4_cfg -> mailbox1 */
2652 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2653         .master         = &dra7xx_l4_cfg_hwmod,
2654         .slave          = &dra7xx_mailbox1_hwmod,
2655         .clk            = "l3_iclk_div",
2656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2657 };
2658
2659 /* l4_per3 -> mailbox2 */
2660 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2661         .master         = &dra7xx_l4_per3_hwmod,
2662         .slave          = &dra7xx_mailbox2_hwmod,
2663         .clk            = "l3_iclk_div",
2664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2665 };
2666
2667 /* l4_per3 -> mailbox3 */
2668 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2669         .master         = &dra7xx_l4_per3_hwmod,
2670         .slave          = &dra7xx_mailbox3_hwmod,
2671         .clk            = "l3_iclk_div",
2672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2673 };
2674
2675 /* l4_per3 -> mailbox4 */
2676 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2677         .master         = &dra7xx_l4_per3_hwmod,
2678         .slave          = &dra7xx_mailbox4_hwmod,
2679         .clk            = "l3_iclk_div",
2680         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2681 };
2682
2683 /* l4_per3 -> mailbox5 */
2684 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2685         .master         = &dra7xx_l4_per3_hwmod,
2686         .slave          = &dra7xx_mailbox5_hwmod,
2687         .clk            = "l3_iclk_div",
2688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2689 };
2690
2691 /* l4_per3 -> mailbox6 */
2692 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2693         .master         = &dra7xx_l4_per3_hwmod,
2694         .slave          = &dra7xx_mailbox6_hwmod,
2695         .clk            = "l3_iclk_div",
2696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2697 };
2698
2699 /* l4_per3 -> mailbox7 */
2700 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2701         .master         = &dra7xx_l4_per3_hwmod,
2702         .slave          = &dra7xx_mailbox7_hwmod,
2703         .clk            = "l3_iclk_div",
2704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2705 };
2706
2707 /* l4_per3 -> mailbox8 */
2708 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2709         .master         = &dra7xx_l4_per3_hwmod,
2710         .slave          = &dra7xx_mailbox8_hwmod,
2711         .clk            = "l3_iclk_div",
2712         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2713 };
2714
2715 /* l4_per3 -> mailbox9 */
2716 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2717         .master         = &dra7xx_l4_per3_hwmod,
2718         .slave          = &dra7xx_mailbox9_hwmod,
2719         .clk            = "l3_iclk_div",
2720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2721 };
2722
2723 /* l4_per3 -> mailbox10 */
2724 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2725         .master         = &dra7xx_l4_per3_hwmod,
2726         .slave          = &dra7xx_mailbox10_hwmod,
2727         .clk            = "l3_iclk_div",
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 /* l4_per3 -> mailbox11 */
2732 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2733         .master         = &dra7xx_l4_per3_hwmod,
2734         .slave          = &dra7xx_mailbox11_hwmod,
2735         .clk            = "l3_iclk_div",
2736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2737 };
2738
2739 /* l4_per3 -> mailbox12 */
2740 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2741         .master         = &dra7xx_l4_per3_hwmod,
2742         .slave          = &dra7xx_mailbox12_hwmod,
2743         .clk            = "l3_iclk_div",
2744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2745 };
2746
2747 /* l4_per3 -> mailbox13 */
2748 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2749         .master         = &dra7xx_l4_per3_hwmod,
2750         .slave          = &dra7xx_mailbox13_hwmod,
2751         .clk            = "l3_iclk_div",
2752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2753 };
2754
2755 /* l4_per1 -> mcspi1 */
2756 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2757         .master         = &dra7xx_l4_per1_hwmod,
2758         .slave          = &dra7xx_mcspi1_hwmod,
2759         .clk            = "l3_iclk_div",
2760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2761 };
2762
2763 /* l4_per1 -> mcspi2 */
2764 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2765         .master         = &dra7xx_l4_per1_hwmod,
2766         .slave          = &dra7xx_mcspi2_hwmod,
2767         .clk            = "l3_iclk_div",
2768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 /* l4_per1 -> mcspi3 */
2772 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2773         .master         = &dra7xx_l4_per1_hwmod,
2774         .slave          = &dra7xx_mcspi3_hwmod,
2775         .clk            = "l3_iclk_div",
2776         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2777 };
2778
2779 /* l4_per1 -> mcspi4 */
2780 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2781         .master         = &dra7xx_l4_per1_hwmod,
2782         .slave          = &dra7xx_mcspi4_hwmod,
2783         .clk            = "l3_iclk_div",
2784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2785 };
2786
2787 /* l4_per1 -> mmc1 */
2788 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2789         .master         = &dra7xx_l4_per1_hwmod,
2790         .slave          = &dra7xx_mmc1_hwmod,
2791         .clk            = "l3_iclk_div",
2792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2793 };
2794
2795 /* l4_per1 -> mmc2 */
2796 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2797         .master         = &dra7xx_l4_per1_hwmod,
2798         .slave          = &dra7xx_mmc2_hwmod,
2799         .clk            = "l3_iclk_div",
2800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2802
2803 /* l4_per1 -> mmc3 */
2804 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2805         .master         = &dra7xx_l4_per1_hwmod,
2806         .slave          = &dra7xx_mmc3_hwmod,
2807         .clk            = "l3_iclk_div",
2808         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2809 };
2810
2811 /* l4_per1 -> mmc4 */
2812 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2813         .master         = &dra7xx_l4_per1_hwmod,
2814         .slave          = &dra7xx_mmc4_hwmod,
2815         .clk            = "l3_iclk_div",
2816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2817 };
2818
2819 /* l4_cfg -> mpu */
2820 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2821         .master         = &dra7xx_l4_cfg_hwmod,
2822         .slave          = &dra7xx_mpu_hwmod,
2823         .clk            = "l3_iclk_div",
2824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2825 };
2826
2827 /* l4_cfg -> ocp2scp1 */
2828 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2829         .master         = &dra7xx_l4_cfg_hwmod,
2830         .slave          = &dra7xx_ocp2scp1_hwmod,
2831         .clk            = "l4_root_clk_div",
2832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* l4_cfg -> ocp2scp3 */
2836 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2837         .master         = &dra7xx_l4_cfg_hwmod,
2838         .slave          = &dra7xx_ocp2scp3_hwmod,
2839         .clk            = "l4_root_clk_div",
2840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2841 };
2842
2843 /* l3_main_1 -> pciess1 */
2844 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2845         .master         = &dra7xx_l3_main_1_hwmod,
2846         .slave          = &dra7xx_pciess1_hwmod,
2847         .clk            = "l3_iclk_div",
2848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2849 };
2850
2851 /* l4_cfg -> pciess1 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2853         .master         = &dra7xx_l4_cfg_hwmod,
2854         .slave          = &dra7xx_pciess1_hwmod,
2855         .clk            = "l4_root_clk_div",
2856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2857 };
2858
2859 /* l3_main_1 -> pciess2 */
2860 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2861         .master         = &dra7xx_l3_main_1_hwmod,
2862         .slave          = &dra7xx_pciess2_hwmod,
2863         .clk            = "l3_iclk_div",
2864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2865 };
2866
2867 /* l4_cfg -> pciess2 */
2868 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2869         .master         = &dra7xx_l4_cfg_hwmod,
2870         .slave          = &dra7xx_pciess2_hwmod,
2871         .clk            = "l4_root_clk_div",
2872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2873 };
2874
2875 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2876         {
2877                 .pa_start       = 0x4b300000,
2878                 .pa_end         = 0x4b30007f,
2879                 .flags          = ADDR_TYPE_RT
2880         },
2881         { }
2882 };
2883
2884 /* l3_main_1 -> qspi */
2885 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2886         .master         = &dra7xx_l3_main_1_hwmod,
2887         .slave          = &dra7xx_qspi_hwmod,
2888         .clk            = "l3_iclk_div",
2889         .addr           = dra7xx_qspi_addrs,
2890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2891 };
2892
2893 /* l4_per3 -> rtcss */
2894 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2895         .master         = &dra7xx_l4_per3_hwmod,
2896         .slave          = &dra7xx_rtcss_hwmod,
2897         .clk            = "l4_root_clk_div",
2898         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2899 };
2900
2901 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2902         {
2903                 .name           = "sysc",
2904                 .pa_start       = 0x4a141100,
2905                 .pa_end         = 0x4a141107,
2906                 .flags          = ADDR_TYPE_RT
2907         },
2908         { }
2909 };
2910
2911 /* l4_cfg -> sata */
2912 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2913         .master         = &dra7xx_l4_cfg_hwmod,
2914         .slave          = &dra7xx_sata_hwmod,
2915         .clk            = "l3_iclk_div",
2916         .addr           = dra7xx_sata_addrs,
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2921         {
2922                 .pa_start       = 0x4a0dd000,
2923                 .pa_end         = 0x4a0dd07f,
2924                 .flags          = ADDR_TYPE_RT
2925         },
2926         { }
2927 };
2928
2929 /* l4_cfg -> smartreflex_core */
2930 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2931         .master         = &dra7xx_l4_cfg_hwmod,
2932         .slave          = &dra7xx_smartreflex_core_hwmod,
2933         .clk            = "l4_root_clk_div",
2934         .addr           = dra7xx_smartreflex_core_addrs,
2935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2936 };
2937
2938 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2939         {
2940                 .pa_start       = 0x4a0d9000,
2941                 .pa_end         = 0x4a0d907f,
2942                 .flags          = ADDR_TYPE_RT
2943         },
2944         { }
2945 };
2946
2947 /* l4_cfg -> smartreflex_mpu */
2948 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2949         .master         = &dra7xx_l4_cfg_hwmod,
2950         .slave          = &dra7xx_smartreflex_mpu_hwmod,
2951         .clk            = "l4_root_clk_div",
2952         .addr           = dra7xx_smartreflex_mpu_addrs,
2953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2954 };
2955
2956 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2957         {
2958                 .pa_start       = 0x4a0f6000,
2959                 .pa_end         = 0x4a0f6fff,
2960                 .flags          = ADDR_TYPE_RT
2961         },
2962         { }
2963 };
2964
2965 /* l4_cfg -> spinlock */
2966 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2967         .master         = &dra7xx_l4_cfg_hwmod,
2968         .slave          = &dra7xx_spinlock_hwmod,
2969         .clk            = "l3_iclk_div",
2970         .addr           = dra7xx_spinlock_addrs,
2971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2972 };
2973
2974 /* l4_wkup -> timer1 */
2975 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2976         .master         = &dra7xx_l4_wkup_hwmod,
2977         .slave          = &dra7xx_timer1_hwmod,
2978         .clk            = "wkupaon_iclk_mux",
2979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2980 };
2981
2982 /* l4_per1 -> timer2 */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2984         .master         = &dra7xx_l4_per1_hwmod,
2985         .slave          = &dra7xx_timer2_hwmod,
2986         .clk            = "l3_iclk_div",
2987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2988 };
2989
2990 /* l4_per1 -> timer3 */
2991 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2992         .master         = &dra7xx_l4_per1_hwmod,
2993         .slave          = &dra7xx_timer3_hwmod,
2994         .clk            = "l3_iclk_div",
2995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2996 };
2997
2998 /* l4_per1 -> timer4 */
2999 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3000         .master         = &dra7xx_l4_per1_hwmod,
3001         .slave          = &dra7xx_timer4_hwmod,
3002         .clk            = "l3_iclk_div",
3003         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3004 };
3005
3006 /* l4_per3 -> timer5 */
3007 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3008         .master         = &dra7xx_l4_per3_hwmod,
3009         .slave          = &dra7xx_timer5_hwmod,
3010         .clk            = "l3_iclk_div",
3011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3012 };
3013
3014 /* l4_per3 -> timer6 */
3015 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3016         .master         = &dra7xx_l4_per3_hwmod,
3017         .slave          = &dra7xx_timer6_hwmod,
3018         .clk            = "l3_iclk_div",
3019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3020 };
3021
3022 /* l4_per3 -> timer7 */
3023 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3024         .master         = &dra7xx_l4_per3_hwmod,
3025         .slave          = &dra7xx_timer7_hwmod,
3026         .clk            = "l3_iclk_div",
3027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3028 };
3029
3030 /* l4_per3 -> timer8 */
3031 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3032         .master         = &dra7xx_l4_per3_hwmod,
3033         .slave          = &dra7xx_timer8_hwmod,
3034         .clk            = "l3_iclk_div",
3035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3036 };
3037
3038 /* l4_per1 -> timer9 */
3039 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3040         .master         = &dra7xx_l4_per1_hwmod,
3041         .slave          = &dra7xx_timer9_hwmod,
3042         .clk            = "l3_iclk_div",
3043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3044 };
3045
3046 /* l4_per1 -> timer10 */
3047 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3048         .master         = &dra7xx_l4_per1_hwmod,
3049         .slave          = &dra7xx_timer10_hwmod,
3050         .clk            = "l3_iclk_div",
3051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 /* l4_per1 -> timer11 */
3055 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3056         .master         = &dra7xx_l4_per1_hwmod,
3057         .slave          = &dra7xx_timer11_hwmod,
3058         .clk            = "l3_iclk_div",
3059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061
3062 /* l4_per1 -> uart1 */
3063 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3064         .master         = &dra7xx_l4_per1_hwmod,
3065         .slave          = &dra7xx_uart1_hwmod,
3066         .clk            = "l3_iclk_div",
3067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3068 };
3069
3070 /* l4_per1 -> uart2 */
3071 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3072         .master         = &dra7xx_l4_per1_hwmod,
3073         .slave          = &dra7xx_uart2_hwmod,
3074         .clk            = "l3_iclk_div",
3075         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3076 };
3077
3078 /* l4_per1 -> uart3 */
3079 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3080         .master         = &dra7xx_l4_per1_hwmod,
3081         .slave          = &dra7xx_uart3_hwmod,
3082         .clk            = "l3_iclk_div",
3083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3084 };
3085
3086 /* l4_per1 -> uart4 */
3087 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3088         .master         = &dra7xx_l4_per1_hwmod,
3089         .slave          = &dra7xx_uart4_hwmod,
3090         .clk            = "l3_iclk_div",
3091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3092 };
3093
3094 /* l4_per1 -> uart5 */
3095 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3096         .master         = &dra7xx_l4_per1_hwmod,
3097         .slave          = &dra7xx_uart5_hwmod,
3098         .clk            = "l3_iclk_div",
3099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3100 };
3101
3102 /* l4_per1 -> uart6 */
3103 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3104         .master         = &dra7xx_l4_per1_hwmod,
3105         .slave          = &dra7xx_uart6_hwmod,
3106         .clk            = "l3_iclk_div",
3107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3108 };
3109
3110 /* l4_per2 -> uart7 */
3111 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3112         .master         = &dra7xx_l4_per2_hwmod,
3113         .slave          = &dra7xx_uart7_hwmod,
3114         .clk            = "l3_iclk_div",
3115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3116 };
3117
3118 /* l4_per2 -> uart8 */
3119 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3120         .master         = &dra7xx_l4_per2_hwmod,
3121         .slave          = &dra7xx_uart8_hwmod,
3122         .clk            = "l3_iclk_div",
3123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 /* l4_per2 -> uart9 */
3127 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3128         .master         = &dra7xx_l4_per2_hwmod,
3129         .slave          = &dra7xx_uart9_hwmod,
3130         .clk            = "l3_iclk_div",
3131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3132 };
3133
3134 /* l4_wkup -> uart10 */
3135 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3136         .master         = &dra7xx_l4_wkup_hwmod,
3137         .slave          = &dra7xx_uart10_hwmod,
3138         .clk            = "wkupaon_iclk_mux",
3139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3140 };
3141
3142 /* l4_per3 -> usb_otg_ss1 */
3143 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3144         .master         = &dra7xx_l4_per3_hwmod,
3145         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3146         .clk            = "dpll_core_h13x2_ck",
3147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3148 };
3149
3150 /* l4_per3 -> usb_otg_ss2 */
3151 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3152         .master         = &dra7xx_l4_per3_hwmod,
3153         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3154         .clk            = "dpll_core_h13x2_ck",
3155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3156 };
3157
3158 /* l4_per3 -> usb_otg_ss3 */
3159 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3160         .master         = &dra7xx_l4_per3_hwmod,
3161         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3162         .clk            = "dpll_core_h13x2_ck",
3163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3164 };
3165
3166 /* l4_per3 -> usb_otg_ss4 */
3167 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3168         .master         = &dra7xx_l4_per3_hwmod,
3169         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3170         .clk            = "dpll_core_h13x2_ck",
3171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3172 };
3173
3174 /* l3_main_1 -> vcp1 */
3175 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3176         .master         = &dra7xx_l3_main_1_hwmod,
3177         .slave          = &dra7xx_vcp1_hwmod,
3178         .clk            = "l3_iclk_div",
3179         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3180 };
3181
3182 /* l4_per2 -> vcp1 */
3183 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3184         .master         = &dra7xx_l4_per2_hwmod,
3185         .slave          = &dra7xx_vcp1_hwmod,
3186         .clk            = "l3_iclk_div",
3187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3188 };
3189
3190 /* l3_main_1 -> vcp2 */
3191 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3192         .master         = &dra7xx_l3_main_1_hwmod,
3193         .slave          = &dra7xx_vcp2_hwmod,
3194         .clk            = "l3_iclk_div",
3195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3196 };
3197
3198 /* l4_per2 -> vcp2 */
3199 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3200         .master         = &dra7xx_l4_per2_hwmod,
3201         .slave          = &dra7xx_vcp2_hwmod,
3202         .clk            = "l3_iclk_div",
3203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3204 };
3205
3206 /* l4_wkup -> wd_timer2 */
3207 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3208         .master         = &dra7xx_l4_wkup_hwmod,
3209         .slave          = &dra7xx_wd_timer2_hwmod,
3210         .clk            = "wkupaon_iclk_mux",
3211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3212 };
3213
3214 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3215         &dra7xx_l3_main_2__l3_instr,
3216         &dra7xx_l4_cfg__l3_main_1,
3217         &dra7xx_mpu__l3_main_1,
3218         &dra7xx_l3_main_1__l3_main_2,
3219         &dra7xx_l4_cfg__l3_main_2,
3220         &dra7xx_l3_main_1__l4_cfg,
3221         &dra7xx_l3_main_1__l4_per1,
3222         &dra7xx_l3_main_1__l4_per2,
3223         &dra7xx_l3_main_1__l4_per3,
3224         &dra7xx_l3_main_1__l4_wkup,
3225         &dra7xx_l4_per2__atl,
3226         &dra7xx_l3_main_1__bb2d,
3227         &dra7xx_l4_wkup__counter_32k,
3228         &dra7xx_l4_wkup__ctrl_module_wkup,
3229         &dra7xx_l4_wkup__dcan1,
3230         &dra7xx_l4_per2__dcan2,
3231         &dra7xx_l4_per2__cpgmac0,
3232         &dra7xx_gmac__mdio,
3233         &dra7xx_l4_cfg__dma_system,
3234         &dra7xx_l3_main_1__dss,
3235         &dra7xx_l3_main_1__dispc,
3236         &dra7xx_l3_main_1__hdmi,
3237         &dra7xx_l4_per1__elm,
3238         &dra7xx_l4_wkup__gpio1,
3239         &dra7xx_l4_per1__gpio2,
3240         &dra7xx_l4_per1__gpio3,
3241         &dra7xx_l4_per1__gpio4,
3242         &dra7xx_l4_per1__gpio5,
3243         &dra7xx_l4_per1__gpio6,
3244         &dra7xx_l4_per1__gpio7,
3245         &dra7xx_l4_per1__gpio8,
3246         &dra7xx_l3_main_1__gpmc,
3247         &dra7xx_l4_per1__hdq1w,
3248         &dra7xx_l4_per1__i2c1,
3249         &dra7xx_l4_per1__i2c2,
3250         &dra7xx_l4_per1__i2c3,
3251         &dra7xx_l4_per1__i2c4,
3252         &dra7xx_l4_per1__i2c5,
3253         &dra7xx_l4_cfg__mailbox1,
3254         &dra7xx_l4_per3__mailbox2,
3255         &dra7xx_l4_per3__mailbox3,
3256         &dra7xx_l4_per3__mailbox4,
3257         &dra7xx_l4_per3__mailbox5,
3258         &dra7xx_l4_per3__mailbox6,
3259         &dra7xx_l4_per3__mailbox7,
3260         &dra7xx_l4_per3__mailbox8,
3261         &dra7xx_l4_per3__mailbox9,
3262         &dra7xx_l4_per3__mailbox10,
3263         &dra7xx_l4_per3__mailbox11,
3264         &dra7xx_l4_per3__mailbox12,
3265         &dra7xx_l4_per3__mailbox13,
3266         &dra7xx_l4_per1__mcspi1,
3267         &dra7xx_l4_per1__mcspi2,
3268         &dra7xx_l4_per1__mcspi3,
3269         &dra7xx_l4_per1__mcspi4,
3270         &dra7xx_l4_per1__mmc1,
3271         &dra7xx_l4_per1__mmc2,
3272         &dra7xx_l4_per1__mmc3,
3273         &dra7xx_l4_per1__mmc4,
3274         &dra7xx_l4_cfg__mpu,
3275         &dra7xx_l4_cfg__ocp2scp1,
3276         &dra7xx_l4_cfg__ocp2scp3,
3277         &dra7xx_l3_main_1__pciess1,
3278         &dra7xx_l4_cfg__pciess1,
3279         &dra7xx_l3_main_1__pciess2,
3280         &dra7xx_l4_cfg__pciess2,
3281         &dra7xx_l3_main_1__qspi,
3282         &dra7xx_l4_per3__rtcss,
3283         &dra7xx_l4_cfg__sata,
3284         &dra7xx_l4_cfg__smartreflex_core,
3285         &dra7xx_l4_cfg__smartreflex_mpu,
3286         &dra7xx_l4_cfg__spinlock,
3287         &dra7xx_l4_wkup__timer1,
3288         &dra7xx_l4_per1__timer2,
3289         &dra7xx_l4_per1__timer3,
3290         &dra7xx_l4_per1__timer4,
3291         &dra7xx_l4_per3__timer5,
3292         &dra7xx_l4_per3__timer6,
3293         &dra7xx_l4_per3__timer7,
3294         &dra7xx_l4_per3__timer8,
3295         &dra7xx_l4_per1__timer9,
3296         &dra7xx_l4_per1__timer10,
3297         &dra7xx_l4_per1__timer11,
3298         &dra7xx_l4_per1__uart1,
3299         &dra7xx_l4_per1__uart2,
3300         &dra7xx_l4_per1__uart3,
3301         &dra7xx_l4_per1__uart4,
3302         &dra7xx_l4_per1__uart5,
3303         &dra7xx_l4_per1__uart6,
3304         &dra7xx_l4_per2__uart7,
3305         &dra7xx_l4_per2__uart8,
3306         &dra7xx_l4_per2__uart9,
3307         &dra7xx_l4_wkup__uart10,
3308         &dra7xx_l4_per3__usb_otg_ss1,
3309         &dra7xx_l4_per3__usb_otg_ss2,
3310         &dra7xx_l4_per3__usb_otg_ss3,
3311         &dra7xx_l3_main_1__vcp1,
3312         &dra7xx_l4_per2__vcp1,
3313         &dra7xx_l3_main_1__vcp2,
3314         &dra7xx_l4_per2__vcp2,
3315         &dra7xx_l4_wkup__wd_timer2,
3316         NULL,
3317 };
3318
3319 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3320         &dra7xx_l4_per3__usb_otg_ss4,
3321         NULL,
3322 };
3323
3324 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3325         NULL,
3326 };
3327
3328 int __init dra7xx_hwmod_init(void)
3329 {
3330         int ret;
3331
3332         omap_hwmod_init();
3333         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3334
3335         if (!ret && soc_is_dra74x())
3336                 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3337         else if (!ret && soc_is_dra72x())
3338                 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3339
3340         return ret;
3341 }