arch/arm/mach-omap2/sram.c

   1 /*
   2  *
   3  * OMAP SRAM detection and management
   4  *
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Written by Tony Lindgren <tony@atomide.com>
   7  *
   8  * Copyright (C) 2009-2012 Texas Instruments
   9  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/fncpy.h>
  22 #include <asm/tlb.h>
  23 #include <asm/cacheflush.h>
  24
  25 #include <asm/mach/map.h>
  26
  27 #include "soc.h"
  28 #include "iomap.h"
  29 #include "prm2xxx_3xxx.h"
  30 #include "sdrc.h"
  31 #include "sram.h"
  32
  33 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  34 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  35
  36 #define SRAM_BOOTLOADER_SZ      0x00
  37
  38 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  39 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  40 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  41
  42 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  43 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  44 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  45 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  46 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  47
  48 #define GP_DEVICE               0x300
  49
  50 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  51
  52 static unsigned long omap_sram_start;
  53 static unsigned long omap_sram_skip;
  54 static unsigned long omap_sram_size;
  55
  56 /*
  57  * Depending on the target RAMFS firewall setup, the public usable amount of
  58  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  59  * device allows ARM11 but not other initiators for full size. This
  60  * functionality seems ok until some nice security API happens.
  61  */
  62 static int is_sram_locked(void)
  63 {
  64         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  65                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  66                 if (cpu_is_omap242x()) {
  67                         writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  68                         writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  69                         writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  70                 }
  71                 if (cpu_is_omap34xx()) {
  72                         writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  73                         writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  74                         writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  75                         writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
  76                         writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  77                 }
  78                 return 0;
  79         } else
  80                 return 1; /* assume locked with no PPA or security driver */
  81 }
  82
  83 /*
  84  * The amount of SRAM depends on the core type.
  85  * Note that we cannot try to test for SRAM here because writes
  86  * to secure SRAM will hang the system. Also the SRAM is not
  87  * yet mapped at this point.
  88  */
  89 static void __init omap_detect_sram(void)
  90 {
  91         omap_sram_skip = SRAM_BOOTLOADER_SZ;
  92         if (is_sram_locked()) {
  93                 if (cpu_is_omap34xx()) {
  94                         omap_sram_start = OMAP3_SRAM_PUB_PA;
  95                         if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
  96                             (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
  97                                 omap_sram_size = 0x7000; /* 28K */
  98                                 omap_sram_skip += SZ_16K;
  99                         } else {
 100                                 omap_sram_size = 0x8000; /* 32K */
 101                         }
 102                 } else {
 103                         omap_sram_start = OMAP2_SRAM_PUB_PA;
 104                         omap_sram_size = 0x800; /* 2K */
 105                 }
 106         } else {
 107                 if (cpu_is_omap34xx()) {
 108                         omap_sram_start = OMAP3_SRAM_PA;
 109                         omap_sram_size = 0x10000; /* 64K */
 110                 } else {
 111                         omap_sram_start = OMAP2_SRAM_PA;
 112                         if (cpu_is_omap242x())
 113                                 omap_sram_size = 0xa0000; /* 640K */
 114                         else if (cpu_is_omap243x())
 115                                 omap_sram_size = 0x10000; /* 64K */
 116                 }
 117         }
 118 }
 119
 120 /*
 121  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 122  */
 123 static void __init omap2_map_sram(void)
 124 {
 125         int cached = 1;
 126
 127 #ifdef CONFIG_OMAP4_ERRATA_I688
 128         if (cpu_is_omap44xx()) {
 129                 omap_sram_start += PAGE_SIZE;
 130                 omap_sram_size -= SZ_16K;
 131         }
 132 #endif
 133         if (cpu_is_omap34xx()) {
 134                 /*
 135                  * SRAM must be marked as non-cached on OMAP3 since the
 136                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 137                  * SDRAM controller disabled, and if it is marked cached,
 138                  * the ARM may attempt to write cache lines back to SDRAM
 139                  * which will cause the system to hang.
 140                  */
 141                 cached = 0;
 142         }
 143
 144         omap_map_sram(omap_sram_start, omap_sram_size,
 145                         omap_sram_skip, cached);
 146 }
 147
 148 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 149                               u32 base_cs, u32 force_unlock);
 150
 151 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 152                    u32 base_cs, u32 force_unlock)
 153 {
 154         BUG_ON(!_omap2_sram_ddr_init);
 155         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 156                              base_cs, force_unlock);
 157 }
 158
 159 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 160                                           u32 mem_type);
 161
 162 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 163 {
 164         BUG_ON(!_omap2_sram_reprogram_sdrc);
 165         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 166 }
 167
 168 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 169
 170 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 171 {
 172         BUG_ON(!_omap2_set_prcm);
 173         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 174 }
 175
 176 #ifdef CONFIG_SOC_OMAP2420
 177 static int __init omap242x_sram_init(void)
 178 {
 179         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 180                                         omap242x_sram_ddr_init_sz);
 181
 182         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 183                                             omap242x_sram_reprogram_sdrc_sz);
 184
 185         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 186                                          omap242x_sram_set_prcm_sz);
 187
 188         return 0;
 189 }
 190 #else
 191 static inline int omap242x_sram_init(void)
 192 {
 193         return 0;
 194 }
 195 #endif
 196
 197 #ifdef CONFIG_SOC_OMAP2430
 198 static int __init omap243x_sram_init(void)
 199 {
 200         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 201                                         omap243x_sram_ddr_init_sz);
 202
 203         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 204                                             omap243x_sram_reprogram_sdrc_sz);
 205
 206         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 207                                          omap243x_sram_set_prcm_sz);
 208
 209         return 0;
 210 }
 211 #else
 212 static inline int omap243x_sram_init(void)
 213 {
 214         return 0;
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_ARCH_OMAP3
 219
 220 static u32 (*_omap3_sram_configure_core_dpll)(
 221                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 222                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 223                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 224                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 225                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 226
 227 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 228                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 229                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 230                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 231                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 232 {
 233         BUG_ON(!_omap3_sram_configure_core_dpll);
 234         return _omap3_sram_configure_core_dpll(
 235                         m2, unlock_dll, f, inc,
 236                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 237                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 238                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 239                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 240 }
 241
 242 void omap3_sram_restore_context(void)
 243 {
 244         omap_sram_reset();
 245
 246         _omap3_sram_configure_core_dpll =
 247                 omap_sram_push(omap3_sram_configure_core_dpll,
 248                                omap3_sram_configure_core_dpll_sz);
 249         omap_push_sram_idle();
 250 }
 251
 252 static inline int omap34xx_sram_init(void)
 253 {
 254         omap3_sram_restore_context();
 255         return 0;
 256 }
 257 #else
 258 static inline int omap34xx_sram_init(void)
 259 {
 260         return 0;
 261 }
 262 #endif /* CONFIG_ARCH_OMAP3 */
 263
 264 int __init omap_sram_init(void)
 265 {
 266         omap_detect_sram();
 267         omap2_map_sram();
 268
 269         if (cpu_is_omap242x())
 270                 omap242x_sram_init();
 271         else if (cpu_is_omap2430())
 272                 omap243x_sram_init();
 273         else if (cpu_is_omap34xx())
 274                 omap34xx_sram_init();
 275
 276         return 0;
 277 }