arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/io.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/ata_platform.h>
  31 #include <linux/amba/mmci.h>
  32 #include <linux/gfp.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/hardware/icst.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/map.h>
  47
  48 #include <asm/hardware/gic.h>
  49
  50 #include <mach/clkdev.h>
  51 #include <mach/platform.h>
  52 #include <mach/irqs.h>
  53 #include <plat/timer-sp.h>
  54
  55 #include "core.h"
  56
  57 /* used by entry-macro.S and platsmp.c */
  58 void __iomem *gic_cpu_base_addr;
  59
  60 #ifdef CONFIG_ZONE_DMA
  61 /*
  62  * Adjust the zones if there are restrictions for DMA access.
  63  */
  64 void __init realview_adjust_zones(int node, unsigned long *size,
  65                                   unsigned long *hole)
  66 {
  67         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
  68
  69         if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
  70                 return;
  71
  72         size[ZONE_NORMAL] = size[0] - dma_size;
  73         size[ZONE_DMA] = dma_size;
  74         hole[ZONE_NORMAL] = hole[0];
  75         hole[ZONE_DMA] = 0;
  76 }
  77 #endif
  78
  79
  80 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  81
  82 static int realview_flash_init(void)
  83 {
  84         u32 val;
  85
  86         val = __raw_readl(REALVIEW_FLASHCTRL);
  87         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  88         __raw_writel(val, REALVIEW_FLASHCTRL);
  89
  90         return 0;
  91 }
  92
  93 static void realview_flash_exit(void)
  94 {
  95         u32 val;
  96
  97         val = __raw_readl(REALVIEW_FLASHCTRL);
  98         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  99         __raw_writel(val, REALVIEW_FLASHCTRL);
 100 }
 101
 102 static void realview_flash_set_vpp(int on)
 103 {
 104         u32 val;
 105
 106         val = __raw_readl(REALVIEW_FLASHCTRL);
 107         if (on)
 108                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 109         else
 110                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 111         __raw_writel(val, REALVIEW_FLASHCTRL);
 112 }
 113
 114 static struct flash_platform_data realview_flash_data = {
 115         .map_name               = "cfi_probe",
 116         .width                  = 4,
 117         .init                   = realview_flash_init,
 118         .exit                   = realview_flash_exit,
 119         .set_vpp                = realview_flash_set_vpp,
 120 };
 121
 122 struct platform_device realview_flash_device = {
 123         .name                   = "armflash",
 124         .id                     = 0,
 125         .dev                    = {
 126                 .platform_data  = &realview_flash_data,
 127         },
 128 };
 129
 130 int realview_flash_register(struct resource *res, u32 num)
 131 {
 132         realview_flash_device.resource = res;
 133         realview_flash_device.num_resources = num;
 134         return platform_device_register(&realview_flash_device);
 135 }
 136
 137 static struct smsc911x_platform_config smsc911x_config = {
 138         .flags          = SMSC911X_USE_32BIT,
 139         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 140         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 141         .phy_interface  = PHY_INTERFACE_MODE_MII,
 142 };
 143
 144 static struct platform_device realview_eth_device = {
 145         .name           = "smsc911x",
 146         .id             = 0,
 147         .num_resources  = 2,
 148 };
 149
 150 int realview_eth_register(const char *name, struct resource *res)
 151 {
 152         if (name)
 153                 realview_eth_device.name = name;
 154         realview_eth_device.resource = res;
 155         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 156                 realview_eth_device.dev.platform_data = &smsc911x_config;
 157
 158         return platform_device_register(&realview_eth_device);
 159 }
 160
 161 struct platform_device realview_usb_device = {
 162         .name                   = "isp1760",
 163         .num_resources          = 2,
 164 };
 165
 166 int realview_usb_register(struct resource *res)
 167 {
 168         realview_usb_device.resource = res;
 169         return platform_device_register(&realview_usb_device);
 170 }
 171
 172 static struct pata_platform_info pata_platform_data = {
 173         .ioport_shift           = 1,
 174 };
 175
 176 static struct resource pata_resources[] = {
 177         [0] = {
 178                 .start          = REALVIEW_CF_BASE,
 179                 .end            = REALVIEW_CF_BASE + 0xff,
 180                 .flags          = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start          = REALVIEW_CF_BASE + 0x100,
 184                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 185                 .flags          = IORESOURCE_MEM,
 186         },
 187 };
 188
 189 struct platform_device realview_cf_device = {
 190         .name                   = "pata_platform",
 191         .id                     = -1,
 192         .num_resources          = ARRAY_SIZE(pata_resources),
 193         .resource               = pata_resources,
 194         .dev                    = {
 195                 .platform_data  = &pata_platform_data,
 196         },
 197 };
 198
 199 static struct resource realview_i2c_resource = {
 200         .start          = REALVIEW_I2C_BASE,
 201         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 202         .flags          = IORESOURCE_MEM,
 203 };
 204
 205 struct platform_device realview_i2c_device = {
 206         .name           = "versatile-i2c",
 207         .id             = 0,
 208         .num_resources  = 1,
 209         .resource       = &realview_i2c_resource,
 210 };
 211
 212 static struct i2c_board_info realview_i2c_board_info[] = {
 213         {
 214                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 215         },
 216 };
 217
 218 static int __init realview_i2c_init(void)
 219 {
 220         return i2c_register_board_info(0, realview_i2c_board_info,
 221                                        ARRAY_SIZE(realview_i2c_board_info));
 222 }
 223 arch_initcall(realview_i2c_init);
 224
 225 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 226
 227 /*
 228  * This is only used if GPIOLIB support is disabled
 229  */
 230 static unsigned int realview_mmc_status(struct device *dev)
 231 {
 232         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 233         u32 mask;
 234
 235         if (adev->res.start == REALVIEW_MMCI0_BASE)
 236                 mask = 1;
 237         else
 238                 mask = 2;
 239
 240         return !(readl(REALVIEW_SYSMCI) & mask);
 241 }
 242
 243 struct mmci_platform_data realview_mmc0_plat_data = {
 244         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 245         .status         = realview_mmc_status,
 246         .gpio_wp        = 17,
 247         .gpio_cd        = 16,
 248 };
 249
 250 struct mmci_platform_data realview_mmc1_plat_data = {
 251         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 252         .status         = realview_mmc_status,
 253         .gpio_wp        = 19,
 254         .gpio_cd        = 18,
 255 };
 256
 257 /*
 258  * Clock handling
 259  */
 260 static const struct icst_params realview_oscvco_params = {
 261         .ref            = 24000000,
 262         .vco_max        = ICST307_VCO_MAX,
 263         .vco_min        = ICST307_VCO_MIN,
 264         .vd_min         = 4 + 8,
 265         .vd_max         = 511 + 8,
 266         .rd_min         = 1 + 2,
 267         .rd_max         = 127 + 2,
 268         .s2div          = icst307_s2div,
 269         .idx2s          = icst307_idx2s,
 270 };
 271
 272 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 273 {
 274         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 275         u32 val;
 276
 277         val = readl(clk->vcoreg) & ~0x7ffff;
 278         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 279
 280         writel(0xa05f, sys_lock);
 281         writel(val, clk->vcoreg);
 282         writel(0, sys_lock);
 283 }
 284
 285 static const struct clk_ops oscvco_clk_ops = {
 286         .round  = icst_clk_round,
 287         .set    = icst_clk_set,
 288         .setvco = realview_oscvco_set,
 289 };
 290
 291 static struct clk oscvco_clk = {
 292         .ops    = &oscvco_clk_ops,
 293         .params = &realview_oscvco_params,
 294 };
 295
 296 /*
 297  * These are fixed clocks.
 298  */
 299 static struct clk ref24_clk = {
 300         .rate   = 24000000,
 301 };
 302
 303 static struct clk dummy_apb_pclk;
 304
 305 static struct clk_lookup lookups[] = {
 306         {       /* Bus clock */
 307                 .con_id         = "apb_pclk",
 308                 .clk            = &dummy_apb_pclk,
 309         }, {    /* UART0 */
 310                 .dev_id         = "dev:uart0",
 311                 .clk            = &ref24_clk,
 312         }, {    /* UART1 */
 313                 .dev_id         = "dev:uart1",
 314                 .clk            = &ref24_clk,
 315         }, {    /* UART2 */
 316                 .dev_id         = "dev:uart2",
 317                 .clk            = &ref24_clk,
 318         }, {    /* UART3 */
 319                 .dev_id         = "fpga:uart3",
 320                 .clk            = &ref24_clk,
 321         }, {    /* KMI0 */
 322                 .dev_id         = "fpga:kmi0",
 323                 .clk            = &ref24_clk,
 324         }, {    /* KMI1 */
 325                 .dev_id         = "fpga:kmi1",
 326                 .clk            = &ref24_clk,
 327         }, {    /* MMC0 */
 328                 .dev_id         = "fpga:mmc0",
 329                 .clk            = &ref24_clk,
 330         }, {    /* EB:CLCD */
 331                 .dev_id         = "dev:clcd",
 332                 .clk            = &oscvco_clk,
 333         }, {    /* PB:CLCD */
 334                 .dev_id         = "issp:clcd",
 335                 .clk            = &oscvco_clk,
 336         }
 337 };
 338
 339 static int __init clk_init(void)
 340 {
 341         if (machine_is_realview_pb1176())
 342                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 343         else
 344                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 345
 346         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 347
 348         return 0;
 349 }
 350 core_initcall(clk_init);
 351
 352 /*
 353  * CLCD support.
 354  */
 355 #define SYS_CLCD_NLCDIOON       (1 << 2)
 356 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 357 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 358 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 359 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 360 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 361 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 362 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 363 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 364
 365 static struct clcd_panel vga = {
 366         .mode           = {
 367                 .name           = "VGA",
 368                 .refresh        = 60,
 369                 .xres           = 640,
 370                 .yres           = 480,
 371                 .pixclock       = 39721,
 372                 .left_margin    = 40,
 373                 .right_margin   = 24,
 374                 .upper_margin   = 32,
 375                 .lower_margin   = 11,
 376                 .hsync_len      = 96,
 377                 .vsync_len      = 2,
 378                 .sync           = 0,
 379                 .vmode          = FB_VMODE_NONINTERLACED,
 380         },
 381         .width          = -1,
 382         .height         = -1,
 383         .tim2           = TIM2_BCD | TIM2_IPC,
 384         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 385         .bpp            = 16,
 386 };
 387
 388 static struct clcd_panel xvga = {
 389         .mode           = {
 390                 .name           = "XVGA",
 391                 .refresh        = 60,
 392                 .xres           = 1024,
 393                 .yres           = 768,
 394                 .pixclock       = 15748,
 395                 .left_margin    = 152,
 396                 .right_margin   = 48,
 397                 .upper_margin   = 23,
 398                 .lower_margin   = 3,
 399                 .hsync_len      = 104,
 400                 .vsync_len      = 4,
 401                 .sync           = 0,
 402                 .vmode          = FB_VMODE_NONINTERLACED,
 403         },
 404         .width          = -1,
 405         .height         = -1,
 406         .tim2           = TIM2_BCD | TIM2_IPC,
 407         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 408         .bpp            = 16,
 409 };
 410
 411 static struct clcd_panel sanyo_3_8_in = {
 412         .mode           = {
 413                 .name           = "Sanyo QVGA",
 414                 .refresh        = 116,
 415                 .xres           = 320,
 416                 .yres           = 240,
 417                 .pixclock       = 100000,
 418                 .left_margin    = 6,
 419                 .right_margin   = 6,
 420                 .upper_margin   = 5,
 421                 .lower_margin   = 5,
 422                 .hsync_len      = 6,
 423                 .vsync_len      = 6,
 424                 .sync           = 0,
 425                 .vmode          = FB_VMODE_NONINTERLACED,
 426         },
 427         .width          = -1,
 428         .height         = -1,
 429         .tim2           = TIM2_BCD,
 430         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 431         .bpp            = 16,
 432 };
 433
 434 static struct clcd_panel sanyo_2_5_in = {
 435         .mode           = {
 436                 .name           = "Sanyo QVGA Portrait",
 437                 .refresh        = 116,
 438                 .xres           = 240,
 439                 .yres           = 320,
 440                 .pixclock       = 100000,
 441                 .left_margin    = 20,
 442                 .right_margin   = 10,
 443                 .upper_margin   = 2,
 444                 .lower_margin   = 2,
 445                 .hsync_len      = 10,
 446                 .vsync_len      = 2,
 447                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 448                 .vmode          = FB_VMODE_NONINTERLACED,
 449         },
 450         .width          = -1,
 451         .height         = -1,
 452         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 453         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 454         .bpp            = 16,
 455 };
 456
 457 static struct clcd_panel epson_2_2_in = {
 458         .mode           = {
 459                 .name           = "Epson QCIF",
 460                 .refresh        = 390,
 461                 .xres           = 176,
 462                 .yres           = 220,
 463                 .pixclock       = 62500,
 464                 .left_margin    = 3,
 465                 .right_margin   = 2,
 466                 .upper_margin   = 1,
 467                 .lower_margin   = 0,
 468                 .hsync_len      = 3,
 469                 .vsync_len      = 2,
 470                 .sync           = 0,
 471                 .vmode          = FB_VMODE_NONINTERLACED,
 472         },
 473         .width          = -1,
 474         .height         = -1,
 475         .tim2           = TIM2_BCD | TIM2_IPC,
 476         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 477         .bpp            = 16,
 478 };
 479
 480 /*
 481  * Detect which LCD panel is connected, and return the appropriate
 482  * clcd_panel structure.  Note: we do not have any information on
 483  * the required timings for the 8.4in panel, so we presently assume
 484  * VGA timings.
 485  */
 486 static struct clcd_panel *realview_clcd_panel(void)
 487 {
 488         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 489         struct clcd_panel *vga_panel;
 490         struct clcd_panel *panel;
 491         u32 val;
 492
 493         if (machine_is_realview_eb())
 494                 vga_panel = &vga;
 495         else
 496                 vga_panel = &xvga;
 497
 498         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 499         if (val == SYS_CLCD_ID_SANYO_3_8)
 500                 panel = &sanyo_3_8_in;
 501         else if (val == SYS_CLCD_ID_SANYO_2_5)
 502                 panel = &sanyo_2_5_in;
 503         else if (val == SYS_CLCD_ID_EPSON_2_2)
 504                 panel = &epson_2_2_in;
 505         else if (val == SYS_CLCD_ID_VGA)
 506                 panel = vga_panel;
 507         else {
 508                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 509                         val);
 510                 panel = vga_panel;
 511         }
 512
 513         return panel;
 514 }
 515
 516 /*
 517  * Disable all display connectors on the interface module.
 518  */
 519 static void realview_clcd_disable(struct clcd_fb *fb)
 520 {
 521         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 522         u32 val;
 523
 524         val = readl(sys_clcd);
 525         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 526         writel(val, sys_clcd);
 527 }
 528
 529 /*
 530  * Enable the relevant connector on the interface module.
 531  */
 532 static void realview_clcd_enable(struct clcd_fb *fb)
 533 {
 534         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 535         u32 val;
 536
 537         /*
 538          * Enable the PSUs
 539          */
 540         val = readl(sys_clcd);
 541         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 542         writel(val, sys_clcd);
 543 }
 544
 545 static int realview_clcd_setup(struct clcd_fb *fb)
 546 {
 547         unsigned long framesize;
 548         dma_addr_t dma;
 549
 550         if (machine_is_realview_eb())
 551                 /* VGA, 16bpp */
 552                 framesize = 640 * 480 * 2;
 553         else
 554                 /* XVGA, 16bpp */
 555                 framesize = 1024 * 768 * 2;
 556
 557         fb->panel               = realview_clcd_panel();
 558
 559         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 560                                                     &dma, GFP_KERNEL | GFP_DMA);
 561         if (!fb->fb.screen_base) {
 562                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 563                 return -ENOMEM;
 564         }
 565
 566         fb->fb.fix.smem_start   = dma;
 567         fb->fb.fix.smem_len     = framesize;
 568
 569         return 0;
 570 }
 571
 572 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 573 {
 574         return dma_mmap_writecombine(&fb->dev->dev, vma,
 575                                      fb->fb.screen_base,
 576                                      fb->fb.fix.smem_start,
 577                                      fb->fb.fix.smem_len);
 578 }
 579
 580 static void realview_clcd_remove(struct clcd_fb *fb)
 581 {
 582         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 583                               fb->fb.screen_base, fb->fb.fix.smem_start);
 584 }
 585
 586 struct clcd_board clcd_plat_data = {
 587         .name           = "RealView",
 588         .check          = clcdfb_check,
 589         .decode         = clcdfb_decode,
 590         .disable        = realview_clcd_disable,
 591         .enable         = realview_clcd_enable,
 592         .setup          = realview_clcd_setup,
 593         .mmap           = realview_clcd_mmap,
 594         .remove         = realview_clcd_remove,
 595 };
 596
 597 #ifdef CONFIG_LEDS
 598 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 599
 600 void realview_leds_event(led_event_t ledevt)
 601 {
 602         unsigned long flags;
 603         u32 val;
 604         u32 led = 1 << smp_processor_id();
 605
 606         local_irq_save(flags);
 607         val = readl(VA_LEDS_BASE);
 608
 609         switch (ledevt) {
 610         case led_idle_start:
 611                 val = val & ~led;
 612                 break;
 613
 614         case led_idle_end:
 615                 val = val | led;
 616                 break;
 617
 618         case led_timer:
 619                 val = val ^ REALVIEW_SYS_LED7;
 620                 break;
 621
 622         case led_halted:
 623                 val = 0;
 624                 break;
 625
 626         default:
 627                 break;
 628         }
 629
 630         writel(val, VA_LEDS_BASE);
 631         local_irq_restore(flags);
 632 }
 633 #endif  /* CONFIG_LEDS */
 634
 635 /*
 636  * Where is the timer (VA)?
 637  */
 638 void __iomem *timer0_va_base;
 639 void __iomem *timer1_va_base;
 640 void __iomem *timer2_va_base;
 641 void __iomem *timer3_va_base;
 642
 643 /*
 644  * Set up the clock source and clock events devices
 645  */
 646 void __init realview_timer_init(unsigned int timer_irq)
 647 {
 648         u32 val;
 649
 650         /*
 651          * set clock frequency:
 652          *      REALVIEW_REFCLK is 32KHz
 653          *      REALVIEW_TIMCLK is 1MHz
 654          */
 655         val = readl(__io_address(REALVIEW_SCTL_BASE));
 656         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 657                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 658                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 659                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 660                __io_address(REALVIEW_SCTL_BASE));
 661
 662         /*
 663          * Initialise to a known state (all timers off)
 664          */
 665         writel(0, timer0_va_base + TIMER_CTRL);
 666         writel(0, timer1_va_base + TIMER_CTRL);
 667         writel(0, timer2_va_base + TIMER_CTRL);
 668         writel(0, timer3_va_base + TIMER_CTRL);
 669
 670         sp804_clocksource_init(timer3_va_base);
 671         sp804_clockevents_init(timer0_va_base, timer_irq);
 672 }
 673
 674 /*
 675  * Setup the memory banks.
 676  */
 677 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 678                     struct meminfo *meminfo)
 679 {
 680         /*
 681          * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 682          * Half of this is mirrored at 0.
 683          */
 684 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 685         meminfo->bank[0].start = 0x70000000;
 686         meminfo->bank[0].size = SZ_512M;
 687         meminfo->nr_banks = 1;
 688 #else
 689         meminfo->bank[0].start = 0;
 690         meminfo->bank[0].size = SZ_256M;
 691         meminfo->nr_banks = 1;
 692 #endif
 693 }