arch/arm/mach-s5pc100/dev-spi.c

   1 /* linux/arch/arm/mach-s5pc100/dev-spi.c
   2  *
   3  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/gpio.h>
  14
  15 #include <mach/dma.h>
  16 #include <mach/map.h>
  17 #include <mach/spi-clocks.h>
  18
  19 #include <plat/s3c64xx-spi.h>
  20 #include <plat/gpio-cfg.h>
  21 #include <plat/irqs.h>
  22
  23 static char *spi_src_clks[] = {
  24         [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
  25         [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
  26         [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
  27 };
  28
  29 /* SPI Controller platform_devices */
  30
  31 /* Since we emulate multi-cs capability, we do not touch the CS.
  32  * The emulated CS is toggled by board specific mechanism, as it can
  33  * be either some immediate GPIO or some signal out of some other
  34  * chip in between ... or some yet another way.
  35  * We simply do not assume anything about CS.
  36  */
  37 static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
  38 {
  39         switch (pdev->id) {
  40         case 0:
  41                 s3c_gpio_cfgpin_range(S5PC100_GPB(0), 3, S3C_GPIO_SFN(2));
  42                 s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
  43                 s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
  44                 s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
  45                 break;
  46
  47         case 1:
  48                 s3c_gpio_cfgpin_range(S5PC100_GPB(4), 3, S3C_GPIO_SFN(2));
  49                 s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
  50                 s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
  51                 s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
  52                 break;
  53
  54         case 2:
  55                 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
  56                 s3c_gpio_cfgpin_range(S5PC100_GPB(2), 2, S3C_GPIO_SFN(3));
  57                 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
  58                 s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
  59                 s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
  60                 break;
  61
  62         default:
  63                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  64                 return -EINVAL;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static struct resource s5pc100_spi0_resource[] = {
  71         [0] = {
  72                 .start = S5PC100_PA_SPI0,
  73                 .end   = S5PC100_PA_SPI0 + 0x100 - 1,
  74                 .flags = IORESOURCE_MEM,
  75         },
  76         [1] = {
  77                 .start = DMACH_SPI0_TX,
  78                 .end   = DMACH_SPI0_TX,
  79                 .flags = IORESOURCE_DMA,
  80         },
  81         [2] = {
  82                 .start = DMACH_SPI0_RX,
  83                 .end   = DMACH_SPI0_RX,
  84                 .flags = IORESOURCE_DMA,
  85         },
  86         [3] = {
  87                 .start = IRQ_SPI0,
  88                 .end   = IRQ_SPI0,
  89                 .flags = IORESOURCE_IRQ,
  90         },
  91 };
  92
  93 static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
  94         .cfg_gpio = s5pc100_spi_cfg_gpio,
  95         .fifo_lvl_mask = 0x7f,
  96         .rx_lvl_offset = 13,
  97         .high_speed = 1,
  98 };
  99
 100 static u64 spi_dmamask = DMA_BIT_MASK(32);
 101
 102 struct platform_device s5pc100_device_spi0 = {
 103         .name             = "s3c64xx-spi",
 104         .id               = 0,
 105         .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
 106         .resource         = s5pc100_spi0_resource,
 107         .dev = {
 108                 .dma_mask               = &spi_dmamask,
 109                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 110                 .platform_data = &s5pc100_spi0_pdata,
 111         },
 112 };
 113
 114 static struct resource s5pc100_spi1_resource[] = {
 115         [0] = {
 116                 .start = S5PC100_PA_SPI1,
 117                 .end   = S5PC100_PA_SPI1 + 0x100 - 1,
 118                 .flags = IORESOURCE_MEM,
 119         },
 120         [1] = {
 121                 .start = DMACH_SPI1_TX,
 122                 .end   = DMACH_SPI1_TX,
 123                 .flags = IORESOURCE_DMA,
 124         },
 125         [2] = {
 126                 .start = DMACH_SPI1_RX,
 127                 .end   = DMACH_SPI1_RX,
 128                 .flags = IORESOURCE_DMA,
 129         },
 130         [3] = {
 131                 .start = IRQ_SPI1,
 132                 .end   = IRQ_SPI1,
 133                 .flags = IORESOURCE_IRQ,
 134         },
 135 };
 136
 137 static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
 138         .cfg_gpio = s5pc100_spi_cfg_gpio,
 139         .fifo_lvl_mask = 0x7f,
 140         .rx_lvl_offset = 13,
 141         .high_speed = 1,
 142 };
 143
 144 struct platform_device s5pc100_device_spi1 = {
 145         .name             = "s3c64xx-spi",
 146         .id               = 1,
 147         .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
 148         .resource         = s5pc100_spi1_resource,
 149         .dev = {
 150                 .dma_mask               = &spi_dmamask,
 151                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 152                 .platform_data = &s5pc100_spi1_pdata,
 153         },
 154 };
 155
 156 static struct resource s5pc100_spi2_resource[] = {
 157         [0] = {
 158                 .start = S5PC100_PA_SPI2,
 159                 .end   = S5PC100_PA_SPI2 + 0x100 - 1,
 160                 .flags = IORESOURCE_MEM,
 161         },
 162         [1] = {
 163                 .start = DMACH_SPI2_TX,
 164                 .end   = DMACH_SPI2_TX,
 165                 .flags = IORESOURCE_DMA,
 166         },
 167         [2] = {
 168                 .start = DMACH_SPI2_RX,
 169                 .end   = DMACH_SPI2_RX,
 170                 .flags = IORESOURCE_DMA,
 171         },
 172         [3] = {
 173                 .start = IRQ_SPI2,
 174                 .end   = IRQ_SPI2,
 175                 .flags = IORESOURCE_IRQ,
 176         },
 177 };
 178
 179 static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
 180         .cfg_gpio = s5pc100_spi_cfg_gpio,
 181         .fifo_lvl_mask = 0x7f,
 182         .rx_lvl_offset = 13,
 183         .high_speed = 1,
 184 };
 185
 186 struct platform_device s5pc100_device_spi2 = {
 187         .name             = "s3c64xx-spi",
 188         .id               = 2,
 189         .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
 190         .resource         = s5pc100_spi2_resource,
 191         .dev = {
 192                 .dma_mask               = &spi_dmamask,
 193                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 194                 .platform_data = &s5pc100_spi2_pdata,
 195         },
 196 };
 197
 198 void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 199 {
 200         struct s3c64xx_spi_info *pd;
 201
 202         /* Reject invalid configuration */
 203         if (!num_cs || src_clk_nr < 0
 204                         || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
 205                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 206                 return;
 207         }
 208
 209         switch (cntrlr) {
 210         case 0:
 211                 pd = &s5pc100_spi0_pdata;
 212                 break;
 213         case 1:
 214                 pd = &s5pc100_spi1_pdata;
 215                 break;
 216         case 2:
 217                 pd = &s5pc100_spi2_pdata;
 218                 break;
 219         default:
 220                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 221                                                         __func__, cntrlr);
 222                 return;
 223         }
 224
 225         pd->num_cs = num_cs;
 226         pd->src_clk_nr = src_clk_nr;
 227         pd->src_clk_name = spi_src_clks[src_clk_nr];
 228 }