3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if (ACPI && PCI)
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_ELF_RANDOMIZE
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_NMI_SAFE_CMPXCHG
37 select ARCH_INLINE_READ_LOCK if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
53 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
63 select ARCH_KEEP_MEMBLOCK
64 select ARCH_USE_CMPXCHG_LOCKREF
65 select ARCH_USE_QUEUED_RWLOCKS
66 select ARCH_USE_QUEUED_SPINLOCKS
67 select ARCH_SUPPORTS_MEMORY_FAILURE
68 select ARCH_SUPPORTS_ATOMIC_RMW
69 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
70 select ARCH_SUPPORTS_NUMA_BALANCING
71 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
72 select ARCH_WANT_FRAME_POINTERS
73 select ARCH_HAS_UBSAN_SANITIZE_ALL
77 select AUDIT_ARCH_COMPAT_GENERIC
78 select ARM_GIC_V2M if PCI
80 select ARM_GIC_V3_ITS if PCI
82 select BUILDTIME_EXTABLE_SORT
83 select CLONE_BACKWARDS
85 select CPU_PM if (SUSPEND || CPU_IDLE)
87 select DCACHE_WORD_ACCESS
88 select DMA_DIRECT_REMAP
91 select GENERIC_ALLOCATOR
92 select GENERIC_ARCH_TOPOLOGY
93 select GENERIC_CLOCKEVENTS
94 select GENERIC_CLOCKEVENTS_BROADCAST
95 select GENERIC_CPU_AUTOPROBE
96 select GENERIC_CPU_VULNERABILITIES
97 select GENERIC_EARLY_IOREMAP
98 select GENERIC_IDLE_POLL_SETUP
99 select GENERIC_IRQ_MULTI_HANDLER
100 select GENERIC_IRQ_PROBE
101 select GENERIC_IRQ_SHOW
102 select GENERIC_IRQ_SHOW_LEVEL
103 select GENERIC_PCI_IOMAP
104 select GENERIC_SCHED_CLOCK
105 select GENERIC_SMP_IDLE_THREAD
106 select GENERIC_STRNCPY_FROM_USER
107 select GENERIC_STRNLEN_USER
108 select GENERIC_TIME_VSYSCALL
109 select HANDLE_DOMAIN_IRQ
110 select HARDIRQS_SW_RESEND
112 select HAVE_ACPI_APEI if (ACPI && EFI)
113 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
114 select HAVE_ARCH_AUDITSYSCALL
115 select HAVE_ARCH_BITREVERSE
116 select HAVE_ARCH_HUGE_VMAP
117 select HAVE_ARCH_JUMP_LABEL
118 select HAVE_ARCH_JUMP_LABEL_RELATIVE
119 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
120 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
121 select HAVE_ARCH_KGDB
122 select HAVE_ARCH_MMAP_RND_BITS
123 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
124 select HAVE_ARCH_PREL32_RELOCATIONS
125 select HAVE_ARCH_SECCOMP_FILTER
126 select HAVE_ARCH_STACKLEAK
127 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
128 select HAVE_ARCH_TRACEHOOK
129 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
130 select HAVE_ARCH_VMAP_STACK
131 select HAVE_ARM_SMCCC
133 select HAVE_C_RECORDMCOUNT
134 select HAVE_CMPXCHG_DOUBLE
135 select HAVE_CMPXCHG_LOCAL
136 select HAVE_CONTEXT_TRACKING
137 select HAVE_DEBUG_BUGVERBOSE
138 select HAVE_DEBUG_KMEMLEAK
139 select HAVE_DMA_CONTIGUOUS
140 select HAVE_DYNAMIC_FTRACE
141 select HAVE_EFFICIENT_UNALIGNED_ACCESS
142 select HAVE_FTRACE_MCOUNT_RECORD
143 select HAVE_FUNCTION_TRACER
144 select HAVE_FUNCTION_GRAPH_TRACER
145 select HAVE_GCC_PLUGINS
146 select HAVE_HW_BREAKPOINT if PERF_EVENTS
147 select HAVE_IRQ_TIME_ACCOUNTING
148 select HAVE_MEMBLOCK_NODE_MAP if NUMA
150 select HAVE_PATA_PLATFORM
151 select HAVE_PERF_EVENTS
152 select HAVE_PERF_REGS
153 select HAVE_PERF_USER_STACK_DUMP
154 select HAVE_REGS_AND_STACK_ACCESS_API
155 select HAVE_FUNCTION_ARG_ACCESS_API
156 select HAVE_RCU_TABLE_FREE
158 select HAVE_STACKPROTECTOR
159 select HAVE_SYSCALL_TRACEPOINTS
161 select HAVE_KRETPROBES
162 select IOMMU_DMA if IOMMU_SUPPORT
164 select IRQ_FORCED_THREADING
165 select MODULES_USE_ELF_RELA
166 select NEED_DMA_MAP_STATE
167 select NEED_SG_DMA_LENGTH
169 select OF_EARLY_FLATTREE
170 select PCI_DOMAINS_GENERIC if PCI
171 select PCI_ECAM if (ACPI && PCI)
172 select PCI_SYSCALL if PCI
178 select SYSCTL_EXCEPTION_TRACE
179 select THREAD_INFO_IN_TASK
181 ARM 64-bit (AArch64) Linux support.
189 config ARM64_PAGE_SHIFT
191 default 16 if ARM64_64K_PAGES
192 default 14 if ARM64_16K_PAGES
195 config ARM64_CONT_SHIFT
197 default 5 if ARM64_64K_PAGES
198 default 7 if ARM64_16K_PAGES
201 config ARCH_MMAP_RND_BITS_MIN
202 default 14 if ARM64_64K_PAGES
203 default 16 if ARM64_16K_PAGES
206 # max bits determined by the following formula:
207 # VA_BITS - PAGE_SHIFT - 3
208 config ARCH_MMAP_RND_BITS_MAX
209 default 19 if ARM64_VA_BITS=36
210 default 24 if ARM64_VA_BITS=39
211 default 27 if ARM64_VA_BITS=42
212 default 30 if ARM64_VA_BITS=47
213 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
214 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
215 default 33 if ARM64_VA_BITS=48
216 default 14 if ARM64_64K_PAGES
217 default 16 if ARM64_16K_PAGES
220 config ARCH_MMAP_RND_COMPAT_BITS_MIN
221 default 7 if ARM64_64K_PAGES
222 default 9 if ARM64_16K_PAGES
225 config ARCH_MMAP_RND_COMPAT_BITS_MAX
231 config STACKTRACE_SUPPORT
234 config ILLEGAL_POINTER_VALUE
236 default 0xdead000000000000
238 config LOCKDEP_SUPPORT
241 config TRACE_IRQFLAGS_SUPPORT
248 config GENERIC_BUG_RELATIVE_POINTERS
250 depends on GENERIC_BUG
252 config GENERIC_HWEIGHT
258 config GENERIC_CALIBRATE_DELAY
264 config HAVE_GENERIC_GUP
267 config ARCH_ENABLE_MEMORY_HOTPLUG
273 config KERNEL_MODE_NEON
276 config FIX_EARLYCON_MEM
279 config PGTABLE_LEVELS
281 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
282 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
283 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
284 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
285 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
286 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
288 config ARCH_SUPPORTS_UPROBES
291 config ARCH_PROC_KCORE_TEXT
294 source "arch/arm64/Kconfig.platforms"
296 menu "Kernel Features"
298 menu "ARM errata workarounds via the alternatives framework"
300 config ARM64_WORKAROUND_CLEAN_CACHE
303 config ARM64_ERRATUM_826319
304 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
306 select ARM64_WORKAROUND_CLEAN_CACHE
308 This option adds an alternative code sequence to work around ARM
309 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
310 AXI master interface and an L2 cache.
312 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
313 and is unable to accept a certain write via this interface, it will
314 not progress on read data presented on the read data channel and the
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this does not necessarily enable the workaround,
320 as it depends on the alternative framework, which will only patch
321 the kernel if an affected CPU is detected.
325 config ARM64_ERRATUM_827319
326 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
328 select ARM64_WORKAROUND_CLEAN_CACHE
330 This option adds an alternative code sequence to work around ARM
331 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
332 master interface and an L2 cache.
334 Under certain conditions this erratum can cause a clean line eviction
335 to occur at the same time as another transaction to the same address
336 on the AMBA 5 CHI interface, which can cause data corruption if the
337 interconnect reorders the two transactions.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_824069
348 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
350 select ARM64_WORKAROUND_CLEAN_CACHE
352 This option adds an alternative code sequence to work around ARM
353 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
354 to a coherent interconnect.
356 If a Cortex-A53 processor is executing a store or prefetch for
357 write instruction at the same time as a processor in another
358 cluster is executing a cache maintenance operation to the same
359 address, then this erratum might cause a clean cache line to be
360 incorrectly marked as dirty.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this option does not necessarily enable the
365 workaround, as it depends on the alternative framework, which will
366 only patch the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_819472
371 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 select ARM64_WORKAROUND_CLEAN_CACHE
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
402 The workaround is to promote device loads to use Load-Acquire
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_834220
411 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
415 This option adds an alternative code sequence to work around ARM
416 erratum 834220 on Cortex-A57 parts up to r1p2.
418 Affected Cortex-A57 parts might report a Stage 2 translation
419 fault as the result of a Stage 1 fault for load crossing a
420 page boundary when there is a permission or device memory
421 alignment fault at Stage 1 and a translation fault at Stage 2.
423 The workaround is to verify that the Stage 1 translation
424 doesn't generate a fault before handling the Stage 2 fault.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_845719
432 bool "Cortex-A53: 845719: a load might read incorrect data"
436 This option adds an alternative code sequence to work around ARM
437 erratum 845719 on Cortex-A53 parts up to r0p4.
439 When running a compat (AArch32) userspace on an affected Cortex-A53
440 part, a load at EL0 from a virtual address that matches the bottom 32
441 bits of the virtual address used by a recent load at (AArch64) EL1
442 might return incorrect data.
444 The workaround is to write the contextidr_el1 register on exception
445 return to a 32-bit task.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_843419
453 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
455 select ARM64_MODULE_PLTS if MODULES
457 This option links the kernel with '--fix-cortex-a53-843419' and
458 enables PLT support to replace certain ADRP instructions, which can
459 cause subsequent memory accesses to use an incorrect address on
460 Cortex-A53 parts up to r0p4.
464 config ARM64_ERRATUM_1024718
465 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
468 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
470 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
471 update of the hardware dirty bit when the DBM/AP bits are updated
472 without a break-before-make. The workaround is to disable the usage
473 of hardware DBM locally on the affected cores. CPUs not affected by
474 this erratum will continue to use the feature.
478 config ARM64_ERRATUM_1418040
479 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
483 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
484 errata 1188873 and 1418040.
486 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
487 cause register corruption when accessing the timer registers
488 from AArch32 userspace.
492 config ARM64_ERRATUM_1165522
493 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
496 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
498 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
499 corrupted TLBs by speculating an AT instruction during a guest
504 config ARM64_ERRATUM_1286807
505 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
507 select ARM64_WORKAROUND_REPEAT_TLBI
509 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
511 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
512 address for a cacheable mapping of a location is being
513 accessed by a core while another core is remapping the virtual
514 address to a new physical page using the recommended
515 break-before-make sequence, then under very rare circumstances
516 TLBI+DSB completes before a read using the translation being
517 invalidated has been observed by other observers. The
518 workaround repeats the TLBI+DSB operation.
522 config ARM64_ERRATUM_1463225
523 bool "Cortex-A76: Software Step might prevent interrupt recognition"
526 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
528 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
529 of a system call instruction (SVC) can prevent recognition of
530 subsequent interrupts when software stepping is disabled in the
531 exception handler of the system call and either kernel debugging
532 is enabled or VHE is in use.
534 Work around the erratum by triggering a dummy step exception
535 when handling a system call from a task that is being stepped
536 in a VHE configuration of the kernel.
540 config CAVIUM_ERRATUM_22375
541 bool "Cavium erratum 22375, 24313"
544 Enable workaround for errata 22375 and 24313.
546 This implements two gicv3-its errata workarounds for ThunderX. Both
547 with a small impact affecting only ITS table allocation.
549 erratum 22375: only alloc 8MB table size
550 erratum 24313: ignore memory access type
552 The fixes are in ITS initialization and basically ignore memory access
553 type and table size provided by the TYPER and BASER registers.
557 config CAVIUM_ERRATUM_23144
558 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
562 ITS SYNC command hang for cross node io and collections/cpu mapping.
566 config CAVIUM_ERRATUM_23154
567 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
570 The gicv3 of ThunderX requires a modified version for
571 reading the IAR status to ensure data synchronization
572 (access to icc_iar1_el1 is not sync'ed before and after).
576 config CAVIUM_ERRATUM_27456
577 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
580 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
581 instructions may cause the icache to become corrupted if it
582 contains data for a non-current ASID. The fix is to
583 invalidate the icache when changing the mm context.
587 config CAVIUM_ERRATUM_30115
588 bool "Cavium erratum 30115: Guest may disable interrupts in host"
591 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
592 1.2, and T83 Pass 1.0, KVM guest execution may disable
593 interrupts in host. Trapping both GICv3 group-0 and group-1
594 accesses sidesteps the issue.
598 config QCOM_FALKOR_ERRATUM_1003
599 bool "Falkor E1003: Incorrect translation due to ASID change"
602 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
603 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
604 in TTBR1_EL1, this situation only occurs in the entry trampoline and
605 then only for entries in the walk cache, since the leaf translation
606 is unchanged. Work around the erratum by invalidating the walk cache
607 entries for the trampoline before entering the kernel proper.
609 config ARM64_WORKAROUND_REPEAT_TLBI
612 config QCOM_FALKOR_ERRATUM_1009
613 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
615 select ARM64_WORKAROUND_REPEAT_TLBI
617 On Falkor v1, the CPU may prematurely complete a DSB following a
618 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
619 one more time to fix the issue.
623 config QCOM_QDF2400_ERRATUM_0065
624 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
627 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
628 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
629 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
633 config SOCIONEXT_SYNQUACER_PREITS
634 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
637 Socionext Synquacer SoCs implement a separate h/w block to generate
638 MSI doorbell writes with non-zero values for the device ID.
642 config HISILICON_ERRATUM_161600802
643 bool "Hip07 161600802: Erroneous redistributor VLPI base"
646 The HiSilicon Hip07 SoC uses the wrong redistributor base
647 when issued ITS commands such as VMOVP and VMAPP, and requires
648 a 128kB offset to be applied to the target address in this commands.
652 config QCOM_FALKOR_ERRATUM_E1041
653 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
656 Falkor CPU may speculatively fetch instructions from an improper
657 memory location when MMU translation is changed from SCTLR_ELn[M]=1
658 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
662 config FUJITSU_ERRATUM_010001
663 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
666 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
667 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
668 accesses may cause undefined fault (Data abort, DFSC=0b111111).
669 This fault occurs under a specific hardware condition when a
670 load/store instruction performs an address translation using:
671 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
672 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
673 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
674 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
676 The workaround is to ensure these bits are clear in TCR_ELx.
677 The workaround only affects the Fujitsu-A64FX.
686 default ARM64_4K_PAGES
688 Page size (translation granule) configuration.
690 config ARM64_4K_PAGES
693 This feature enables 4KB pages support.
695 config ARM64_16K_PAGES
698 The system will use 16KB pages support. AArch32 emulation
699 requires applications compiled with 16K (or a multiple of 16K)
702 config ARM64_64K_PAGES
705 This feature enables 64KB pages support (4KB by default)
706 allowing only two levels of page tables and faster TLB
707 look-up. AArch32 emulation requires applications compiled
708 with 64K aligned segments.
713 prompt "Virtual address space size"
714 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
715 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
716 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
718 Allows choosing one of multiple possible virtual address
719 space sizes. The level of translation table is determined by
720 a combination of page size and virtual address space size.
722 config ARM64_VA_BITS_36
723 bool "36-bit" if EXPERT
724 depends on ARM64_16K_PAGES
726 config ARM64_VA_BITS_39
728 depends on ARM64_4K_PAGES
730 config ARM64_VA_BITS_42
732 depends on ARM64_64K_PAGES
734 config ARM64_VA_BITS_47
736 depends on ARM64_16K_PAGES
738 config ARM64_VA_BITS_48
741 config ARM64_USER_VA_BITS_52
743 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
745 Enable 52-bit virtual addressing for userspace when explicitly
746 requested via a hint to mmap(). The kernel will continue to
747 use 48-bit virtual addresses for its own mappings.
749 NOTE: Enabling 52-bit virtual addressing in conjunction with
750 ARMv8.3 Pointer Authentication will result in the PAC being
751 reduced from 7 bits to 3 bits, which may have a significant
752 impact on its susceptibility to brute-force attacks.
754 If unsure, select 48-bit virtual addressing instead.
758 config ARM64_FORCE_52BIT
759 bool "Force 52-bit virtual addresses for userspace"
760 depends on ARM64_USER_VA_BITS_52 && EXPERT
762 For systems with 52-bit userspace VAs enabled, the kernel will attempt
763 to maintain compatibility with older software by providing 48-bit VAs
764 unless a hint is supplied to mmap.
766 This configuration option disables the 48-bit compatibility logic, and
767 forces all userspace addresses to be 52-bit on HW that supports it. One
768 should only enable this configuration option for stress testing userspace
769 memory management code. If unsure say N here.
773 default 36 if ARM64_VA_BITS_36
774 default 39 if ARM64_VA_BITS_39
775 default 42 if ARM64_VA_BITS_42
776 default 47 if ARM64_VA_BITS_47
777 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
780 prompt "Physical address space size"
781 default ARM64_PA_BITS_48
783 Choose the maximum physical address range that the kernel will
786 config ARM64_PA_BITS_48
789 config ARM64_PA_BITS_52
790 bool "52-bit (ARMv8.2)"
791 depends on ARM64_64K_PAGES
792 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
794 Enable support for a 52-bit physical address space, introduced as
795 part of the ARMv8.2-LPA extension.
797 With this enabled, the kernel will also continue to work on CPUs that
798 do not support ARMv8.2-LPA, but with some added memory overhead (and
799 minor performance overhead).
805 default 48 if ARM64_PA_BITS_48
806 default 52 if ARM64_PA_BITS_52
808 config CPU_BIG_ENDIAN
809 bool "Build big-endian kernel"
811 Say Y if you plan on running a kernel in big-endian mode.
814 bool "Multi-core scheduler support"
816 Multi-core scheduler support improves the CPU scheduler's decision
817 making when dealing with multi-core CPU chips at a cost of slightly
818 increased overhead in some places. If unsure say N here.
821 bool "SMT scheduler support"
823 Improves the CPU scheduler's decision making when dealing with
824 MultiThreading at a cost of slightly increased overhead in some
825 places. If unsure say N here.
828 int "Maximum number of CPUs (2-4096)"
833 bool "Support for hot-pluggable CPUs"
834 select GENERIC_IRQ_MIGRATION
836 Say Y here to experiment with turning CPUs off and on. CPUs
837 can be controlled through /sys/devices/system/cpu.
839 # Common NUMA Features
841 bool "Numa Memory Allocation and Scheduler Support"
842 select ACPI_NUMA if ACPI
845 Enable NUMA (Non Uniform Memory Access) support.
847 The kernel will try to allocate memory used by a CPU on the
848 local memory of the CPU and add some more
849 NUMA awareness to the kernel.
852 int "Maximum NUMA Nodes (as a power of 2)"
855 depends on NEED_MULTIPLE_NODES
857 Specify the maximum number of NUMA Nodes available on the target
858 system. Increases memory reserved to accommodate various tables.
860 config USE_PERCPU_NUMA_NODE_ID
864 config HAVE_SETUP_PER_CPU_AREA
868 config NEED_PER_CPU_EMBED_FIRST_CHUNK
875 source "kernel/Kconfig.hz"
877 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
880 config ARCH_SPARSEMEM_ENABLE
882 select SPARSEMEM_VMEMMAP_ENABLE
884 config ARCH_SPARSEMEM_DEFAULT
885 def_bool ARCH_SPARSEMEM_ENABLE
887 config ARCH_SELECT_MEMORY_MODEL
888 def_bool ARCH_SPARSEMEM_ENABLE
890 config ARCH_FLATMEM_ENABLE
893 config HAVE_ARCH_PFN_VALID
896 config HW_PERF_EVENTS
900 config SYS_SUPPORTS_HUGETLBFS
903 config ARCH_WANT_HUGE_PMD_SHARE
904 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
906 config ARCH_HAS_CACHE_LINE_SIZE
909 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
910 def_bool y if PGTABLE_LEVELS > 2
913 bool "Enable seccomp to safely compute untrusted bytecode"
915 This kernel feature is useful for number crunching applications
916 that may need to compute untrusted bytecode during their
917 execution. By using pipes or other transports made available to
918 the process as file descriptors supporting the read/write
919 syscalls, it's possible to isolate those applications in
920 their own address space using seccomp. Once seccomp is
921 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
922 and the task is only allowed to execute a few safe syscalls
923 defined by each seccomp mode.
926 bool "Enable paravirtualization code"
928 This changes the kernel so it can modify itself when it is run
929 under a hypervisor, potentially improving performance significantly
930 over full virtualization.
932 config PARAVIRT_TIME_ACCOUNTING
933 bool "Paravirtual steal time accounting"
937 Select this option to enable fine granularity task steal time
938 accounting. Time spent executing other tasks in parallel with
939 the current vCPU is discounted from the vCPU power. To account for
940 that, there can be a small performance impact.
942 If in doubt, say N here.
945 depends on PM_SLEEP_SMP
947 bool "kexec system call"
949 kexec is a system call that implements the ability to shutdown your
950 current kernel, and to start another kernel. It is like a reboot
951 but it is independent of the system firmware. And like a reboot
952 you can start any kernel with it, not just Linux.
955 bool "kexec file based system call"
958 This is new version of kexec system call. This system call is
959 file based and takes file descriptors as system call argument
960 for kernel and initramfs as opposed to list of segments as
961 accepted by previous system call.
963 config KEXEC_VERIFY_SIG
964 bool "Verify kernel signature during kexec_file_load() syscall"
965 depends on KEXEC_FILE
967 Select this option to verify a signature with loaded kernel
968 image. If configured, any attempt of loading a image without
969 valid signature will fail.
971 In addition to that option, you need to enable signature
972 verification for the corresponding kernel image type being
973 loaded in order for this to work.
975 config KEXEC_IMAGE_VERIFY_SIG
976 bool "Enable Image signature verification support"
978 depends on KEXEC_VERIFY_SIG
979 depends on EFI && SIGNED_PE_FILE_VERIFICATION
981 Enable Image signature verification support.
983 comment "Support for PE file signature verification disabled"
984 depends on KEXEC_VERIFY_SIG
985 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
988 bool "Build kdump crash kernel"
990 Generate crash dump after being started by kexec. This should
991 be normally only set in special crash dump kernels which are
992 loaded in the main kernel with kexec-tools into a specially
993 reserved region and then later executed after a crash by
996 For more details see Documentation/kdump/kdump.txt
1003 bool "Xen guest support on ARM64"
1004 depends on ARM64 && OF
1008 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1010 config FORCE_MAX_ZONEORDER
1012 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1013 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1016 The kernel memory allocator divides physically contiguous memory
1017 blocks into "zones", where each zone is a power of two number of
1018 pages. This option selects the largest power of two that the kernel
1019 keeps in the memory allocator. If you need to allocate very large
1020 blocks of physically contiguous memory, then you may need to
1021 increase this value.
1023 This config option is actually maximum order plus one. For example,
1024 a value of 11 means that the largest free memory block is 2^10 pages.
1026 We make sure that we can allocate upto a HugePage size for each configuration.
1028 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1030 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1031 4M allocations matching the default size used by generic code.
1033 config UNMAP_KERNEL_AT_EL0
1034 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1037 Speculation attacks against some high-performance processors can
1038 be used to bypass MMU permission checks and leak kernel data to
1039 userspace. This can be defended against by unmapping the kernel
1040 when running in userspace, mapping it back in on exception entry
1041 via a trampoline page in the vector table.
1045 config HARDEN_BRANCH_PREDICTOR
1046 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1049 Speculation attacks against some high-performance processors rely on
1050 being able to manipulate the branch predictor for a victim context by
1051 executing aliasing branches in the attacker context. Such attacks
1052 can be partially mitigated against by clearing internal branch
1053 predictor state and limiting the prediction logic in some situations.
1055 This config option will take CPU-specific actions to harden the
1056 branch predictor against aliasing attacks and may rely on specific
1057 instruction sequences or control bits being set by the system
1062 config HARDEN_EL2_VECTORS
1063 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1066 Speculation attacks against some high-performance processors can
1067 be used to leak privileged information such as the vector base
1068 register, resulting in a potential defeat of the EL2 layout
1071 This config option will map the vectors to a fixed location,
1072 independent of the EL2 code mapping, so that revealing VBAR_EL2
1073 to an attacker does not give away any extra information. This
1074 only gets enabled on affected CPUs.
1079 bool "Speculative Store Bypass Disable" if EXPERT
1082 This enables mitigation of the bypassing of previous stores
1083 by speculative loads.
1087 config RODATA_FULL_DEFAULT_ENABLED
1088 bool "Apply r/o permissions of VM areas also to their linear aliases"
1091 Apply read-only attributes of VM areas to the linear alias of
1092 the backing pages as well. This prevents code or read-only data
1093 from being modified (inadvertently or intentionally) via another
1094 mapping of the same memory page. This additional enhancement can
1095 be turned off at runtime by passing rodata=[off|on] (and turned on
1096 with rodata=full if this option is set to 'n')
1098 This requires the linear region to be mapped down to pages,
1099 which may adversely affect performance in some cases.
1101 config ARM64_SW_TTBR0_PAN
1102 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1104 Enabling this option prevents the kernel from accessing
1105 user-space memory directly by pointing TTBR0_EL1 to a reserved
1106 zeroed area and reserved ASID. The user access routines
1107 restore the valid TTBR0_EL1 temporarily.
1110 bool "Kernel support for 32-bit EL0"
1111 depends on ARM64_4K_PAGES || EXPERT
1112 select COMPAT_BINFMT_ELF if BINFMT_ELF
1114 select OLD_SIGSUSPEND3
1115 select COMPAT_OLD_SIGACTION
1117 This option enables support for a 32-bit EL0 running under a 64-bit
1118 kernel at EL1. AArch32-specific components such as system calls,
1119 the user helper functions, VFP support and the ptrace interface are
1120 handled appropriately by the kernel.
1122 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1123 that you will only be able to execute AArch32 binaries that were compiled
1124 with page size aligned segments.
1126 If you want to execute 32-bit userspace applications, say Y.
1130 config KUSER_HELPERS
1131 bool "Enable kuser helpers page for 32 bit applications"
1134 Warning: disabling this option may break 32-bit user programs.
1136 Provide kuser helpers to compat tasks. The kernel provides
1137 helper code to userspace in read only form at a fixed location
1138 to allow userspace to be independent of the CPU type fitted to
1139 the system. This permits binaries to be run on ARMv4 through
1140 to ARMv8 without modification.
1142 See Documentation/arm/kernel_user_helpers.txt for details.
1144 However, the fixed address nature of these helpers can be used
1145 by ROP (return orientated programming) authors when creating
1148 If all of the binaries and libraries which run on your platform
1149 are built specifically for your platform, and make no use of
1150 these helpers, then you can turn this option off to hinder
1151 such exploits. However, in that case, if a binary or library
1152 relying on those helpers is run, it will not function correctly.
1154 Say N here only if you are absolutely certain that you do not
1155 need these helpers; otherwise, the safe option is to say Y.
1158 menuconfig ARMV8_DEPRECATED
1159 bool "Emulate deprecated/obsolete ARMv8 instructions"
1162 Legacy software support may require certain instructions
1163 that have been deprecated or obsoleted in the architecture.
1165 Enable this config to enable selective emulation of these
1172 config SWP_EMULATION
1173 bool "Emulate SWP/SWPB instructions"
1175 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1176 they are always undefined. Say Y here to enable software
1177 emulation of these instructions for userspace using LDXR/STXR.
1179 In some older versions of glibc [<=2.8] SWP is used during futex
1180 trylock() operations with the assumption that the code will not
1181 be preempted. This invalid assumption may be more likely to fail
1182 with SWP emulation enabled, leading to deadlock of the user
1185 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1186 on an external transaction monitoring block called a global
1187 monitor to maintain update atomicity. If your system does not
1188 implement a global monitor, this option can cause programs that
1189 perform SWP operations to uncached memory to deadlock.
1193 config CP15_BARRIER_EMULATION
1194 bool "Emulate CP15 Barrier instructions"
1196 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1197 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1198 strongly recommended to use the ISB, DSB, and DMB
1199 instructions instead.
1201 Say Y here to enable software emulation of these
1202 instructions for AArch32 userspace code. When this option is
1203 enabled, CP15 barrier usage is traced which can help
1204 identify software that needs updating.
1208 config SETEND_EMULATION
1209 bool "Emulate SETEND instruction"
1211 The SETEND instruction alters the data-endianness of the
1212 AArch32 EL0, and is deprecated in ARMv8.
1214 Say Y here to enable software emulation of the instruction
1215 for AArch32 userspace code.
1217 Note: All the cpus on the system must have mixed endian support at EL0
1218 for this feature to be enabled. If a new CPU - which doesn't support mixed
1219 endian - is hotplugged in after this feature has been enabled, there could
1220 be unexpected results in the applications.
1227 menu "ARMv8.1 architectural features"
1229 config ARM64_HW_AFDBM
1230 bool "Support for hardware updates of the Access and Dirty page flags"
1233 The ARMv8.1 architecture extensions introduce support for
1234 hardware updates of the access and dirty information in page
1235 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1236 capable processors, accesses to pages with PTE_AF cleared will
1237 set this bit instead of raising an access flag fault.
1238 Similarly, writes to read-only pages with the DBM bit set will
1239 clear the read-only bit (AP[2]) instead of raising a
1242 Kernels built with this configuration option enabled continue
1243 to work on pre-ARMv8.1 hardware and the performance impact is
1244 minimal. If unsure, say Y.
1247 bool "Enable support for Privileged Access Never (PAN)"
1250 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1251 prevents the kernel or hypervisor from accessing user-space (EL0)
1254 Choosing this option will cause any unprotected (not using
1255 copy_to_user et al) memory access to fail with a permission fault.
1257 The feature is detected at runtime, and will remain as a 'nop'
1258 instruction if the cpu does not implement the feature.
1260 config ARM64_LSE_ATOMICS
1261 bool "Atomic instructions"
1264 As part of the Large System Extensions, ARMv8.1 introduces new
1265 atomic instructions that are designed specifically to scale in
1268 Say Y here to make use of these instructions for the in-kernel
1269 atomic routines. This incurs a small overhead on CPUs that do
1270 not support these instructions and requires the kernel to be
1271 built with binutils >= 2.25 in order for the new instructions
1275 bool "Enable support for Virtualization Host Extensions (VHE)"
1278 Virtualization Host Extensions (VHE) allow the kernel to run
1279 directly at EL2 (instead of EL1) on processors that support
1280 it. This leads to better performance for KVM, as they reduce
1281 the cost of the world switch.
1283 Selecting this option allows the VHE feature to be detected
1284 at runtime, and does not affect processors that do not
1285 implement this feature.
1289 menu "ARMv8.2 architectural features"
1292 bool "Enable support for User Access Override (UAO)"
1295 User Access Override (UAO; part of the ARMv8.2 Extensions)
1296 causes the 'unprivileged' variant of the load/store instructions to
1297 be overridden to be privileged.
1299 This option changes get_user() and friends to use the 'unprivileged'
1300 variant of the load/store instructions. This ensures that user-space
1301 really did have access to the supplied memory. When addr_limit is
1302 set to kernel memory the UAO bit will be set, allowing privileged
1303 access to kernel memory.
1305 Choosing this option will cause copy_to_user() et al to use user-space
1308 The feature is detected at runtime, the kernel will use the
1309 regular load/store instructions if the cpu does not implement the
1313 bool "Enable support for persistent memory"
1314 select ARCH_HAS_PMEM_API
1315 select ARCH_HAS_UACCESS_FLUSHCACHE
1317 Say Y to enable support for the persistent memory API based on the
1318 ARMv8.2 DCPoP feature.
1320 The feature is detected at runtime, and the kernel will use DC CVAC
1321 operations if DC CVAP is not supported (following the behaviour of
1322 DC CVAP itself if the system does not define a point of persistence).
1324 config ARM64_RAS_EXTN
1325 bool "Enable support for RAS CPU Extensions"
1328 CPUs that support the Reliability, Availability and Serviceability
1329 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1330 errors, classify them and report them to software.
1332 On CPUs with these extensions system software can use additional
1333 barriers to determine if faults are pending and read the
1334 classification from a new set of registers.
1336 Selecting this feature will allow the kernel to use these barriers
1337 and access the new registers if the system supports the extension.
1338 Platform RAS features may additionally depend on firmware support.
1341 bool "Enable support for Common Not Private (CNP) translations"
1343 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1345 Common Not Private (CNP) allows translation table entries to
1346 be shared between different PEs in the same inner shareable
1347 domain, so the hardware can use this fact to optimise the
1348 caching of such entries in the TLB.
1350 Selecting this option allows the CNP feature to be detected
1351 at runtime, and does not affect PEs that do not implement
1356 menu "ARMv8.3 architectural features"
1358 config ARM64_PTR_AUTH
1359 bool "Enable support for pointer authentication"
1361 depends on !KVM || ARM64_VHE
1363 Pointer authentication (part of the ARMv8.3 Extensions) provides
1364 instructions for signing and authenticating pointers against secret
1365 keys, which can be used to mitigate Return Oriented Programming (ROP)
1368 This option enables these instructions at EL0 (i.e. for userspace).
1370 Choosing this option will cause the kernel to initialise secret keys
1371 for each process at exec() time, with these keys being
1372 context-switched along with the process.
1374 The feature is detected at runtime. If the feature is not present in
1375 hardware it will not be advertised to userspace/KVM guest nor will it
1376 be enabled. However, KVM guest also require VHE mode and hence
1377 CONFIG_ARM64_VHE=y option to use this feature.
1382 bool "ARM Scalable Vector Extension support"
1384 depends on !KVM || ARM64_VHE
1386 The Scalable Vector Extension (SVE) is an extension to the AArch64
1387 execution state which complements and extends the SIMD functionality
1388 of the base architecture to support much larger vectors and to enable
1389 additional vectorisation opportunities.
1391 To enable use of this extension on CPUs that implement it, say Y.
1393 On CPUs that support the SVE2 extensions, this option will enable
1396 Note that for architectural reasons, firmware _must_ implement SVE
1397 support when running on SVE capable hardware. The required support
1400 * version 1.5 and later of the ARM Trusted Firmware
1401 * the AArch64 boot wrapper since commit 5e1261e08abf
1402 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1404 For other firmware implementations, consult the firmware documentation
1407 If you need the kernel to boot on SVE-capable hardware with broken
1408 firmware, you may need to say N here until you get your firmware
1409 fixed. Otherwise, you may experience firmware panics or lockups when
1410 booting the kernel. If unsure and you are not observing these
1411 symptoms, you should assume that it is safe to say Y.
1413 CPUs that support SVE are architecturally required to support the
1414 Virtualization Host Extensions (VHE), so the kernel makes no
1415 provision for supporting SVE alongside KVM without VHE enabled.
1416 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1417 KVM in the same kernel image.
1419 config ARM64_MODULE_PLTS
1421 select HAVE_MOD_ARCH_SPECIFIC
1423 config ARM64_PSEUDO_NMI
1424 bool "Support for NMI-like interrupts"
1425 select CONFIG_ARM_GIC_V3
1427 Adds support for mimicking Non-Maskable Interrupts through the use of
1428 GIC interrupt priority. This support requires version 3 or later of
1431 This high priority configuration for interrupts needs to be
1432 explicitly enabled by setting the kernel parameter
1433 "irqchip.gicv3_pseudo_nmi" to 1.
1440 This builds the kernel as a Position Independent Executable (PIE),
1441 which retains all relocation metadata required to relocate the
1442 kernel binary at runtime to a different virtual address than the
1443 address it was linked at.
1444 Since AArch64 uses the RELA relocation format, this requires a
1445 relocation pass at runtime even if the kernel is loaded at the
1446 same address it was linked at.
1448 config RANDOMIZE_BASE
1449 bool "Randomize the address of the kernel image"
1450 select ARM64_MODULE_PLTS if MODULES
1453 Randomizes the virtual address at which the kernel image is
1454 loaded, as a security feature that deters exploit attempts
1455 relying on knowledge of the location of kernel internals.
1457 It is the bootloader's job to provide entropy, by passing a
1458 random u64 value in /chosen/kaslr-seed at kernel entry.
1460 When booting via the UEFI stub, it will invoke the firmware's
1461 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1462 to the kernel proper. In addition, it will randomise the physical
1463 location of the kernel Image as well.
1467 config RANDOMIZE_MODULE_REGION_FULL
1468 bool "Randomize the module region over a 4 GB range"
1469 depends on RANDOMIZE_BASE
1472 Randomizes the location of the module region inside a 4 GB window
1473 covering the core kernel. This way, it is less likely for modules
1474 to leak information about the location of core kernel data structures
1475 but it does imply that function calls between modules and the core
1476 kernel will need to be resolved via veneers in the module PLT.
1478 When this option is not set, the module region will be randomized over
1479 a limited range that contains the [_stext, _etext] interval of the
1480 core kernel, so branch relocations are always in range.
1482 config CC_HAVE_STACKPROTECTOR_SYSREG
1483 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1485 config STACKPROTECTOR_PER_TASK
1487 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1493 config ARM64_ACPI_PARKING_PROTOCOL
1494 bool "Enable support for the ARM64 ACPI parking protocol"
1497 Enable support for the ARM64 ACPI parking protocol. If disabled
1498 the kernel will not allow booting through the ARM64 ACPI parking
1499 protocol even if the corresponding data is present in the ACPI
1503 string "Default kernel command string"
1506 Provide a set of default command-line options at build time by
1507 entering them here. As a minimum, you should specify the the
1508 root device (e.g. root=/dev/nfs).
1510 config CMDLINE_FORCE
1511 bool "Always use the default kernel command string"
1513 Always use the default kernel command string, even if the boot
1514 loader passes other arguments to the kernel.
1515 This is useful if you cannot or don't want to change the
1516 command-line options your boot loader passes to the kernel.
1522 bool "UEFI runtime support"
1523 depends on OF && !CPU_BIG_ENDIAN
1524 depends on KERNEL_MODE_NEON
1525 select ARCH_SUPPORTS_ACPI
1528 select EFI_PARAMS_FROM_FDT
1529 select EFI_RUNTIME_WRAPPERS
1534 This option provides support for runtime services provided
1535 by UEFI firmware (such as non-volatile variables, realtime
1536 clock, and platform reset). A UEFI stub is also provided to
1537 allow the kernel to be booted as an EFI application. This
1538 is only useful on systems that have UEFI firmware.
1541 bool "Enable support for SMBIOS (DMI) tables"
1545 This enables SMBIOS/DMI feature for systems.
1547 This option is only useful on systems that have UEFI firmware.
1548 However, even with this option, the resultant kernel should
1549 continue to boot on existing non-UEFI platforms.
1553 config SYSVIPC_COMPAT
1555 depends on COMPAT && SYSVIPC
1557 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1559 depends on HUGETLB_PAGE && MIGRATION
1561 menu "Power management options"
1563 source "kernel/power/Kconfig"
1565 config ARCH_HIBERNATION_POSSIBLE
1569 config ARCH_HIBERNATION_HEADER
1571 depends on HIBERNATION
1573 config ARCH_SUSPEND_POSSIBLE
1578 menu "CPU Power Management"
1580 source "drivers/cpuidle/Kconfig"
1582 source "drivers/cpufreq/Kconfig"
1586 source "drivers/firmware/Kconfig"
1588 source "drivers/acpi/Kconfig"
1590 source "arch/arm64/kvm/Kconfig"
1593 source "arch/arm64/crypto/Kconfig"