arch/arm64/boot/dts/renesas/r8a77961.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a77961-sysc.h>
  11
  12 #define CPG_AUDIO_CLK_I         R8A77961_CLK_S0D4
  13
  14 / {
  15         compatible = "renesas,r8a77961";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         /*
  20          * The external audio clocks are configured as 0 Hz fixed frequency
  21          * clocks by default.
  22          * Boards that provide audio clocks should override them.
  23          */
  24         audio_clk_a: audio_clk_a {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <0>;
  28         };
  29
  30         audio_clk_b: audio_clk_b {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <0>;
  34         };
  35
  36         audio_clk_c: audio_clk_c {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 clock-frequency = <0>;
  40         };
  41
  42         /* External CAN clock - to be overridden by boards that provide it */
  43         can_clk: can {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <0>;
  47         };
  48
  49         cluster0_opp: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp-500000000 {
  54                         opp-hz = /bits/ 64 <500000000>;
  55                         opp-microvolt = <820000>;
  56                         clock-latency-ns = <300000>;
  57                 };
  58                 opp-1000000000 {
  59                         opp-hz = /bits/ 64 <1000000000>;
  60                         opp-microvolt = <820000>;
  61                         clock-latency-ns = <300000>;
  62                 };
  63                 opp-1500000000 {
  64                         opp-hz = /bits/ 64 <1500000000>;
  65                         opp-microvolt = <820000>;
  66                         clock-latency-ns = <300000>;
  67                 };
  68                 opp-1600000000 {
  69                         opp-hz = /bits/ 64 <1600000000>;
  70                         opp-microvolt = <900000>;
  71                         clock-latency-ns = <300000>;
  72                         turbo-mode;
  73                 };
  74                 opp-1700000000 {
  75                         opp-hz = /bits/ 64 <1700000000>;
  76                         opp-microvolt = <900000>;
  77                         clock-latency-ns = <300000>;
  78                         turbo-mode;
  79                 };
  80                 opp-1800000000 {
  81                         opp-hz = /bits/ 64 <1800000000>;
  82                         opp-microvolt = <960000>;
  83                         clock-latency-ns = <300000>;
  84                         turbo-mode;
  85                 };
  86         };
  87
  88         cluster1_opp: opp_table1 {
  89                 compatible = "operating-points-v2";
  90                 opp-shared;
  91
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         opp-microvolt = <820000>;
  95                         clock-latency-ns = <300000>;
  96                 };
  97                 opp-1000000000 {
  98                         opp-hz = /bits/ 64 <1000000000>;
  99                         opp-microvolt = <820000>;
 100                         clock-latency-ns = <300000>;
 101                 };
 102                 opp-1200000000 {
 103                         opp-hz = /bits/ 64 <1200000000>;
 104                         opp-microvolt = <820000>;
 105                         clock-latency-ns = <300000>;
 106                 };
 107                 opp-1300000000 {
 108                         opp-hz = /bits/ 64 <1300000000>;
 109                         opp-microvolt = <820000>;
 110                         clock-latency-ns = <300000>;
 111                         turbo-mode;
 112                 };
 113         };
 114
 115         cpus {
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118
 119                 cpu-map {
 120                         cluster0 {
 121                                 core0 {
 122                                         cpu = <&a57_0>;
 123                                 };
 124                                 core1 {
 125                                         cpu = <&a57_1>;
 126                                 };
 127                         };
 128
 129                         cluster1 {
 130                                 core0 {
 131                                         cpu = <&a53_0>;
 132                                 };
 133                                 core1 {
 134                                         cpu = <&a53_1>;
 135                                 };
 136                                 core2 {
 137                                         cpu = <&a53_2>;
 138                                 };
 139                                 core3 {
 140                                         cpu = <&a53_3>;
 141                                 };
 142                         };
 143                 };
 144
 145                 a57_0: cpu@0 {
 146                         compatible = "arm,cortex-a57";
 147                         reg = <0x0>;
 148                         device_type = "cpu";
 149                         power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
 150                         next-level-cache = <&L2_CA57>;
 151                         enable-method = "psci";
 152                         cpu-idle-states = <&CPU_SLEEP_0>;
 153                         dynamic-power-coefficient = <854>;
 154                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         capacity-dmips-mhz = <1024>;
 157                         #cooling-cells = <2>;
 158                 };
 159
 160                 a57_1: cpu@1 {
 161                         compatible = "arm,cortex-a57";
 162                         reg = <0x1>;
 163                         device_type = "cpu";
 164                         power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
 165                         next-level-cache = <&L2_CA57>;
 166                         enable-method = "psci";
 167                         cpu-idle-states = <&CPU_SLEEP_0>;
 168                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         capacity-dmips-mhz = <1024>;
 171                         #cooling-cells = <2>;
 172                 };
 173
 174                 a53_0: cpu@100 {
 175                         compatible = "arm,cortex-a53";
 176                         reg = <0x100>;
 177                         device_type = "cpu";
 178                         power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
 179                         next-level-cache = <&L2_CA53>;
 180                         enable-method = "psci";
 181                         cpu-idle-states = <&CPU_SLEEP_1>;
 182                         #cooling-cells = <2>;
 183                         dynamic-power-coefficient = <277>;
 184                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                         capacity-dmips-mhz = <535>;
 187                 };
 188
 189                 a53_1: cpu@101 {
 190                         compatible = "arm,cortex-a53";
 191                         reg = <0x101>;
 192                         device_type = "cpu";
 193                         power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
 194                         next-level-cache = <&L2_CA53>;
 195                         enable-method = "psci";
 196                         cpu-idle-states = <&CPU_SLEEP_1>;
 197                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                         capacity-dmips-mhz = <535>;
 200                 };
 201
 202                 a53_2: cpu@102 {
 203                         compatible = "arm,cortex-a53";
 204                         reg = <0x102>;
 205                         device_type = "cpu";
 206                         power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
 207                         next-level-cache = <&L2_CA53>;
 208                         enable-method = "psci";
 209                         cpu-idle-states = <&CPU_SLEEP_1>;
 210                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 211                         operating-points-v2 = <&cluster1_opp>;
 212                         capacity-dmips-mhz = <535>;
 213                 };
 214
 215                 a53_3: cpu@103 {
 216                         compatible = "arm,cortex-a53";
 217                         reg = <0x103>;
 218                         device_type = "cpu";
 219                         power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
 220                         next-level-cache = <&L2_CA53>;
 221                         enable-method = "psci";
 222                         cpu-idle-states = <&CPU_SLEEP_1>;
 223                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 224                         operating-points-v2 = <&cluster1_opp>;
 225                         capacity-dmips-mhz = <535>;
 226                 };
 227
 228                 L2_CA57: cache-controller-0 {
 229                         compatible = "cache";
 230                         power-domains = <&sysc R8A77961_PD_CA57_SCU>;
 231                         cache-unified;
 232                         cache-level = <2>;
 233                 };
 234
 235                 L2_CA53: cache-controller-1 {
 236                         compatible = "cache";
 237                         power-domains = <&sysc R8A77961_PD_CA53_SCU>;
 238                         cache-unified;
 239                         cache-level = <2>;
 240                 };
 241
 242                 idle-states {
 243                         entry-method = "psci";
 244
 245                         CPU_SLEEP_0: cpu-sleep-0 {
 246                                 compatible = "arm,idle-state";
 247                                 arm,psci-suspend-param = <0x0010000>;
 248                                 local-timer-stop;
 249                                 entry-latency-us = <400>;
 250                                 exit-latency-us = <500>;
 251                                 min-residency-us = <4000>;
 252                         };
 253
 254                         CPU_SLEEP_1: cpu-sleep-1 {
 255                                 compatible = "arm,idle-state";
 256                                 arm,psci-suspend-param = <0x0010000>;
 257                                 local-timer-stop;
 258                                 entry-latency-us = <700>;
 259                                 exit-latency-us = <700>;
 260                                 min-residency-us = <5000>;
 261                         };
 262                 };
 263         };
 264
 265         extal_clk: extal {
 266                 compatible = "fixed-clock";
 267                 #clock-cells = <0>;
 268                 /* This value must be overridden by the board */
 269                 clock-frequency = <0>;
 270         };
 271
 272         extalr_clk: extalr {
 273                 compatible = "fixed-clock";
 274                 #clock-cells = <0>;
 275                 /* This value must be overridden by the board */
 276                 clock-frequency = <0>;
 277         };
 278
 279         /* External PCIe clock - can be overridden by the board */
 280         pcie_bus_clk: pcie_bus {
 281                 compatible = "fixed-clock";
 282                 #clock-cells = <0>;
 283                 clock-frequency = <0>;
 284         };
 285
 286         pmu_a53 {
 287                 compatible = "arm,cortex-a53-pmu";
 288                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 289                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 290                                       <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 291                                       <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 292                 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
 293         };
 294
 295         pmu_a57 {
 296                 compatible = "arm,cortex-a57-pmu";
 297                 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 298                                       <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 299                 interrupt-affinity = <&a57_0>, <&a57_1>;
 300         };
 301
 302         psci {
 303                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 304                 method = "smc";
 305         };
 306
 307         /* External SCIF clock - to be overridden by boards that provide it */
 308         scif_clk: scif {
 309                 compatible = "fixed-clock";
 310                 #clock-cells = <0>;
 311                 clock-frequency = <0>;
 312         };
 313
 314         soc {
 315                 compatible = "simple-bus";
 316                 interrupt-parent = <&gic>;
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 ranges;
 320
 321                 rwdt: watchdog@e6020000 {
 322                         reg = <0 0xe6020000 0 0x0c>;
 323                         /* placeholder */
 324                 };
 325
 326                 gpio2: gpio@e6052000 {
 327                         reg = <0 0xe6052000 0 0x50>;
 328                         #gpio-cells = <2>;
 329                         gpio-controller;
 330                         #interrupt-cells = <2>;
 331                         interrupt-controller;
 332                         /* placeholder */
 333                 };
 334
 335                 gpio3: gpio@e6053000 {
 336                         reg = <0 0xe6053000 0 0x50>;
 337                         #gpio-cells = <2>;
 338                         gpio-controller;
 339                         #interrupt-cells = <2>;
 340                         interrupt-controller;
 341                         /* placeholder */
 342                 };
 343
 344                 gpio4: gpio@e6054000 {
 345                         reg = <0 0xe6054000 0 0x50>;
 346                         #gpio-cells = <2>;
 347                         gpio-controller;
 348                         #interrupt-cells = <2>;
 349                         interrupt-controller;
 350                         /* placeholder */
 351                 };
 352
 353                 gpio5: gpio@e6055000 {
 354                         reg = <0 0xe6055000 0 0x50>;
 355                         #gpio-cells = <2>;
 356                         gpio-controller;
 357                         #interrupt-cells = <2>;
 358                         interrupt-controller;
 359                         /* placeholder */
 360                 };
 361
 362                 gpio6: gpio@e6055400 {
 363                         reg = <0 0xe6055400 0 0x50>;
 364                         #gpio-cells = <2>;
 365                         gpio-controller;
 366                         #interrupt-cells = <2>;
 367                         interrupt-controller;
 368                         /* placeholder */
 369                 };
 370
 371                 pfc: pin-controller@e6060000 {
 372                         compatible = "renesas,pfc-r8a77961";
 373                         reg = <0 0xe6060000 0 0x50c>;
 374                 };
 375
 376                 cpg: clock-controller@e6150000 {
 377                         compatible = "renesas,r8a77961-cpg-mssr";
 378                         reg = <0 0xe6150000 0 0x1000>;
 379                         clocks = <&extal_clk>, <&extalr_clk>;
 380                         clock-names = "extal", "extalr";
 381                         #clock-cells = <2>;
 382                         #power-domain-cells = <0>;
 383                         #reset-cells = <1>;
 384                 };
 385
 386                 rst: reset-controller@e6160000 {
 387                         compatible = "renesas,r8a77961-rst";
 388                         reg = <0 0xe6160000 0 0x0200>;
 389                 };
 390
 391                 sysc: system-controller@e6180000 {
 392                         compatible = "renesas,r8a77961-sysc";
 393                         reg = <0 0xe6180000 0 0x0400>;
 394                         #power-domain-cells = <1>;
 395                 };
 396
 397                 intc_ex: interrupt-controller@e61c0000 {
 398                         #interrupt-cells = <2>;
 399                         interrupt-controller;
 400                         reg = <0 0xe61c0000 0 0x200>;
 401                         /* placeholder */
 402                 };
 403
 404                 i2c2: i2c@e6510000 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         reg = <0 0xe6510000 0 0x40>;
 408                         /* placeholder */
 409                 };
 410
 411                 i2c4: i2c@e66d8000 {
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         reg = <0 0xe66d8000 0 0x40>;
 415                         /* placeholder */
 416                 };
 417
 418                 i2c_dvfs: i2c@e60b0000 {
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         reg = <0 0xe60b0000 0 0x425>;
 422                         /* placeholder */
 423                 };
 424
 425                 hscif1: serial@e6550000 {
 426                         reg = <0 0xe6550000 0 0x60>;
 427                         /* placeholder */
 428                 };
 429
 430                 hsusb: usb@e6590000 {
 431                         reg = <0 0xe6590000 0 0x200>;
 432                         /* placeholder */
 433                 };
 434
 435                 usb3_phy0: usb-phy@e65ee000 {
 436                         reg = <0 0xe65ee000 0 0x90>;
 437                         #phy-cells = <0>;
 438                         /* placeholder */
 439                 };
 440
 441                 avb: ethernet@e6800000 {
 442                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         /* placeholder */
 446                 };
 447
 448                 pwm1: pwm@e6e31000 {
 449                         reg = <0 0xe6e31000 0 8>;
 450                         #pwm-cells = <2>;
 451                         /* placeholder */
 452                 };
 453
 454                 scif1: serial@e6e68000 {
 455                         reg = <0 0xe6e68000 0 64>;
 456                         /* placeholder */
 457                 };
 458
 459                 scif2: serial@e6e88000 {
 460                         compatible = "renesas,scif-r8a77961",
 461                                      "renesas,rcar-gen3-scif", "renesas,scif";
 462                         reg = <0 0xe6e88000 0 64>;
 463                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&cpg CPG_MOD 310>,
 465                                  <&cpg CPG_CORE R8A77961_CLK_S3D1>,
 466                                  <&scif_clk>;
 467                         clock-names = "fck", "brg_int", "scif_clk";
 468                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 469                         resets = <&cpg 310>;
 470                         status = "disabled";
 471                 };
 472
 473                 vin0: video@e6ef0000 {
 474                         reg = <0 0xe6ef0000 0 0x1000>;
 475                         /* placeholder */
 476                 };
 477
 478                 vin1: video@e6ef1000 {
 479                         reg = <0 0xe6ef1000 0 0x1000>;
 480                         /* placeholder */
 481                 };
 482
 483                 vin2: video@e6ef2000 {
 484                         reg = <0 0xe6ef2000 0 0x1000>;
 485                         /* placeholder */
 486                 };
 487
 488                 vin3: video@e6ef3000 {
 489                         reg = <0 0xe6ef3000 0 0x1000>;
 490                         /* placeholder */
 491                 };
 492
 493                 vin4: video@e6ef4000 {
 494                         reg = <0 0xe6ef4000 0 0x1000>;
 495                         /* placeholder */
 496                 };
 497
 498                 vin5: video@e6ef5000 {
 499                         reg = <0 0xe6ef5000 0 0x1000>;
 500                         /* placeholder */
 501                 };
 502
 503                 vin6: video@e6ef6000 {
 504                         reg = <0 0xe6ef6000 0 0x1000>;
 505                         /* placeholder */
 506                 };
 507
 508                 vin7: video@e6ef7000 {
 509                         reg = <0 0xe6ef7000 0 0x1000>;
 510                         /* placeholder */
 511                 };
 512
 513                 rcar_sound: sound@ec500000 {
 514                         reg = <0 0xec500000 0 0x1000>, /* SCU */
 515                               <0 0xec5a0000 0 0x100>,  /* ADG */
 516                               <0 0xec540000 0 0x1000>, /* SSIU */
 517                               <0 0xec541000 0 0x280>,  /* SSI */
 518                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
 519                         /* placeholder */
 520                         rcar_sound,dvc {
 521                                 dvc0: dvc-0 { };
 522                                 dvc1: dvc-1 { };
 523                         };
 524
 525                         rcar_sound,src {
 526                                 src0: src-0 { };
 527                                 src1: src-1 { };
 528                         };
 529
 530                         rcar_sound,ssi {
 531                                 ssi0: ssi-0 { };
 532                                 ssi1: ssi-1 { };
 533                         };
 534                 };
 535
 536                 xhci0: usb@ee000000 {
 537                         reg = <0 0xee000000 0 0xc00>;
 538                         /* placeholder */
 539                 };
 540
 541                 usb3_peri0: usb@ee020000 {
 542                         reg = <0 0xee020000 0 0x400>;
 543                         /* placeholder */
 544                 };
 545
 546                 ohci0: usb@ee080000 {
 547                         reg = <0 0xee080000 0 0x100>;
 548                         /* placeholder */
 549                 };
 550
 551                 ohci1: usb@ee0a0000 {
 552                         reg = <0 0xee0a0000 0 0x100>;
 553                         /* placeholder */
 554                 };
 555
 556                 ehci0: usb@ee080100 {
 557                         reg = <0 0xee080100 0 0x100>;
 558                         /* placeholder */
 559                 };
 560
 561                 ehci1: usb@ee0a0100 {
 562                         reg = <0 0xee0a0100 0 0x100>;
 563                         /* placeholder */
 564                 };
 565
 566                 usb2_phy0: usb-phy@ee080200 {
 567                         reg = <0 0xee080200 0 0x700>;
 568                         /* placeholder */
 569                 };
 570
 571                 usb2_phy1: usb-phy@ee0a0200 {
 572                         reg = <0 0xee0a0200 0 0x700>;
 573                         /* placeholder */
 574                 };
 575
 576                 sdhi0: sd@ee100000 {
 577                         reg = <0 0xee100000 0 0x2000>;
 578                         /* placeholder */
 579                 };
 580
 581                 sdhi2: sd@ee140000 {
 582                         reg = <0 0xee140000 0 0x2000>;
 583                         /* placeholder */
 584                 };
 585
 586                 sdhi3: sd@ee160000 {
 587                         reg = <0 0xee160000 0 0x2000>;
 588                         /* placeholder */
 589                 };
 590
 591                 gic: interrupt-controller@f1010000 {
 592                         compatible = "arm,gic-400";
 593                         #interrupt-cells = <3>;
 594                         #address-cells = <0>;
 595                         interrupt-controller;
 596                         reg = <0x0 0xf1010000 0 0x1000>,
 597                               <0x0 0xf1020000 0 0x20000>,
 598                               <0x0 0xf1040000 0 0x20000>,
 599                               <0x0 0xf1060000 0 0x20000>;
 600                         interrupts = <GIC_PPI 9
 601                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 602                         clocks = <&cpg CPG_MOD 408>;
 603                         clock-names = "clk";
 604                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 605                         resets = <&cpg 408>;
 606                 };
 607
 608                 pciec0: pcie@fe000000 {
 609                         reg = <0 0xfe000000 0 0x80000>;
 610                         /* placeholder */
 611                 };
 612
 613                 pciec1: pcie@ee800000 {
 614                         reg = <0 0xee800000 0 0x80000>;
 615                         /* placeholder */
 616                 };
 617
 618                 csi20: csi2@fea80000 {
 619                         reg = <0 0xfea80000 0 0x10000>;
 620                         /* placeholder */
 621
 622                         ports {
 623                                 #address-cells = <1>;
 624                                 #size-cells = <0>;
 625
 626                                 port@1 {
 627                                         #address-cells = <1>;
 628                                         #size-cells = <0>;
 629                                         reg = <1>;
 630                                 };
 631                         };
 632                 };
 633
 634                 csi40: csi2@feaa0000 {
 635                         reg = <0 0xfeaa0000 0 0x10000>;
 636                         /* placeholder */
 637
 638                         ports {
 639                                 #address-cells = <1>;
 640                                 #size-cells = <0>;
 641
 642                                 port@1 {
 643                                         #address-cells = <1>;
 644                                         #size-cells = <0>;
 645
 646                                         reg = <1>;
 647                                 };
 648                         };
 649                 };
 650
 651                 hdmi0: hdmi@fead0000 {
 652                         reg = <0 0xfead0000 0 0x10000>;
 653                         /* placeholder */
 654
 655                         ports {
 656                                 #address-cells = <1>;
 657                                 #size-cells = <0>;
 658                                 port@0 {
 659                                         reg = <0>;
 660                                 };
 661                                 port@1 {
 662                                         reg = <1>;
 663                                 };
 664                                 port@2 {
 665                                         /* HDMI sound */
 666                                         reg = <2>;
 667                                 };
 668                         };
 669                 };
 670
 671                 du: display@feb00000 {
 672                         reg = <0 0xfeb00000 0 0x70000>;
 673                         /* placeholder */
 674
 675                         ports {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678
 679                                 port@0 {
 680                                         reg = <0>;
 681                                         du_out_rgb: endpoint {
 682                                         };
 683                                 };
 684                                 port@1 {
 685                                         reg = <1>;
 686                                         du_out_hdmi0: endpoint {
 687                                         };
 688                                 };
 689                                 port@2 {
 690                                         reg = <2>;
 691                                         du_out_lvds0: endpoint {
 692                                         };
 693                                 };
 694                         };
 695                 };
 696
 697                 prr: chipid@fff00044 {
 698                         compatible = "renesas,prr";
 699                         reg = <0 0xfff00044 0 4>;
 700                 };
 701         };
 702
 703         timer {
 704                 compatible = "arm,armv8-timer";
 705                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 706                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 707                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 708                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 709         };
 710
 711         /* External USB clocks - can be overridden by the board */
 712         usb3s0_clk: usb3s0 {
 713                 compatible = "fixed-clock";
 714                 #clock-cells = <0>;
 715                 clock-frequency = <0>;
 716         };
 717
 718         usb_extal_clk: usb_extal {
 719                 compatible = "fixed-clock";
 720                 #clock-cells = <0>;
 721                 clock-frequency = <0>;
 722         };
 723 };