2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
29 #include <asm/pgtable-hwdef.h>
30 #include <asm/cputype.h>
31 #include <asm/ptrace.h>
32 #include <asm/thread_info.h>
35 * Stack pushing/popping (register pairs only). Equivalent to store decrement
36 * before, load increment after.
38 .macro push, xreg1, xreg2
39 stp \xreg1, \xreg2, [sp, #-16]!
42 .macro pop, xreg1, xreg2
43 ldp \xreg1, \xreg2, [sp], #16
47 * Enable and disable interrupts.
57 .macro save_and_disable_irq, flags
62 .macro restore_irq, flags
67 * Enable and disable debug exceptions.
77 .macro disable_step_tsk, flgs, tmp
78 tbz \flgs, #TIF_SINGLESTEP, 9990f
82 isb // Synchronise with enable_dbg
86 .macro enable_step_tsk, flgs, tmp
87 tbz \flgs, #TIF_SINGLESTEP, 9990f
96 * Enable both debug exceptions and interrupts. This is likely to be
97 * faster than two daifclr operations, since writes to this register
98 * are self-synchronising.
100 .macro enable_dbg_and_irq
101 msr daifclr, #(8 | 2)
105 * SMP data memory barrier
121 * Emit an entry into the exception table
123 .macro _asm_extable, from, to
124 .pushsection __ex_table, "a"
126 .long (\from - .), (\to - .)
130 #define USER(l, x...) \
132 _asm_extable 9999b, l
137 lr .req x30 // link register
148 * Select code when configured for BE.
150 #ifdef CONFIG_CPU_BIG_ENDIAN
151 #define CPU_BE(code...) code
153 #define CPU_BE(code...)
157 * Select code when configured for LE.
159 #ifdef CONFIG_CPU_BIG_ENDIAN
160 #define CPU_LE(code...)
162 #define CPU_LE(code...) code
166 * Define a macro that constructs a 64-bit value by concatenating two
167 * 32-bit registers. Note that on big endian systems the order of the
168 * registers is swapped.
170 #ifndef CONFIG_CPU_BIG_ENDIAN
171 .macro regs_to_64, rd, lbits, hbits
173 .macro regs_to_64, rd, hbits, lbits
175 orr \rd, \lbits, \hbits, lsl #32
179 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
180 * <symbol> is within the range +/- 4 GB of the PC.
183 * @dst: destination register (64 bit wide)
184 * @sym: name of the symbol
185 * @tmp: optional scratch register to be used if <dst> == sp, which
186 * is not allowed in an adrp instruction
188 .macro adr_l, dst, sym, tmp=
191 add \dst, \dst, :lo12:\sym
194 add \dst, \tmp, :lo12:\sym
199 * @dst: destination register (32 or 64 bit wide)
200 * @sym: name of the symbol
201 * @tmp: optional 64-bit scratch register to be used if <dst> is a
202 * 32-bit wide register, in which case it cannot be used to hold
205 .macro ldr_l, dst, sym, tmp=
208 ldr \dst, [\dst, :lo12:\sym]
211 ldr \dst, [\tmp, :lo12:\sym]
216 * @src: source register (32 or 64 bit wide)
217 * @sym: name of the symbol
218 * @tmp: mandatory 64-bit scratch register to calculate the address
219 * while <src> needs to be preserved.
221 .macro str_l, src, sym, tmp
223 str \src, [\tmp, :lo12:\sym]
227 * @dst: Result of per_cpu(sym, smp_processor_id())
228 * @sym: The name of the per-cpu variable
229 * @tmp: scratch register
231 .macro adr_this_cpu, dst, sym, tmp
238 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id()))
239 * @sym: The name of the per-cpu variable
240 * @tmp: scratch register
242 .macro ldr_this_cpu dst, sym, tmp
245 ldr \dst, [\dst, \tmp]
249 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
251 .macro vma_vm_mm, rd, rn
252 ldr \rd, [\rn, #VMA_VM_MM]
256 * mmid - get context id from mm pointer (mm->context.id)
259 ldr \rd, [\rn, #MM_CONTEXT_ID]
263 * dcache_line_size - get the minimum D-cache line size from the CTR register.
265 .macro dcache_line_size, reg, tmp
266 mrs \tmp, ctr_el0 // read CTR
267 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
268 mov \reg, #4 // bytes per word
269 lsl \reg, \reg, \tmp // actual cache line size
273 * icache_line_size - get the minimum I-cache line size from the CTR register.
275 .macro icache_line_size, reg, tmp
276 mrs \tmp, ctr_el0 // read CTR
277 and \tmp, \tmp, #0xf // cache line size encoding
278 mov \reg, #4 // bytes per word
279 lsl \reg, \reg, \tmp // actual cache line size
283 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
285 .macro tcr_set_idmap_t0sz, valreg, tmpreg
286 #ifndef CONFIG_ARM64_VA_BITS_48
287 ldr_l \tmpreg, idmap_t0sz
288 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
293 * Macro to perform a data cache maintenance for the interval
294 * [kaddr, kaddr + size)
296 * op: operation passed to dc instruction
297 * domain: domain used in dsb instruciton
298 * kaddr: starting virtual address of the region
299 * size: size of the region
300 * Corrupts: kaddr, size, tmp1, tmp2
302 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
303 dcache_line_size \tmp1, \tmp2
304 add \size, \kaddr, \size
306 bic \kaddr, \kaddr, \tmp2
308 .if (\op == cvau || \op == cvac)
309 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
317 add \kaddr, \kaddr, \tmp1
324 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
326 .macro reset_pmuserenr_el0, tmpreg
327 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
328 sbfx \tmpreg, \tmpreg, #8, #4
329 cmp \tmpreg, #1 // Skip if no PMU present
331 msr pmuserenr_el0, xzr // Disable PMU access from EL0
336 * copy_page - copy src to dest using temp registers t1-t8
338 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
339 9998: ldp \t1, \t2, [\src]
340 ldp \t3, \t4, [\src, #16]
341 ldp \t5, \t6, [\src, #32]
342 ldp \t7, \t8, [\src, #48]
344 stnp \t1, \t2, [\dest]
345 stnp \t3, \t4, [\dest, #16]
346 stnp \t5, \t6, [\dest, #32]
347 stnp \t7, \t8, [\dest, #48]
348 add \dest, \dest, #64
349 tst \src, #(PAGE_SIZE - 1)
354 * Annotate a function as position independent, i.e., safe to be called before
355 * the kernel virtual mapping is activated.
357 #define ENDPIPROC(x) \
359 .type __pi_##x, %function; \
361 .size __pi_##x, . - x; \
365 * Emit a 64-bit absolute little endian symbol reference in a way that
366 * ensures that it will be resolved at build time, even when building a
367 * PIE binary. This requires cooperation from the linker script, which
368 * must emit the lo32/hi32 halves individually.
376 * mov_q - move an immediate constant into a 64-bit register using
377 * between 2 and 4 movz/movk instructions (depending on the
378 * magnitude and sign of the operand)
380 .macro mov_q, reg, val
381 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
382 movz \reg, :abs_g1_s:\val
384 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
385 movz \reg, :abs_g2_s:\val
387 movz \reg, :abs_g3:\val
388 movk \reg, :abs_g2_nc:\val
390 movk \reg, :abs_g1_nc:\val
392 movk \reg, :abs_g0_nc:\val
396 * Return the current thread_info.
398 .macro get_thread_info, rd
403 * Check the MIDR_EL1 of the current CPU for a given model and a range of
404 * variant/revision. See asm/cputype.h for the macros used below.
406 * model: MIDR_CPU_PART of CPU
407 * rv_min: Minimum of MIDR_CPU_VAR_REV()
408 * rv_max: Maximum of MIDR_CPU_VAR_REV()
409 * res: Result register.
410 * tmp1, tmp2, tmp3: Temporary registers
412 * Corrupts: res, tmp1, tmp2, tmp3
413 * Returns: 0, if the CPU id doesn't match. Non-zero otherwise
415 .macro cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3
417 mov_q \tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)
418 mov_q \tmp2, MIDR_CPU_PART_MASK
419 and \tmp3, \res, \tmp2 // Extract model
420 and \tmp1, \res, \tmp1 // rev & variant
424 cbz \res, .Ldone\@ // Model matches ?
426 .if (\rv_min != 0) // Skip min check if rv_min == 0
430 .endif // \rv_min != 0
431 /* Skip rv_max check if rv_min == rv_max && rv_min != 0 */
432 .if ((\rv_min != \rv_max) || \rv_min == 0)
436 and \res, \res, \tmp2
441 #endif /* __ASM_ASSEMBLER_H */