arch/arm64/include/asm/cpufeature.h

   1 /*
   2  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __ASM_CPUFEATURE_H
  10 #define __ASM_CPUFEATURE_H
  11
  12 #include <asm/hwcap.h>
  13 #include <asm/sysreg.h>
  14
  15 /*
  16  * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
  17  * in the kernel and for user space to keep track of which optional features
  18  * are supported by the current system. So let's map feature 'x' to HWCAP_x.
  19  * Note that HWCAP_x constants are bit fields so we need to take the log.
  20  */
  21
  22 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
  23 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
  24
  25 #define ARM64_WORKAROUND_CLEAN_CACHE            0
  26 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
  27 #define ARM64_WORKAROUND_845719                 2
  28 #define ARM64_HAS_SYSREG_GIC_CPUIF              3
  29 #define ARM64_HAS_PAN                           4
  30 #define ARM64_HAS_LSE_ATOMICS                   5
  31 #define ARM64_WORKAROUND_CAVIUM_23154           6
  32 #define ARM64_WORKAROUND_834220                 7
  33 #define ARM64_HAS_NO_HW_PREFETCH                8
  34 #define ARM64_HAS_UAO                           9
  35 #define ARM64_ALT_PAN_NOT_UAO                   10
  36
  37 #define ARM64_WORKAROUND_CAVIUM_27456           11
  38 #define ARM64_HAS_VIRT_HOST_EXTN                12
  39 #define ARM64_HARDEN_BRANCH_PREDICTOR           13
  40 #define ARM64_UNMAP_KERNEL_AT_EL0               14
  41 #define ARM64_HAS_32BIT_EL0                     15
  42 #define ARM64_NCAPS                             16
  43
  44 #ifndef __ASSEMBLY__
  45
  46 #include <linux/kernel.h>
  47
  48 extern const char *machine_name;
  49
  50 /* CPU feature register tracking */
  51 enum ftr_type {
  52         FTR_EXACT,      /* Use a predefined safe value */
  53         FTR_LOWER_SAFE, /* Smaller value is safe */
  54         FTR_HIGHER_SAFE,/* Bigger value is safe */
  55 };
  56
  57 #define FTR_STRICT      true    /* SANITY check strict matching required */
  58 #define FTR_NONSTRICT   false   /* SANITY check ignored */
  59
  60 #define FTR_SIGNED      true    /* Value should be treated as signed */
  61 #define FTR_UNSIGNED    false   /* Value should be treated as unsigned */
  62
  63 struct arm64_ftr_bits {
  64         bool            sign;   /* Value is signed ? */
  65         bool            strict; /* CPU Sanity check: strict matching required ? */
  66         enum ftr_type   type;
  67         u8              shift;
  68         u8              width;
  69         s64             safe_val; /* safe value for discrete features */
  70 };
  71
  72 /*
  73  * @arm64_ftr_reg - Feature register
  74  * @strict_mask         Bits which should match across all CPUs for sanity.
  75  * @sys_val             Safe value across the CPUs (system view)
  76  */
  77 struct arm64_ftr_reg {
  78         u32                     sys_id;
  79         const char              *name;
  80         u64                     strict_mask;
  81         u64                     sys_val;
  82         struct arm64_ftr_bits   *ftr_bits;
  83 };
  84
  85 struct arm64_cpu_capabilities {
  86         const char *desc;
  87         u16 capability;
  88         bool (*matches)(const struct arm64_cpu_capabilities *);
  89         int (*enable)(void *);          /* Called on all active CPUs */
  90         union {
  91                 struct {        /* To be used for erratum handling only */
  92                         u32 midr_model;
  93                         u32 midr_range_min, midr_range_max;
  94                 };
  95
  96                 struct {        /* Feature register checking */
  97                         u32 sys_reg;
  98                         int field_pos;
  99                         int min_field_value;
 100                         int hwcap_type;
 101                         unsigned long hwcap;
 102                 };
 103         };
 104 };
 105
 106 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 107
 108 static inline bool cpu_have_feature(unsigned int num)
 109 {
 110         return elf_hwcap & (1UL << num);
 111 }
 112
 113 static inline bool cpus_have_cap(unsigned int num)
 114 {
 115         if (num >= ARM64_NCAPS)
 116                 return false;
 117         return test_bit(num, cpu_hwcaps);
 118 }
 119
 120 static inline void cpus_set_cap(unsigned int num)
 121 {
 122         if (num >= ARM64_NCAPS)
 123                 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
 124                         num, ARM64_NCAPS);
 125         else
 126                 __set_bit(num, cpu_hwcaps);
 127 }
 128
 129 static inline int __attribute_const__
 130 cpuid_feature_extract_field_width(u64 features, int field, int width)
 131 {
 132         return (s64)(features << (64 - width - field)) >> (64 - width);
 133 }
 134
 135 static inline int __attribute_const__
 136 cpuid_feature_extract_field(u64 features, int field)
 137 {
 138         return cpuid_feature_extract_field_width(features, field, 4);
 139 }
 140
 141 static inline unsigned int __attribute_const__
 142 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
 143 {
 144         return (u64)(features << (64 - width - field)) >> (64 - width);
 145 }
 146
 147 static inline unsigned int __attribute_const__
 148 cpuid_feature_extract_unsigned_field(u64 features, int field)
 149 {
 150         return cpuid_feature_extract_unsigned_field_width(features, field, 4);
 151 }
 152
 153 static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
 154 {
 155         return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
 156 }
 157
 158 static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
 159 {
 160         return ftrp->sign ?
 161                 cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :
 162                 cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);
 163 }
 164
 165 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 166 {
 167         return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
 168                 cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
 169 }
 170
 171 void __init setup_cpu_features(void);
 172
 173 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 174                             const char *info);
 175 void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
 176 void check_local_cpu_errata(void);
 177 void __init enable_errata_workarounds(void);
 178
 179 #ifdef CONFIG_HOTPLUG_CPU
 180 void verify_local_cpu_capabilities(void);
 181 #else
 182 static inline void verify_local_cpu_capabilities(void)
 183 {
 184 }
 185 #endif
 186
 187 u64 read_system_reg(u32 id);
 188
 189 static inline bool cpu_supports_mixed_endian_el0(void)
 190 {
 191         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1));
 192 }
 193
 194 static inline bool system_supports_32bit_el0(void)
 195 {
 196         return cpus_have_cap(ARM64_HAS_32BIT_EL0);
 197 }
 198
 199 static inline bool system_supports_mixed_endian_el0(void)
 200 {
 201         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
 202 }
 203
 204 static inline bool system_uses_ttbr0_pan(void)
 205 {
 206         return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
 207                 !cpus_have_cap(ARM64_HAS_PAN);
 208 }
 209
 210 #endif /* __ASSEMBLY__ */
 211
 212 #endif