arch/arm64/include/asm/cpufeature.h

   1 /*
   2  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __ASM_CPUFEATURE_H
  10 #define __ASM_CPUFEATURE_H
  11
  12 #include <asm/hwcap.h>
  13 #include <asm/sysreg.h>
  14
  15 /*
  16  * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
  17  * in the kernel and for user space to keep track of which optional features
  18  * are supported by the current system. So let's map feature 'x' to HWCAP_x.
  19  * Note that HWCAP_x constants are bit fields so we need to take the log.
  20  */
  21
  22 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
  23 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
  24
  25 #define ARM64_WORKAROUND_CLEAN_CACHE            0
  26 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
  27 #define ARM64_WORKAROUND_845719                 2
  28 #define ARM64_HAS_SYSREG_GIC_CPUIF              3
  29 #define ARM64_HAS_PAN                           4
  30 #define ARM64_HAS_LSE_ATOMICS                   5
  31 #define ARM64_WORKAROUND_CAVIUM_23154           6
  32 #define ARM64_WORKAROUND_834220                 7
  33 #define ARM64_HAS_NO_HW_PREFETCH                8
  34 #define ARM64_HAS_UAO                           9
  35 #define ARM64_ALT_PAN_NOT_UAO                   10
  36 #define ARM64_HAS_VIRT_HOST_EXTN                11
  37 #define ARM64_WORKAROUND_CAVIUM_27456           12
  38 #define ARM64_HAS_32BIT_EL0                     13
  39 #define ARM64_UNMAP_KERNEL_AT_EL0               23
  40
  41 #define ARM64_NCAPS                             24
  42
  43 #ifndef __ASSEMBLY__
  44
  45 #include <linux/kernel.h>
  46
  47 /* CPU feature register tracking */
  48 enum ftr_type {
  49         FTR_EXACT,                      /* Use a predefined safe value */
  50         FTR_LOWER_SAFE,                 /* Smaller value is safe */
  51         FTR_HIGHER_SAFE,                /* Bigger value is safe */
  52         FTR_HIGHER_OR_ZERO_SAFE,        /* Bigger value is safe, but 0 is biggest */
  53 };
  54
  55 #define FTR_STRICT      true    /* SANITY check strict matching required */
  56 #define FTR_NONSTRICT   false   /* SANITY check ignored */
  57
  58 #define FTR_SIGNED      true    /* Value should be treated as signed */
  59 #define FTR_UNSIGNED    false   /* Value should be treated as unsigned */
  60
  61 struct arm64_ftr_bits {
  62         bool            sign;   /* Value is signed ? */
  63         bool            strict; /* CPU Sanity check: strict matching required ? */
  64         enum ftr_type   type;
  65         u8              shift;
  66         u8              width;
  67         s64             safe_val; /* safe value for discrete features */
  68 };
  69
  70 /*
  71  * @arm64_ftr_reg - Feature register
  72  * @strict_mask         Bits which should match across all CPUs for sanity.
  73  * @sys_val             Safe value across the CPUs (system view)
  74  */
  75 struct arm64_ftr_reg {
  76         u32                     sys_id;
  77         const char              *name;
  78         u64                     strict_mask;
  79         u64                     sys_val;
  80         struct arm64_ftr_bits   *ftr_bits;
  81 };
  82
  83 struct arm64_cpu_capabilities {
  84         const char *desc;
  85         u16 capability;
  86         bool (*matches)(const struct arm64_cpu_capabilities *);
  87         int (*enable)(void *);          /* Called on all active CPUs */
  88         union {
  89                 struct {        /* To be used for erratum handling only */
  90                         u32 midr_model;
  91                         u32 midr_range_min, midr_range_max;
  92                 };
  93
  94                 struct {        /* Feature register checking */
  95                         u32 sys_reg;
  96                         int field_pos;
  97                         int min_field_value;
  98                         int hwcap_type;
  99                         unsigned long hwcap;
 100                 };
 101         };
 102 };
 103
 104 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 105
 106 static inline bool cpu_have_feature(unsigned int num)
 107 {
 108         return elf_hwcap & (1UL << num);
 109 }
 110
 111 static inline bool cpus_have_cap(unsigned int num)
 112 {
 113         if (num >= ARM64_NCAPS)
 114                 return false;
 115         return test_bit(num, cpu_hwcaps);
 116 }
 117
 118 static inline void cpus_set_cap(unsigned int num)
 119 {
 120         if (num >= ARM64_NCAPS)
 121                 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
 122                         num, ARM64_NCAPS);
 123         else
 124                 __set_bit(num, cpu_hwcaps);
 125 }
 126
 127 static inline int __attribute_const__
 128 cpuid_feature_extract_field_width(u64 features, int field, int width)
 129 {
 130         return (s64)(features << (64 - width - field)) >> (64 - width);
 131 }
 132
 133 static inline int __attribute_const__
 134 cpuid_feature_extract_field(u64 features, int field)
 135 {
 136         return cpuid_feature_extract_field_width(features, field, 4);
 137 }
 138
 139 static inline unsigned int __attribute_const__
 140 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
 141 {
 142         return (u64)(features << (64 - width - field)) >> (64 - width);
 143 }
 144
 145 static inline unsigned int __attribute_const__
 146 cpuid_feature_extract_unsigned_field(u64 features, int field)
 147 {
 148         return cpuid_feature_extract_unsigned_field_width(features, field, 4);
 149 }
 150
 151 static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
 152 {
 153         return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
 154 }
 155
 156 static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
 157 {
 158         return ftrp->sign ?
 159                 cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :
 160                 cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);
 161 }
 162
 163 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 164 {
 165         return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
 166                 cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
 167 }
 168
 169 void __init setup_cpu_features(void);
 170
 171 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 172                             const char *info);
 173 void check_local_cpu_errata(void);
 174
 175 #ifdef CONFIG_HOTPLUG_CPU
 176 void verify_local_cpu_capabilities(void);
 177 #else
 178 static inline void verify_local_cpu_capabilities(void)
 179 {
 180 }
 181 #endif
 182
 183 u64 read_system_reg(u32 id);
 184
 185 static inline bool cpu_supports_mixed_endian_el0(void)
 186 {
 187         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1));
 188 }
 189
 190 static inline bool system_supports_32bit_el0(void)
 191 {
 192         return cpus_have_cap(ARM64_HAS_32BIT_EL0);
 193 }
 194
 195 static inline bool system_supports_mixed_endian_el0(void)
 196 {
 197         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
 198 }
 199
 200 static inline bool system_uses_ttbr0_pan(void)
 201 {
 202         return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
 203                 !cpus_have_cap(ARM64_HAS_PAN);
 204 }
 205
 206 #endif /* __ASSEMBLY__ */
 207
 208 #endif