arch/arm64/include/asm/cpufeature.h

   1 /*
   2  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __ASM_CPUFEATURE_H
  10 #define __ASM_CPUFEATURE_H
  11
  12 #include <asm/hwcap.h>
  13 #include <asm/sysreg.h>
  14
  15 /*
  16  * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
  17  * in the kernel and for user space to keep track of which optional features
  18  * are supported by the current system. So let's map feature 'x' to HWCAP_x.
  19  * Note that HWCAP_x constants are bit fields so we need to take the log.
  20  */
  21
  22 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
  23 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
  24
  25 #define ARM64_WORKAROUND_CLEAN_CACHE            0
  26 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
  27 #define ARM64_WORKAROUND_845719                 2
  28 #define ARM64_HAS_SYSREG_GIC_CPUIF              3
  29 #define ARM64_HAS_PAN                           4
  30 #define ARM64_HAS_LSE_ATOMICS                   5
  31 #define ARM64_WORKAROUND_CAVIUM_23154           6
  32 #define ARM64_WORKAROUND_834220                 7
  33 #define ARM64_HAS_NO_HW_PREFETCH                8
  34 #define ARM64_HAS_UAO                           9
  35 #define ARM64_ALT_PAN_NOT_UAO                   10
  36 #define ARM64_HAS_VIRT_HOST_EXTN                11
  37 #define ARM64_WORKAROUND_CAVIUM_27456           12
  38 #define ARM64_HAS_32BIT_EL0                     13
  39 #define ARM64_UNMAP_KERNEL_AT_EL0               23
  40
  41 #define ARM64_NCAPS                             24
  42
  43 #ifndef __ASSEMBLY__
  44
  45 #include <linux/kernel.h>
  46
  47 /* CPU feature register tracking */
  48 enum ftr_type {
  49         FTR_EXACT,      /* Use a predefined safe value */
  50         FTR_LOWER_SAFE, /* Smaller value is safe */
  51         FTR_HIGHER_SAFE,/* Bigger value is safe */
  52 };
  53
  54 #define FTR_STRICT      true    /* SANITY check strict matching required */
  55 #define FTR_NONSTRICT   false   /* SANITY check ignored */
  56
  57 #define FTR_SIGNED      true    /* Value should be treated as signed */
  58 #define FTR_UNSIGNED    false   /* Value should be treated as unsigned */
  59
  60 struct arm64_ftr_bits {
  61         bool            sign;   /* Value is signed ? */
  62         bool            strict; /* CPU Sanity check: strict matching required ? */
  63         enum ftr_type   type;
  64         u8              shift;
  65         u8              width;
  66         s64             safe_val; /* safe value for discrete features */
  67 };
  68
  69 /*
  70  * @arm64_ftr_reg - Feature register
  71  * @strict_mask         Bits which should match across all CPUs for sanity.
  72  * @sys_val             Safe value across the CPUs (system view)
  73  */
  74 struct arm64_ftr_reg {
  75         u32                     sys_id;
  76         const char              *name;
  77         u64                     strict_mask;
  78         u64                     sys_val;
  79         struct arm64_ftr_bits   *ftr_bits;
  80 };
  81
  82 struct arm64_cpu_capabilities {
  83         const char *desc;
  84         u16 capability;
  85         bool (*matches)(const struct arm64_cpu_capabilities *);
  86         int (*enable)(void *);          /* Called on all active CPUs */
  87         union {
  88                 struct {        /* To be used for erratum handling only */
  89                         u32 midr_model;
  90                         u32 midr_range_min, midr_range_max;
  91                 };
  92
  93                 struct {        /* Feature register checking */
  94                         u32 sys_reg;
  95                         int field_pos;
  96                         int min_field_value;
  97                         int hwcap_type;
  98                         unsigned long hwcap;
  99                 };
 100         };
 101 };
 102
 103 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 104
 105 static inline bool cpu_have_feature(unsigned int num)
 106 {
 107         return elf_hwcap & (1UL << num);
 108 }
 109
 110 static inline bool cpus_have_cap(unsigned int num)
 111 {
 112         if (num >= ARM64_NCAPS)
 113                 return false;
 114         return test_bit(num, cpu_hwcaps);
 115 }
 116
 117 static inline void cpus_set_cap(unsigned int num)
 118 {
 119         if (num >= ARM64_NCAPS)
 120                 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
 121                         num, ARM64_NCAPS);
 122         else
 123                 __set_bit(num, cpu_hwcaps);
 124 }
 125
 126 static inline int __attribute_const__
 127 cpuid_feature_extract_field_width(u64 features, int field, int width)
 128 {
 129         return (s64)(features << (64 - width - field)) >> (64 - width);
 130 }
 131
 132 static inline int __attribute_const__
 133 cpuid_feature_extract_field(u64 features, int field)
 134 {
 135         return cpuid_feature_extract_field_width(features, field, 4);
 136 }
 137
 138 static inline unsigned int __attribute_const__
 139 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
 140 {
 141         return (u64)(features << (64 - width - field)) >> (64 - width);
 142 }
 143
 144 static inline unsigned int __attribute_const__
 145 cpuid_feature_extract_unsigned_field(u64 features, int field)
 146 {
 147         return cpuid_feature_extract_unsigned_field_width(features, field, 4);
 148 }
 149
 150 static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
 151 {
 152         return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
 153 }
 154
 155 static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
 156 {
 157         return ftrp->sign ?
 158                 cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :
 159                 cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);
 160 }
 161
 162 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 163 {
 164         return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
 165                 cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
 166 }
 167
 168 void __init setup_cpu_features(void);
 169
 170 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 171                             const char *info);
 172 void check_local_cpu_errata(void);
 173
 174 #ifdef CONFIG_HOTPLUG_CPU
 175 void verify_local_cpu_capabilities(void);
 176 #else
 177 static inline void verify_local_cpu_capabilities(void)
 178 {
 179 }
 180 #endif
 181
 182 u64 read_system_reg(u32 id);
 183
 184 static inline bool cpu_supports_mixed_endian_el0(void)
 185 {
 186         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1));
 187 }
 188
 189 static inline bool system_supports_32bit_el0(void)
 190 {
 191         return cpus_have_cap(ARM64_HAS_32BIT_EL0);
 192 }
 193
 194 static inline bool system_supports_mixed_endian_el0(void)
 195 {
 196         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
 197 }
 198
 199 static inline bool system_uses_ttbr0_pan(void)
 200 {
 201         return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
 202                 !cpus_have_cap(ARM64_HAS_PAN);
 203 }
 204
 205 #endif /* __ASSEMBLY__ */
 206
 207 #endif