1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
9 #include <asm/proc-fns.h>
11 #include <asm/memory.h>
12 #include <asm/pgtable-hwdef.h>
13 #include <asm/pgtable-prot.h>
14 #include <asm/tlbflush.h>
19 * VMALLOC_START: beginning of the kernel vmalloc space
20 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
23 #define VMALLOC_START (MODULES_END)
24 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
26 #define FIRST_USER_ADDRESS 0UL
30 #include <asm/cmpxchg.h>
31 #include <asm/fixmap.h>
32 #include <linux/mmdebug.h>
33 #include <linux/mm_types.h>
34 #include <linux/sched.h>
36 extern struct page *vmemmap;
38 extern void __pte_error(const char *file, int line, unsigned long val);
39 extern void __pmd_error(const char *file, int line, unsigned long val);
40 extern void __pud_error(const char *file, int line, unsigned long val);
41 extern void __pgd_error(const char *file, int line, unsigned long val);
43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
46 /* Set stride and tlb_level in flush_*_tlb_range */
47 #define flush_pmd_tlb_range(vma, addr, end) \
48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
49 #define flush_pud_tlb_range(vma, addr, end) \
50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
54 * ZERO_PAGE is a global shared page that is always zero: used
55 * for zero-mapped memory areas etc..
57 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
58 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
60 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
63 * Macros to convert between a physical address and its placement in a
64 * page table entry, taking care of 52-bit addresses.
66 #ifdef CONFIG_ARM64_PA_BITS_52
67 #define __pte_to_phys(pte) \
68 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36))
69 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK)
71 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
72 #define __phys_to_pte_val(phys) (phys)
75 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
76 #define pfn_pte(pfn,prot) \
77 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
79 #define pte_none(pte) (!pte_val(pte))
80 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
81 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
84 * The following only work if pte_present(). Undefined behaviour otherwise.
86 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
87 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
88 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
89 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
90 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
91 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
92 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
94 #define pte_cont_addr_end(addr, end) \
95 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
96 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
99 #define pmd_cont_addr_end(addr, end) \
100 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
101 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
104 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
105 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
106 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
108 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
109 #define pte_valid_not_user(pte) \
110 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
111 #define pte_valid_young(pte) \
112 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
113 #define pte_valid_user(pte) \
114 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
117 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
118 * so that we don't erroneously return false for pages that have been
119 * remapped as PROT_NONE but are yet to be flushed from the TLB.
121 #define pte_accessible(mm, pte) \
122 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
125 * p??_access_permitted() is true for valid user mappings (subject to the
126 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit
129 #define pte_access_permitted(pte, write) \
130 (pte_valid_user(pte) && (!(write) || pte_write(pte)))
131 #define pmd_access_permitted(pmd, write) \
132 (pte_access_permitted(pmd_pte(pmd), (write)))
133 #define pud_access_permitted(pud, write) \
134 (pte_access_permitted(pud_pte(pud), (write)))
136 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
138 pte_val(pte) &= ~pgprot_val(prot);
142 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
144 pte_val(pte) |= pgprot_val(prot);
148 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
150 pmd_val(pmd) &= ~pgprot_val(prot);
154 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
156 pmd_val(pmd) |= pgprot_val(prot);
160 static inline pte_t pte_wrprotect(pte_t pte)
162 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
163 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
167 static inline pte_t pte_mkwrite(pte_t pte)
169 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
170 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
174 static inline pte_t pte_mkclean(pte_t pte)
176 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
177 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
182 static inline pte_t pte_mkdirty(pte_t pte)
184 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
187 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
192 static inline pte_t pte_mkold(pte_t pte)
194 return clear_pte_bit(pte, __pgprot(PTE_AF));
197 static inline pte_t pte_mkyoung(pte_t pte)
199 return set_pte_bit(pte, __pgprot(PTE_AF));
202 static inline pte_t pte_mkspecial(pte_t pte)
204 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
207 static inline pte_t pte_mkcont(pte_t pte)
209 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
210 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
213 static inline pte_t pte_mknoncont(pte_t pte)
215 return clear_pte_bit(pte, __pgprot(PTE_CONT));
218 static inline pte_t pte_mkpresent(pte_t pte)
220 return set_pte_bit(pte, __pgprot(PTE_VALID));
223 static inline pmd_t pmd_mkcont(pmd_t pmd)
225 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
228 static inline pte_t pte_mkdevmap(pte_t pte)
230 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
233 static inline void set_pte(pte_t *ptep, pte_t pte)
235 WRITE_ONCE(*ptep, pte);
238 * Only if the new pte is valid and kernel, otherwise TLB maintenance
239 * or update_mmu_cache() have the necessary barriers.
241 if (pte_valid_not_user(pte)) {
247 extern void __sync_icache_dcache(pte_t pteval);
250 * PTE bits configuration in the presence of hardware Dirty Bit Management
251 * (PTE_WRITE == PTE_DBM):
253 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
259 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
260 * the page fault mechanism. Checking the dirty status of a pte becomes:
262 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
265 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
270 if (!IS_ENABLED(CONFIG_DEBUG_VM))
273 old_pte = READ_ONCE(*ptep);
275 if (!pte_valid(old_pte) || !pte_valid(pte))
277 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
281 * Check for potential race with hardware updates of the pte
282 * (ptep_set_access_flags safely changes valid ptes without going
283 * through an invalid entry).
285 VM_WARN_ONCE(!pte_young(pte),
286 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
287 __func__, pte_val(old_pte), pte_val(pte));
288 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
289 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
290 __func__, pte_val(old_pte), pte_val(pte));
293 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
294 pte_t *ptep, pte_t pte)
296 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
297 __sync_icache_dcache(pte);
299 __check_racy_pte_update(mm, ptep, pte);
305 * Huge pte definitions.
307 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
310 * Hugetlb definitions.
312 #define HUGE_MAX_HSTATE 4
313 #define HPAGE_SHIFT PMD_SHIFT
314 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
315 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
316 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
318 static inline pte_t pgd_pte(pgd_t pgd)
320 return __pte(pgd_val(pgd));
323 static inline pte_t p4d_pte(p4d_t p4d)
325 return __pte(p4d_val(p4d));
328 static inline pte_t pud_pte(pud_t pud)
330 return __pte(pud_val(pud));
333 static inline pud_t pte_pud(pte_t pte)
335 return __pud(pte_val(pte));
338 static inline pmd_t pud_pmd(pud_t pud)
340 return __pmd(pud_val(pud));
343 static inline pte_t pmd_pte(pmd_t pmd)
345 return __pte(pmd_val(pmd));
348 static inline pmd_t pte_pmd(pte_t pte)
350 return __pmd(pte_val(pte));
353 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
355 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
358 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
360 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
363 #ifdef CONFIG_NUMA_BALANCING
365 * See the comment in include/linux/pgtable.h
367 static inline int pte_protnone(pte_t pte)
369 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
372 static inline int pmd_protnone(pmd_t pmd)
374 return pte_protnone(pmd_pte(pmd));
378 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
380 static inline int pmd_present(pmd_t pmd)
382 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
389 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
390 static inline int pmd_trans_huge(pmd_t pmd)
392 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
394 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
396 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
397 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
398 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
399 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
400 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
401 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
402 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
403 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
404 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
406 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
408 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
409 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
414 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
416 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
418 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
420 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
421 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
423 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
425 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
428 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
429 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
430 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
431 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
432 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
434 #define pud_young(pud) pte_young(pud_pte(pud))
435 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
436 #define pud_write(pud) pte_write(pud_pte(pud))
438 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
440 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
441 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
442 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
443 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
445 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
447 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
448 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
450 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
451 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
453 #define __pgprot_modify(prot,mask,bits) \
454 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
456 #define pgprot_nx(prot) \
457 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
460 * Mark the prot value as uncacheable and unbufferable.
462 #define pgprot_noncached(prot) \
463 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
464 #define pgprot_writecombine(prot) \
465 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
466 #define pgprot_device(prot) \
467 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
469 * DMA allocations for non-coherent devices use what the Arm architecture calls
470 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
471 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
472 * is intended for MMIO and thus forbids speculation, preserves access size,
473 * requires strict alignment and can also force write responses to come from the
476 #define pgprot_dmacoherent(prot) \
477 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
478 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
480 #define __HAVE_PHYS_MEM_ACCESS_PROT
482 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
483 unsigned long size, pgprot_t vma_prot);
485 #define pmd_none(pmd) (!pmd_val(pmd))
487 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT))
489 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
491 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
493 #define pmd_leaf(pmd) pmd_sect(pmd)
495 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
496 static inline bool pud_sect(pud_t pud) { return false; }
497 static inline bool pud_table(pud_t pud) { return true; }
499 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
501 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
505 extern pgd_t init_pg_dir[PTRS_PER_PGD];
506 extern pgd_t init_pg_end[];
507 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
508 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
509 extern pgd_t idmap_pg_end[];
510 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
512 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
514 static inline bool in_swapper_pgdir(void *addr)
516 return ((unsigned long)addr & PAGE_MASK) ==
517 ((unsigned long)swapper_pg_dir & PAGE_MASK);
520 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
522 #ifdef __PAGETABLE_PMD_FOLDED
523 if (in_swapper_pgdir(pmdp)) {
524 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
527 #endif /* __PAGETABLE_PMD_FOLDED */
529 WRITE_ONCE(*pmdp, pmd);
531 if (pmd_valid(pmd)) {
537 static inline void pmd_clear(pmd_t *pmdp)
539 set_pmd(pmdp, __pmd(0));
542 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
544 return __pmd_to_phys(pmd);
547 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
549 return (unsigned long)__va(pmd_page_paddr(pmd));
552 /* Find an entry in the third-level page table. */
553 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
555 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
556 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
557 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
559 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
561 /* use ONLY for statically allocated translation tables */
562 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
565 * Conversion functions: convert a page and protection to a page entry,
566 * and a page entry and page directory to the page they refer to.
568 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
570 #if CONFIG_PGTABLE_LEVELS > 2
572 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
574 #define pud_none(pud) (!pud_val(pud))
575 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
576 #define pud_present(pud) pte_present(pud_pte(pud))
577 #define pud_leaf(pud) pud_sect(pud)
578 #define pud_valid(pud) pte_valid(pud_pte(pud))
580 static inline void set_pud(pud_t *pudp, pud_t pud)
582 #ifdef __PAGETABLE_PUD_FOLDED
583 if (in_swapper_pgdir(pudp)) {
584 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
587 #endif /* __PAGETABLE_PUD_FOLDED */
589 WRITE_ONCE(*pudp, pud);
591 if (pud_valid(pud)) {
597 static inline void pud_clear(pud_t *pudp)
599 set_pud(pudp, __pud(0));
602 static inline phys_addr_t pud_page_paddr(pud_t pud)
604 return __pud_to_phys(pud);
607 static inline unsigned long pud_page_vaddr(pud_t pud)
609 return (unsigned long)__va(pud_page_paddr(pud));
612 /* Find an entry in the second-level page table. */
613 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
615 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
616 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
617 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
619 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
621 /* use ONLY for statically allocated translation tables */
622 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
626 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
628 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
629 #define pmd_set_fixmap(addr) NULL
630 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
631 #define pmd_clear_fixmap()
633 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
635 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
637 #if CONFIG_PGTABLE_LEVELS > 3
639 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
641 #define p4d_none(p4d) (!p4d_val(p4d))
642 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
643 #define p4d_present(p4d) (p4d_val(p4d))
645 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
647 if (in_swapper_pgdir(p4dp)) {
648 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
652 WRITE_ONCE(*p4dp, p4d);
657 static inline void p4d_clear(p4d_t *p4dp)
659 set_p4d(p4dp, __p4d(0));
662 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
664 return __p4d_to_phys(p4d);
667 static inline unsigned long p4d_page_vaddr(p4d_t p4d)
669 return (unsigned long)__va(p4d_page_paddr(p4d));
672 /* Find an entry in the frst-level page table. */
673 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
675 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
676 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
677 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
679 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
681 /* use ONLY for statically allocated translation tables */
682 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
686 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
687 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
689 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
690 #define pud_set_fixmap(addr) NULL
691 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
692 #define pud_clear_fixmap()
694 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
696 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
698 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
700 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
701 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
703 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
705 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
706 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP;
707 /* preserve the hardware dirty information */
708 if (pte_hw_dirty(pte))
709 pte = pte_mkdirty(pte);
710 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
714 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
716 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
719 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
720 extern int ptep_set_access_flags(struct vm_area_struct *vma,
721 unsigned long address, pte_t *ptep,
722 pte_t entry, int dirty);
724 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
725 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
726 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
727 unsigned long address, pmd_t *pmdp,
728 pmd_t entry, int dirty)
730 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
733 static inline int pud_devmap(pud_t pud)
738 static inline int pgd_devmap(pgd_t pgd)
745 * Atomic pte/pmd modifications.
747 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
748 static inline int __ptep_test_and_clear_young(pte_t *ptep)
752 pte = READ_ONCE(*ptep);
755 pte = pte_mkold(pte);
756 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
757 pte_val(old_pte), pte_val(pte));
758 } while (pte_val(pte) != pte_val(old_pte));
760 return pte_young(pte);
763 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
764 unsigned long address,
767 return __ptep_test_and_clear_young(ptep);
770 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
771 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
772 unsigned long address, pte_t *ptep)
774 int young = ptep_test_and_clear_young(vma, address, ptep);
778 * We can elide the trailing DSB here since the worst that can
779 * happen is that a CPU continues to use the young entry in its
780 * TLB and we mistakenly reclaim the associated page. The
781 * window for such an event is bounded by the next
782 * context-switch, which provides a DSB to complete the TLB
785 flush_tlb_page_nosync(vma, address);
791 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
792 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
793 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
794 unsigned long address,
797 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
799 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
801 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
802 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
803 unsigned long address, pte_t *ptep)
805 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
808 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
809 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
810 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
811 unsigned long address, pmd_t *pmdp)
813 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
815 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
818 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
819 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
821 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
822 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
826 pte = READ_ONCE(*ptep);
830 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
831 * clear), set the PTE_DIRTY bit.
833 if (pte_hw_dirty(pte))
834 pte = pte_mkdirty(pte);
835 pte = pte_wrprotect(pte);
836 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
837 pte_val(old_pte), pte_val(pte));
838 } while (pte_val(pte) != pte_val(old_pte));
841 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
842 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
843 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
844 unsigned long address, pmd_t *pmdp)
846 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
849 #define pmdp_establish pmdp_establish
850 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
851 unsigned long address, pmd_t *pmdp, pmd_t pmd)
853 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
858 * Encode and decode a swap entry:
859 * bits 0-1: present (must be zero)
860 * bits 2-7: swap type
861 * bits 8-57: swap offset
862 * bit 58: PTE_PROT_NONE (must be zero)
864 #define __SWP_TYPE_SHIFT 2
865 #define __SWP_TYPE_BITS 6
866 #define __SWP_OFFSET_BITS 50
867 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
868 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
869 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
871 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
872 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
873 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
875 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
876 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
879 * Ensure that there are not more swap files than can be encoded in the kernel
882 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
884 extern int kern_addr_valid(unsigned long addr);
887 * On AArch64, the cache coherency is handled via the set_pte_at() function.
889 static inline void update_mmu_cache(struct vm_area_struct *vma,
890 unsigned long addr, pte_t *ptep)
893 * We don't do anything here, so there's a very small chance of
894 * us retaking a user fault which we just fixed up. The alternative
895 * is doing a dsb(ishst), but that penalises the fastpath.
899 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
901 #ifdef CONFIG_ARM64_PA_BITS_52
902 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
904 #define phys_to_ttbr(addr) (addr)
908 * On arm64 without hardware Access Flag, copying from user will fail because
909 * the pte is old and cannot be marked young. So we always end up with zeroed
910 * page after fork() + CoW for pfn mappings. We don't always have a
911 * hardware-managed access flag on arm64.
913 static inline bool arch_faults_on_old_pte(void)
915 WARN_ON(preemptible());
917 return !cpu_has_hw_af();
919 #define arch_faults_on_old_pte arch_faults_on_old_pte
921 #endif /* !__ASSEMBLY__ */
923 #endif /* __ASM_PGTABLE_H */