2 * Based on arch/arm/include/asm/processor.h
4 * Copyright (C) 1995-1999 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_PROCESSOR_H
20 #define __ASM_PROCESSOR_H
22 #define KERNEL_DS UL(-1)
23 #define USER_DS ((UL(1) << MAX_USER_VA_BITS) - 1)
26 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
27 * no point in shifting all network buffers by 2 bytes just to make some IP
28 * header fields appear aligned in memory, potentially sacrificing some DMA
29 * performance on some platforms.
31 #define NET_IP_ALIGN 0
36 #include <linux/build_bug.h>
37 #include <linux/cache.h>
38 #include <linux/init.h>
39 #include <linux/stddef.h>
40 #include <linux/string.h>
42 #include <asm/alternative.h>
43 #include <asm/cpufeature.h>
44 #include <asm/hw_breakpoint.h>
46 #include <asm/pgtable-hwdef.h>
47 #include <asm/ptrace.h>
48 #include <asm/types.h>
51 * TASK_SIZE - the maximum size of a user space task.
52 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
55 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS)
57 extern u64 vabits_user;
58 #define TASK_SIZE_64 (UL(1) << vabits_user)
61 #define TASK_SIZE_32 UL(0x100000000)
62 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
63 TASK_SIZE_32 : TASK_SIZE_64)
64 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
65 TASK_SIZE_32 : TASK_SIZE_64)
66 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
67 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
69 #define TASK_SIZE TASK_SIZE_64
70 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
71 #endif /* CONFIG_COMPAT */
73 #ifdef CONFIG_ARM64_FORCE_52BIT
74 #define STACK_TOP_MAX TASK_SIZE_64
75 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
77 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
78 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
79 #endif /* CONFIG_ARM64_FORCE_52BIT */
82 #define AARCH32_VECTORS_BASE 0xffff0000
83 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
84 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
86 #define STACK_TOP STACK_TOP_MAX
87 #endif /* CONFIG_COMPAT */
89 #ifndef CONFIG_ARM64_FORCE_52BIT
90 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
93 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
94 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
96 #endif /* CONFIG_ARM64_FORCE_52BIT */
98 extern phys_addr_t arm64_dma_phys_limit;
99 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
102 #ifdef CONFIG_HAVE_HW_BREAKPOINT
103 /* Have we suspended stepping by a debugger? */
105 /* Allow breakpoints and watchpoints to be disabled for this thread. */
108 /* Hardware breakpoints pinned to this task. */
109 struct perf_event *hbp_break[ARM_MAX_BRP];
110 struct perf_event *hbp_watch[ARM_MAX_WRP];
130 struct thread_struct {
131 struct cpu_context cpu_context; /* cpu context */
134 * Whitelisted fields for hardened usercopy:
135 * Maintainers must ensure manually that this contains no
139 unsigned long tp_value; /* TLS register */
140 unsigned long tp2_value;
141 struct user_fpsimd_state fpsimd_state;
144 unsigned int fpsimd_cpu;
145 void *sve_state; /* SVE registers, if any */
146 unsigned int sve_vl; /* SVE vector length */
147 unsigned int sve_vl_onexec; /* SVE vl after next exec */
148 unsigned long fault_address; /* fault info */
149 unsigned long fault_code; /* ESR_EL1 value */
150 struct debug_info debug; /* debugging */
153 static inline void arch_thread_struct_whitelist(unsigned long *offset,
156 /* Verify that there is no padding among the whitelisted fields: */
157 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
158 sizeof_field(struct thread_struct, uw.tp_value) +
159 sizeof_field(struct thread_struct, uw.tp2_value) +
160 sizeof_field(struct thread_struct, uw.fpsimd_state));
162 *offset = offsetof(struct thread_struct, uw);
163 *size = sizeof_field(struct thread_struct, uw);
167 #define task_user_tls(t) \
169 unsigned long *__tls; \
170 if (is_compat_thread(task_thread_info(t))) \
171 __tls = &(t)->thread.uw.tp2_value; \
173 __tls = &(t)->thread.uw.tp_value; \
177 #define task_user_tls(t) (&(t)->thread.uw.tp_value)
180 /* Sync TPIDR_EL0 back to thread_struct for current */
181 void tls_preserve_current_state(void);
183 #define INIT_THREAD { \
184 .fpsimd_cpu = NR_CPUS, \
187 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
189 memset(regs, 0, sizeof(*regs));
190 forget_syscall(regs);
194 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
197 start_thread_common(regs, pc);
198 regs->pstate = PSR_MODE_EL0t;
200 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
201 regs->pstate |= PSR_SSBS_BIT;
207 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
210 start_thread_common(regs, pc);
211 regs->pstate = PSR_AA32_MODE_USR;
213 regs->pstate |= PSR_AA32_T_BIT;
216 regs->pstate |= PSR_AA32_E_BIT;
219 if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
220 regs->pstate |= PSR_AA32_SSBS_BIT;
222 regs->compat_sp = sp;
226 /* Forward declaration, a strange C thing */
229 /* Free all resources held by a thread. */
230 extern void release_thread(struct task_struct *);
232 unsigned long get_wchan(struct task_struct *p);
234 static inline void cpu_relax(void)
236 asm volatile("yield" ::: "memory");
239 /* Thread switching */
240 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
241 struct task_struct *next);
243 #define task_pt_regs(p) \
244 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
246 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
247 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
250 * Prefetching support
252 #define ARCH_HAS_PREFETCH
253 static inline void prefetch(const void *ptr)
255 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
258 #define ARCH_HAS_PREFETCHW
259 static inline void prefetchw(const void *ptr)
261 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
264 #define ARCH_HAS_SPINLOCK_PREFETCH
265 static inline void spin_lock_prefetch(const void *ptr)
267 asm volatile(ARM64_LSE_ATOMIC_INSN(
268 "prfm pstl1strm, %a0",
269 "nop") : : "p" (ptr));
272 #define HAVE_ARCH_PICK_MMAP_LAYOUT
276 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
277 extern void __init minsigstksz_setup(void);
280 * Not at the top of the file due to a direct #include cycle between
281 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
282 * ensures that contents of processor.h are visible to fpsimd.h even if
283 * processor.h is included first.
285 * These prctl helpers are the only things in this file that require
286 * fpsimd.h. The core code expects them to be in this header.
288 #include <asm/fpsimd.h>
290 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
291 #define SVE_SET_VL(arg) sve_set_current_vl(arg)
292 #define SVE_GET_VL() sve_get_current_vl()
295 * For CONFIG_GCC_PLUGIN_STACKLEAK
297 * These need to be macros because otherwise we get stuck in a nightmare
298 * of header definitions for the use of task_stack_page.
301 #define current_top_of_stack() \
303 struct stack_info _info; \
304 BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info)); \
307 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, NULL))
309 #endif /* __ASSEMBLY__ */
310 #endif /* __ASM_PROCESSOR_H */