1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
8 #define pr_fmt(fmt) "CPU features: " fmt
10 #include <linux/bsearch.h>
11 #include <linux/cpumask.h>
12 #include <linux/crash_dump.h>
13 #include <linux/sort.h>
14 #include <linux/stop_machine.h>
15 #include <linux/types.h>
17 #include <linux/cpu.h>
19 #include <asm/cpufeature.h>
20 #include <asm/cpu_ops.h>
21 #include <asm/fpsimd.h>
22 #include <asm/mmu_context.h>
23 #include <asm/processor.h>
24 #include <asm/sysreg.h>
25 #include <asm/traps.h>
28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
29 static unsigned long elf_hwcap __read_mostly;
32 #define COMPAT_ELF_HWCAP_DEFAULT \
33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
36 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
37 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
40 unsigned int compat_elf_hwcap2 __read_mostly;
43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
44 EXPORT_SYMBOL(cpu_hwcaps);
45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
47 /* Need also bit for ARM64_CB_PATCH */
48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
50 bool arm64_use_ng_mappings = false;
51 EXPORT_SYMBOL(arm64_use_ng_mappings);
54 * Flag to indicate if we have computed the system wide
55 * capabilities based on the boot time active CPUs. This
56 * will be used to determine if a new booting CPU should
57 * go through the verification process to make sure that it
58 * supports the system capabilities, without using a hotplug
61 static bool sys_caps_initialised;
63 static inline void set_sys_caps_initialised(void)
65 sys_caps_initialised = true;
68 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
70 /* file-wide pr_fmt adds "CPU features: " prefix */
71 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
75 static struct notifier_block cpu_hwcaps_notifier = {
76 .notifier_call = dump_cpu_hwcaps
79 static int __init register_cpu_hwcaps_dumper(void)
81 atomic_notifier_chain_register(&panic_notifier_list,
82 &cpu_hwcaps_notifier);
85 __initcall(register_cpu_hwcaps_dumper);
87 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
88 EXPORT_SYMBOL(cpu_hwcap_keys);
90 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
98 .safe_val = SAFE_VAL, \
101 /* Define a feature with unsigned values */
102 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
103 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
105 /* Define a feature with a signed value */
106 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
107 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
109 #define ARM64_FTR_END \
114 /* meta feature for alternatives */
115 static bool __maybe_unused
116 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
118 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
121 * NOTE: Any changes to the visibility of features should be kept in
122 * sync with the documentation of the CPU feature register ABI.
124 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
140 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
141 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
144 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
146 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
147 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
148 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
149 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
150 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
151 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
152 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
153 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
154 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
158 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
161 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
162 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
163 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
164 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
166 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
167 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
168 /* Linux doesn't care about the EL3 */
169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
176 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
181 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
182 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
183 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
185 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
187 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
189 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
191 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
195 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
197 * We already refuse to boot CPUs that don't support our configured
198 * page size, so we can only detect mismatches for a page size other
199 * than the one we're currently using. Unfortunately, SoCs like this
200 * exist in the wild so, even though we don't like it, we'll have to go
201 * along with it and treat them as non-strict.
203 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
204 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
205 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
208 /* Linux shouldn't care about secure memory */
209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
213 * Differing PARange is fine as long as all peripherals and memory are mapped
214 * within the minimum PARange of all CPUs
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
220 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
230 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
242 static const struct arm64_ftr_bits ftr_ctr[] = {
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
250 * Linux can handle differing I-cache policies. Userspace JITs will
251 * make use of *minLine.
252 * If we have differing I-cache policies, report it as the weakest - VIPT.
254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
259 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
260 .name = "SYS_CTR_EL0",
264 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
265 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
270 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
276 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
283 * We can instantiate multiple PMU instances with different levels
286 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
292 static const struct arm64_ftr_bits ftr_mvfr2[] = {
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
298 static const struct arm64_ftr_bits ftr_dczid[] = {
299 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
300 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
305 static const struct arm64_ftr_bits ftr_id_isar5[] = {
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
315 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
320 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
328 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
330 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
340 static const struct arm64_ftr_bits ftr_zcr[] = {
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
342 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
347 * Common ftr bits for a 32bit register with all hidden, strict
348 * attributes, with 4bit feature fields and a default safe value of
349 * 0. Covers the following 32bit registers:
350 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
352 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
364 /* Table for a single 32bit feature value */
365 static const struct arm64_ftr_bits ftr_single32[] = {
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
370 static const struct arm64_ftr_bits ftr_raz[] = {
374 #define ARM64_FTR_REG(id, table) { \
376 .reg = &(struct arm64_ftr_reg){ \
378 .ftr_bits = &((table)[0]), \
381 static const struct __ftr_reg_entry {
383 struct arm64_ftr_reg *reg;
384 } arm64_ftr_regs[] = {
386 /* Op1 = 0, CRn = 0, CRm = 1 */
387 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
388 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
389 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
390 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
391 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
392 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
393 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
395 /* Op1 = 0, CRn = 0, CRm = 2 */
396 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
397 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
398 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
399 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
400 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
401 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
402 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
404 /* Op1 = 0, CRn = 0, CRm = 3 */
405 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
406 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
407 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
409 /* Op1 = 0, CRn = 0, CRm = 4 */
410 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
411 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
412 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
414 /* Op1 = 0, CRn = 0, CRm = 5 */
415 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
416 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
418 /* Op1 = 0, CRn = 0, CRm = 6 */
419 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
420 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
422 /* Op1 = 0, CRn = 0, CRm = 7 */
423 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
424 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
425 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
427 /* Op1 = 0, CRn = 1, CRm = 2 */
428 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
430 /* Op1 = 3, CRn = 0, CRm = 0 */
431 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
432 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
434 /* Op1 = 3, CRn = 14, CRm = 0 */
435 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
438 static int search_cmp_ftr_reg(const void *id, const void *regp)
440 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
444 * get_arm64_ftr_reg - Lookup a feature register entry using its
445 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
446 * ascending order of sys_id , we use binary search to find a matching
449 * returns - Upon success, matching ftr_reg entry for id.
450 * - NULL on failure. It is upto the caller to decide
451 * the impact of a failure.
453 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
455 const struct __ftr_reg_entry *ret;
457 ret = bsearch((const void *)(unsigned long)sys_id,
459 ARRAY_SIZE(arm64_ftr_regs),
460 sizeof(arm64_ftr_regs[0]),
467 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
470 u64 mask = arm64_ftr_mask(ftrp);
473 reg |= (ftr_val << ftrp->shift) & mask;
477 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
482 switch (ftrp->type) {
484 ret = ftrp->safe_val;
487 ret = new < cur ? new : cur;
489 case FTR_HIGHER_OR_ZERO_SAFE:
493 case FTR_HIGHER_SAFE:
494 ret = new > cur ? new : cur;
503 static void __init sort_ftr_regs(void)
507 /* Check that the array is sorted so that we can do the binary search */
508 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
509 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
513 * Initialise the CPU feature register from Boot CPU values.
514 * Also initiliases the strict_mask for the register.
515 * Any bits that are not covered by an arm64_ftr_bits entry are considered
516 * RES0 for the system-wide value, and must strictly match.
518 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
521 u64 strict_mask = ~0x0ULL;
525 const struct arm64_ftr_bits *ftrp;
526 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
530 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
531 u64 ftr_mask = arm64_ftr_mask(ftrp);
532 s64 ftr_new = arm64_ftr_value(ftrp, new);
534 val = arm64_ftr_set_value(ftrp, val, ftr_new);
536 valid_mask |= ftr_mask;
538 strict_mask &= ~ftr_mask;
540 user_mask |= ftr_mask;
542 reg->user_val = arm64_ftr_set_value(ftrp,
550 reg->strict_mask = strict_mask;
551 reg->user_mask = user_mask;
554 extern const struct arm64_cpu_capabilities arm64_errata[];
555 static const struct arm64_cpu_capabilities arm64_features[];
558 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
560 for (; caps->matches; caps++) {
561 if (WARN(caps->capability >= ARM64_NCAPS,
562 "Invalid capability %d\n", caps->capability))
564 if (WARN(cpu_hwcaps_ptrs[caps->capability],
565 "Duplicate entry for capability %d\n",
568 cpu_hwcaps_ptrs[caps->capability] = caps;
572 static void __init init_cpu_hwcaps_indirect_list(void)
574 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
575 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
578 static void __init setup_boot_cpu_capabilities(void);
580 void __init init_cpu_features(struct cpuinfo_arm64 *info)
582 /* Before we start using the tables, make sure it is sorted */
585 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
586 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
587 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
588 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
589 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
590 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
591 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
592 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
593 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
594 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
595 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
596 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
597 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
599 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
600 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
601 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
602 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
603 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
604 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
605 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
606 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
607 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
608 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
609 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
610 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
611 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
612 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
613 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
614 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
615 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
618 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
619 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
624 * Initialize the indirect array of CPU hwcaps capabilities pointers
625 * before we handle the boot CPU below.
627 init_cpu_hwcaps_indirect_list();
630 * Detect and enable early CPU capabilities based on the boot CPU,
631 * after we have initialised the CPU feature infrastructure.
633 setup_boot_cpu_capabilities();
636 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
638 const struct arm64_ftr_bits *ftrp;
640 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
641 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
642 s64 ftr_new = arm64_ftr_value(ftrp, new);
644 if (ftr_cur == ftr_new)
646 /* Find a safe value */
647 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
648 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
653 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
655 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
658 update_cpu_ftr_reg(regp, val);
659 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
661 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
662 regp->name, boot, cpu, val);
667 * Update system wide CPU feature registers with the values from a
668 * non-boot CPU. Also performs SANITY checks to make sure that there
669 * aren't any insane variations from that of the boot CPU.
671 void update_cpu_features(int cpu,
672 struct cpuinfo_arm64 *info,
673 struct cpuinfo_arm64 *boot)
678 * The kernel can handle differing I-cache policies, but otherwise
679 * caches should look identical. Userspace JITs will make use of
682 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
683 info->reg_ctr, boot->reg_ctr);
686 * Userspace may perform DC ZVA instructions. Mismatched block sizes
687 * could result in too much or too little memory being zeroed if a
688 * process is preempted and migrated between CPUs.
690 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
691 info->reg_dczid, boot->reg_dczid);
693 /* If different, timekeeping will be broken (especially with KVM) */
694 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
695 info->reg_cntfrq, boot->reg_cntfrq);
698 * The kernel uses self-hosted debug features and expects CPUs to
699 * support identical debug features. We presently need CTX_CMPs, WRPs,
700 * and BRPs to be identical.
701 * ID_AA64DFR1 is currently RES0.
703 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
704 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
705 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
706 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
708 * Even in big.LITTLE, processors should be identical instruction-set
711 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
712 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
713 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
714 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
717 * Differing PARange support is fine as long as all peripherals and
718 * memory are mapped within the minimum PARange of all CPUs.
719 * Linux should not care about secure memory.
721 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
722 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
723 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
724 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
725 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
726 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
729 * EL3 is not our concern.
731 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
732 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
733 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
734 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
736 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
737 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
740 * If we have AArch32, we care about 32-bit features for compat.
741 * If the system doesn't support AArch32, don't update them.
743 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
744 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
746 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
747 info->reg_id_dfr0, boot->reg_id_dfr0);
748 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
749 info->reg_id_isar0, boot->reg_id_isar0);
750 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
751 info->reg_id_isar1, boot->reg_id_isar1);
752 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
753 info->reg_id_isar2, boot->reg_id_isar2);
754 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
755 info->reg_id_isar3, boot->reg_id_isar3);
756 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
757 info->reg_id_isar4, boot->reg_id_isar4);
758 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
759 info->reg_id_isar5, boot->reg_id_isar5);
762 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
763 * ACTLR formats could differ across CPUs and therefore would have to
764 * be trapped for virtualization anyway.
766 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
767 info->reg_id_mmfr0, boot->reg_id_mmfr0);
768 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
769 info->reg_id_mmfr1, boot->reg_id_mmfr1);
770 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
771 info->reg_id_mmfr2, boot->reg_id_mmfr2);
772 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
773 info->reg_id_mmfr3, boot->reg_id_mmfr3);
774 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
775 info->reg_id_pfr0, boot->reg_id_pfr0);
776 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
777 info->reg_id_pfr1, boot->reg_id_pfr1);
778 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
779 info->reg_mvfr0, boot->reg_mvfr0);
780 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
781 info->reg_mvfr1, boot->reg_mvfr1);
782 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
783 info->reg_mvfr2, boot->reg_mvfr2);
786 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
787 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
788 info->reg_zcr, boot->reg_zcr);
790 /* Probe vector lengths, unless we already gave up on SVE */
791 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
792 !sys_caps_initialised)
797 * Mismatched CPU features are a recipe for disaster. Don't even
798 * pretend to support them.
801 pr_warn_once("Unsupported CPU feature variation detected.\n");
802 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
806 u64 read_sanitised_ftr_reg(u32 id)
808 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
810 /* We shouldn't get a request for an unsupported register */
812 return regp->sys_val;
815 #define read_sysreg_case(r) \
816 case r: return read_sysreg_s(r)
819 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
820 * Read the system register on the current CPU
822 static u64 __read_sysreg_by_encoding(u32 sys_id)
825 read_sysreg_case(SYS_ID_PFR0_EL1);
826 read_sysreg_case(SYS_ID_PFR1_EL1);
827 read_sysreg_case(SYS_ID_DFR0_EL1);
828 read_sysreg_case(SYS_ID_MMFR0_EL1);
829 read_sysreg_case(SYS_ID_MMFR1_EL1);
830 read_sysreg_case(SYS_ID_MMFR2_EL1);
831 read_sysreg_case(SYS_ID_MMFR3_EL1);
832 read_sysreg_case(SYS_ID_ISAR0_EL1);
833 read_sysreg_case(SYS_ID_ISAR1_EL1);
834 read_sysreg_case(SYS_ID_ISAR2_EL1);
835 read_sysreg_case(SYS_ID_ISAR3_EL1);
836 read_sysreg_case(SYS_ID_ISAR4_EL1);
837 read_sysreg_case(SYS_ID_ISAR5_EL1);
838 read_sysreg_case(SYS_MVFR0_EL1);
839 read_sysreg_case(SYS_MVFR1_EL1);
840 read_sysreg_case(SYS_MVFR2_EL1);
842 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
843 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
844 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
845 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
846 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
847 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
848 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
849 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
850 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
851 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
853 read_sysreg_case(SYS_CNTFRQ_EL0);
854 read_sysreg_case(SYS_CTR_EL0);
855 read_sysreg_case(SYS_DCZID_EL0);
863 #include <linux/irqchip/arm-gic-v3.h>
866 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
868 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
870 return val >= entry->min_field_value;
874 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
878 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
879 if (scope == SCOPE_SYSTEM)
880 val = read_sanitised_ftr_reg(entry->sys_reg);
882 val = __read_sysreg_by_encoding(entry->sys_reg);
884 return feature_matches(val, entry);
887 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
891 if (!has_cpuid_feature(entry, scope))
894 has_sre = gic_enable_sre();
896 pr_warn_once("%s present but disabled by higher exception level\n",
902 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
904 u32 midr = read_cpuid_id();
906 /* Cavium ThunderX pass 1.x and 2.x */
907 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
908 MIDR_CPU_VAR_REV(0, 0),
909 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
912 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
914 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
916 return cpuid_feature_extract_signed_field(pfr0,
917 ID_AA64PFR0_FP_SHIFT) < 0;
920 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
925 if (scope == SCOPE_SYSTEM)
926 ctr = arm64_ftr_reg_ctrel0.sys_val;
928 ctr = read_cpuid_effective_cachetype();
930 return ctr & BIT(CTR_IDC_SHIFT);
933 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
936 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
937 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
938 * to the CTR_EL0 on this CPU and emulate it with the real/safe
941 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
942 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
945 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
950 if (scope == SCOPE_SYSTEM)
951 ctr = arm64_ftr_reg_ctrel0.sys_val;
953 ctr = read_cpuid_cachetype();
955 return ctr & BIT(CTR_DIC_SHIFT);
958 static bool __maybe_unused
959 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
962 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
963 * may share TLB entries with a CPU stuck in the crashed
966 if (is_kdump_kernel())
969 return has_cpuid_feature(entry, scope);
973 * This check is triggered during the early boot before the cpufeature
974 * is initialised. Checking the status on the local CPU allows the boot
975 * CPU to detect the need for non-global mappings and thus avoiding a
976 * pagetable re-write after all the CPUs are booted. This check will be
977 * anyway run on individual CPUs, allowing us to get the consistent
978 * state once the SMP CPUs are up and thus make the switch to non-global
979 * mappings if required.
981 bool kaslr_requires_kpti(void)
983 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
987 * E0PD does a similar job to KPTI so can be used instead
990 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
991 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
992 if (cpuid_feature_extract_unsigned_field(mmfr2,
993 ID_AA64MMFR2_E0PD_SHIFT))
998 * Systems affected by Cavium erratum 24756 are incompatible
1001 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1002 extern const struct midr_range cavium_erratum_27456_cpus[];
1004 if (is_midr_in_range_list(read_cpuid_id(),
1005 cavium_erratum_27456_cpus))
1009 return kaslr_offset() > 0;
1012 static bool __meltdown_safe = true;
1013 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1015 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1018 /* List of CPUs that are not vulnerable and don't need KPTI */
1019 static const struct midr_range kpti_safe_list[] = {
1020 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1021 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1022 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1023 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1024 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1025 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1026 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1027 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1028 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1029 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1032 char const *str = "kpti command line option";
1035 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1037 /* Defer to CPU feature registers */
1038 if (has_cpuid_feature(entry, scope))
1039 meltdown_safe = true;
1042 __meltdown_safe = false;
1045 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1046 * ThunderX leads to apparent I-cache corruption of kernel text, which
1047 * ends as well as you might imagine. Don't even try.
1049 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1050 str = "ARM64_WORKAROUND_CAVIUM_27456";
1054 /* Useful for KASLR robustness */
1055 if (kaslr_requires_kpti()) {
1056 if (!__kpti_forced) {
1062 if (cpu_mitigations_off() && !__kpti_forced) {
1063 str = "mitigations=off";
1067 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1068 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1073 if (__kpti_forced) {
1074 pr_info_once("kernel page table isolation forced %s by %s\n",
1075 __kpti_forced > 0 ? "ON" : "OFF", str);
1076 return __kpti_forced > 0;
1079 return !meltdown_safe;
1082 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1084 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1086 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1087 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1088 kpti_remap_fn *remap_fn;
1090 int cpu = smp_processor_id();
1093 * We don't need to rewrite the page-tables if either we've done
1094 * it already or we have KASLR enabled and therefore have not
1095 * created any global mappings at all.
1097 if (arm64_use_ng_mappings)
1100 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1102 cpu_install_idmap();
1103 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1104 cpu_uninstall_idmap();
1107 arm64_use_ng_mappings = true;
1113 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1116 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1118 static int __init parse_kpti(char *str)
1121 int ret = strtobool(str, &enabled);
1126 __kpti_forced = enabled ? 1 : -1;
1129 early_param("kpti", parse_kpti);
1131 #ifdef CONFIG_ARM64_HW_AFDBM
1132 static inline void __cpu_enable_hw_dbm(void)
1134 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1136 write_sysreg(tcr, tcr_el1);
1140 static bool cpu_has_broken_dbm(void)
1142 /* List of CPUs which have broken DBM support. */
1143 static const struct midr_range cpus[] = {
1144 #ifdef CONFIG_ARM64_ERRATUM_1024718
1145 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1150 return is_midr_in_range_list(read_cpuid_id(), cpus);
1153 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1155 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1156 !cpu_has_broken_dbm();
1159 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1161 if (cpu_can_use_dbm(cap))
1162 __cpu_enable_hw_dbm();
1165 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1168 static bool detected = false;
1170 * DBM is a non-conflicting feature. i.e, the kernel can safely
1171 * run a mix of CPUs with and without the feature. So, we
1172 * unconditionally enable the capability to allow any late CPU
1173 * to use the feature. We only enable the control bits on the
1174 * CPU, if it actually supports.
1176 * We have to make sure we print the "feature" detection only
1177 * when at least one CPU actually uses it. So check if this CPU
1178 * can actually use it and print the message exactly once.
1180 * This is safe as all CPUs (including secondary CPUs - due to the
1181 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1182 * goes through the "matches" check exactly once. Also if a CPU
1183 * matches the criteria, it is guaranteed that the CPU will turn
1184 * the DBM on, as the capability is unconditionally enabled.
1186 if (!detected && cpu_can_use_dbm(cap)) {
1188 pr_info("detected: Hardware dirty bit management\n");
1196 #ifdef CONFIG_ARM64_VHE
1197 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1199 return is_kernel_in_hyp_mode();
1202 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1205 * Copy register values that aren't redirected by hardware.
1207 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1208 * this value to tpidr_el2 before we patch the code. Once we've done
1209 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1212 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1213 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1217 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1219 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1221 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1222 WARN_ON(val & (7 << 27 | 7 << 21));
1225 #ifdef CONFIG_ARM64_SSBD
1226 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1228 if (user_mode(regs))
1231 if (instr & BIT(PSTATE_Imm_shift))
1232 regs->pstate |= PSR_SSBS_BIT;
1234 regs->pstate &= ~PSR_SSBS_BIT;
1236 arm64_skip_faulting_instruction(regs, 4);
1240 static struct undef_hook ssbs_emulation_hook = {
1241 .instr_mask = ~(1U << PSTATE_Imm_shift),
1242 .instr_val = 0xd500401f | PSTATE_SSBS,
1243 .fn = ssbs_emulation_handler,
1246 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1248 static bool undef_hook_registered = false;
1249 static DEFINE_RAW_SPINLOCK(hook_lock);
1251 raw_spin_lock(&hook_lock);
1252 if (!undef_hook_registered) {
1253 register_undef_hook(&ssbs_emulation_hook);
1254 undef_hook_registered = true;
1256 raw_spin_unlock(&hook_lock);
1258 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1259 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1260 arm64_set_ssbd_mitigation(false);
1262 arm64_set_ssbd_mitigation(true);
1265 #endif /* CONFIG_ARM64_SSBD */
1267 #ifdef CONFIG_ARM64_PAN
1268 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1271 * We modify PSTATE. This won't work from irq context as the PSTATE
1272 * is discarded once we return from the exception.
1274 WARN_ON_ONCE(in_interrupt());
1276 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1277 asm(SET_PSTATE_PAN(1));
1279 #endif /* CONFIG_ARM64_PAN */
1281 #ifdef CONFIG_ARM64_RAS_EXTN
1282 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1284 /* Firmware may have left a deferred SError in this register. */
1285 write_sysreg_s(0, SYS_DISR_EL1);
1287 #endif /* CONFIG_ARM64_RAS_EXTN */
1289 #ifdef CONFIG_ARM64_PTR_AUTH
1290 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1292 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1293 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1295 #endif /* CONFIG_ARM64_PTR_AUTH */
1297 #ifdef CONFIG_ARM64_E0PD
1298 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1300 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1301 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1303 #endif /* CONFIG_ARM64_E0PD */
1305 #ifdef CONFIG_ARM64_PSEUDO_NMI
1306 static bool enable_pseudo_nmi;
1308 static int __init early_enable_pseudo_nmi(char *p)
1310 return strtobool(p, &enable_pseudo_nmi);
1312 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1314 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1317 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1321 static const struct arm64_cpu_capabilities arm64_features[] = {
1323 .desc = "GIC system register CPU interface",
1324 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1325 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1326 .matches = has_useable_gicv3_cpuif,
1327 .sys_reg = SYS_ID_AA64PFR0_EL1,
1328 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1329 .sign = FTR_UNSIGNED,
1330 .min_field_value = 1,
1332 #ifdef CONFIG_ARM64_PAN
1334 .desc = "Privileged Access Never",
1335 .capability = ARM64_HAS_PAN,
1336 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1337 .matches = has_cpuid_feature,
1338 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1339 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1340 .sign = FTR_UNSIGNED,
1341 .min_field_value = 1,
1342 .cpu_enable = cpu_enable_pan,
1344 #endif /* CONFIG_ARM64_PAN */
1345 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1347 .desc = "LSE atomic instructions",
1348 .capability = ARM64_HAS_LSE_ATOMICS,
1349 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1350 .matches = has_cpuid_feature,
1351 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1352 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1353 .sign = FTR_UNSIGNED,
1354 .min_field_value = 2,
1356 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1358 .desc = "Software prefetching using PRFM",
1359 .capability = ARM64_HAS_NO_HW_PREFETCH,
1360 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1361 .matches = has_no_hw_prefetch,
1363 #ifdef CONFIG_ARM64_UAO
1365 .desc = "User Access Override",
1366 .capability = ARM64_HAS_UAO,
1367 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1368 .matches = has_cpuid_feature,
1369 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1370 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1371 .min_field_value = 1,
1373 * We rely on stop_machine() calling uao_thread_switch() to set
1374 * UAO immediately after patching.
1377 #endif /* CONFIG_ARM64_UAO */
1378 #ifdef CONFIG_ARM64_PAN
1380 .capability = ARM64_ALT_PAN_NOT_UAO,
1381 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1382 .matches = cpufeature_pan_not_uao,
1384 #endif /* CONFIG_ARM64_PAN */
1385 #ifdef CONFIG_ARM64_VHE
1387 .desc = "Virtualization Host Extensions",
1388 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1389 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1390 .matches = runs_at_el2,
1391 .cpu_enable = cpu_copy_el2regs,
1393 #endif /* CONFIG_ARM64_VHE */
1395 .desc = "32-bit EL0 Support",
1396 .capability = ARM64_HAS_32BIT_EL0,
1397 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1398 .matches = has_cpuid_feature,
1399 .sys_reg = SYS_ID_AA64PFR0_EL1,
1400 .sign = FTR_UNSIGNED,
1401 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1402 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1405 .desc = "Kernel page table isolation (KPTI)",
1406 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1407 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1409 * The ID feature fields below are used to indicate that
1410 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1413 .sys_reg = SYS_ID_AA64PFR0_EL1,
1414 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1415 .min_field_value = 1,
1416 .matches = unmap_kernel_at_el0,
1417 .cpu_enable = kpti_install_ng_mappings,
1420 /* FP/SIMD is not implemented */
1421 .capability = ARM64_HAS_NO_FPSIMD,
1422 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1423 .min_field_value = 0,
1424 .matches = has_no_fpsimd,
1426 #ifdef CONFIG_ARM64_PMEM
1428 .desc = "Data cache clean to Point of Persistence",
1429 .capability = ARM64_HAS_DCPOP,
1430 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1431 .matches = has_cpuid_feature,
1432 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1433 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1434 .min_field_value = 1,
1437 .desc = "Data cache clean to Point of Deep Persistence",
1438 .capability = ARM64_HAS_DCPODP,
1439 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1440 .matches = has_cpuid_feature,
1441 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1442 .sign = FTR_UNSIGNED,
1443 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1444 .min_field_value = 2,
1447 #ifdef CONFIG_ARM64_SVE
1449 .desc = "Scalable Vector Extension",
1450 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1451 .capability = ARM64_SVE,
1452 .sys_reg = SYS_ID_AA64PFR0_EL1,
1453 .sign = FTR_UNSIGNED,
1454 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1455 .min_field_value = ID_AA64PFR0_SVE,
1456 .matches = has_cpuid_feature,
1457 .cpu_enable = sve_kernel_enable,
1459 #endif /* CONFIG_ARM64_SVE */
1460 #ifdef CONFIG_ARM64_RAS_EXTN
1462 .desc = "RAS Extension Support",
1463 .capability = ARM64_HAS_RAS_EXTN,
1464 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1465 .matches = has_cpuid_feature,
1466 .sys_reg = SYS_ID_AA64PFR0_EL1,
1467 .sign = FTR_UNSIGNED,
1468 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1469 .min_field_value = ID_AA64PFR0_RAS_V1,
1470 .cpu_enable = cpu_clear_disr,
1472 #endif /* CONFIG_ARM64_RAS_EXTN */
1474 .desc = "Data cache clean to the PoU not required for I/D coherence",
1475 .capability = ARM64_HAS_CACHE_IDC,
1476 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1477 .matches = has_cache_idc,
1478 .cpu_enable = cpu_emulate_effective_ctr,
1481 .desc = "Instruction cache invalidation not required for I/D coherence",
1482 .capability = ARM64_HAS_CACHE_DIC,
1483 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1484 .matches = has_cache_dic,
1487 .desc = "Stage-2 Force Write-Back",
1488 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1489 .capability = ARM64_HAS_STAGE2_FWB,
1490 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1491 .sign = FTR_UNSIGNED,
1492 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1493 .min_field_value = 1,
1494 .matches = has_cpuid_feature,
1495 .cpu_enable = cpu_has_fwb,
1497 #ifdef CONFIG_ARM64_HW_AFDBM
1500 * Since we turn this on always, we don't want the user to
1501 * think that the feature is available when it may not be.
1502 * So hide the description.
1504 * .desc = "Hardware pagetable Dirty Bit Management",
1507 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1508 .capability = ARM64_HW_DBM,
1509 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1510 .sign = FTR_UNSIGNED,
1511 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1512 .min_field_value = 2,
1513 .matches = has_hw_dbm,
1514 .cpu_enable = cpu_enable_hw_dbm,
1518 .desc = "CRC32 instructions",
1519 .capability = ARM64_HAS_CRC32,
1520 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1521 .matches = has_cpuid_feature,
1522 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1523 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1524 .min_field_value = 1,
1526 #ifdef CONFIG_ARM64_SSBD
1528 .desc = "Speculative Store Bypassing Safe (SSBS)",
1529 .capability = ARM64_SSBS,
1530 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1531 .matches = has_cpuid_feature,
1532 .sys_reg = SYS_ID_AA64PFR1_EL1,
1533 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1534 .sign = FTR_UNSIGNED,
1535 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1536 .cpu_enable = cpu_enable_ssbs,
1539 #ifdef CONFIG_ARM64_CNP
1541 .desc = "Common not Private translations",
1542 .capability = ARM64_HAS_CNP,
1543 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1544 .matches = has_useable_cnp,
1545 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1546 .sign = FTR_UNSIGNED,
1547 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1548 .min_field_value = 1,
1549 .cpu_enable = cpu_enable_cnp,
1553 .desc = "Speculation barrier (SB)",
1554 .capability = ARM64_HAS_SB,
1555 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1556 .matches = has_cpuid_feature,
1557 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1558 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1559 .sign = FTR_UNSIGNED,
1560 .min_field_value = 1,
1562 #ifdef CONFIG_ARM64_PTR_AUTH
1564 .desc = "Address authentication (architected algorithm)",
1565 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1566 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1567 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1568 .sign = FTR_UNSIGNED,
1569 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1570 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1571 .matches = has_cpuid_feature,
1572 .cpu_enable = cpu_enable_address_auth,
1575 .desc = "Address authentication (IMP DEF algorithm)",
1576 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1577 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1578 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1579 .sign = FTR_UNSIGNED,
1580 .field_pos = ID_AA64ISAR1_API_SHIFT,
1581 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1582 .matches = has_cpuid_feature,
1583 .cpu_enable = cpu_enable_address_auth,
1586 .desc = "Generic authentication (architected algorithm)",
1587 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1588 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1589 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1590 .sign = FTR_UNSIGNED,
1591 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1592 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1593 .matches = has_cpuid_feature,
1596 .desc = "Generic authentication (IMP DEF algorithm)",
1597 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1598 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1599 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1600 .sign = FTR_UNSIGNED,
1601 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1602 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1603 .matches = has_cpuid_feature,
1605 #endif /* CONFIG_ARM64_PTR_AUTH */
1606 #ifdef CONFIG_ARM64_PSEUDO_NMI
1609 * Depends on having GICv3
1611 .desc = "IRQ priority masking",
1612 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1613 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1614 .matches = can_use_gic_priorities,
1615 .sys_reg = SYS_ID_AA64PFR0_EL1,
1616 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1617 .sign = FTR_UNSIGNED,
1618 .min_field_value = 1,
1621 #ifdef CONFIG_ARM64_E0PD
1624 .capability = ARM64_HAS_E0PD,
1625 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1626 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1627 .sign = FTR_UNSIGNED,
1628 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
1629 .matches = has_cpuid_feature,
1630 .min_field_value = 1,
1631 .cpu_enable = cpu_enable_e0pd,
1637 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1638 .matches = has_cpuid_feature, \
1640 .field_pos = field, \
1642 .min_field_value = min_value,
1644 #define __HWCAP_CAP(name, cap_type, cap) \
1646 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1647 .hwcap_type = cap_type, \
1650 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1652 __HWCAP_CAP(#cap, cap_type, cap) \
1653 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1656 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
1658 __HWCAP_CAP(#cap, cap_type, cap) \
1659 .matches = cpucap_multi_entry_cap_matches, \
1660 .match_list = list, \
1663 #ifdef CONFIG_ARM64_PTR_AUTH
1664 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1666 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1667 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1670 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1671 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1676 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1678 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1679 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1682 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1683 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1689 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1690 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1691 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1692 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1693 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1694 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1695 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1696 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1697 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1698 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1699 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1700 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1701 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1702 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1703 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1704 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1705 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1706 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1707 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1708 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1709 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1710 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1711 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1712 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1713 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1714 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1715 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1716 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1717 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1718 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1719 #ifdef CONFIG_ARM64_SVE
1720 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1721 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1722 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1723 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1724 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1725 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1726 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1728 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1729 #ifdef CONFIG_ARM64_PTR_AUTH
1730 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1731 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1736 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1737 #ifdef CONFIG_COMPAT
1738 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1739 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1740 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1741 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1742 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1747 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1749 switch (cap->hwcap_type) {
1751 cpu_set_feature(cap->hwcap);
1753 #ifdef CONFIG_COMPAT
1754 case CAP_COMPAT_HWCAP:
1755 compat_elf_hwcap |= (u32)cap->hwcap;
1757 case CAP_COMPAT_HWCAP2:
1758 compat_elf_hwcap2 |= (u32)cap->hwcap;
1767 /* Check if we have a particular HWCAP enabled */
1768 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1772 switch (cap->hwcap_type) {
1774 rc = cpu_have_feature(cap->hwcap);
1776 #ifdef CONFIG_COMPAT
1777 case CAP_COMPAT_HWCAP:
1778 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1780 case CAP_COMPAT_HWCAP2:
1781 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1792 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1794 /* We support emulation of accesses to CPU ID feature registers */
1795 cpu_set_named_feature(CPUID);
1796 for (; hwcaps->matches; hwcaps++)
1797 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1798 cap_set_elf_hwcap(hwcaps);
1801 static void update_cpu_capabilities(u16 scope_mask)
1804 const struct arm64_cpu_capabilities *caps;
1806 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1807 for (i = 0; i < ARM64_NCAPS; i++) {
1808 caps = cpu_hwcaps_ptrs[i];
1809 if (!caps || !(caps->type & scope_mask) ||
1810 cpus_have_cap(caps->capability) ||
1811 !caps->matches(caps, cpucap_default_scope(caps)))
1815 pr_info("detected: %s\n", caps->desc);
1816 cpus_set_cap(caps->capability);
1818 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1819 set_bit(caps->capability, boot_capabilities);
1824 * Enable all the available capabilities on this CPU. The capabilities
1825 * with BOOT_CPU scope are handled separately and hence skipped here.
1827 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1830 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1832 for_each_available_cap(i) {
1833 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1838 if (!(cap->type & non_boot_scope))
1841 if (cap->cpu_enable)
1842 cap->cpu_enable(cap);
1848 * Run through the enabled capabilities and enable() it on all active
1851 static void __init enable_cpu_capabilities(u16 scope_mask)
1854 const struct arm64_cpu_capabilities *caps;
1857 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1858 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1860 for (i = 0; i < ARM64_NCAPS; i++) {
1863 caps = cpu_hwcaps_ptrs[i];
1864 if (!caps || !(caps->type & scope_mask))
1866 num = caps->capability;
1867 if (!cpus_have_cap(num))
1870 /* Ensure cpus_have_const_cap(num) works */
1871 static_branch_enable(&cpu_hwcap_keys[num]);
1873 if (boot_scope && caps->cpu_enable)
1875 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1876 * before any secondary CPU boots. Thus, each secondary
1877 * will enable the capability as appropriate via
1878 * check_local_cpu_capabilities(). The only exception is
1879 * the boot CPU, for which the capability must be
1880 * enabled here. This approach avoids costly
1881 * stop_machine() calls for this case.
1883 caps->cpu_enable(caps);
1887 * For all non-boot scope capabilities, use stop_machine()
1888 * as it schedules the work allowing us to modify PSTATE,
1889 * instead of on_each_cpu() which uses an IPI, giving us a
1890 * PSTATE that disappears when we return.
1893 stop_machine(cpu_enable_non_boot_scope_capabilities,
1894 NULL, cpu_online_mask);
1898 * Run through the list of capabilities to check for conflicts.
1899 * If the system has already detected a capability, take necessary
1900 * action on this CPU.
1902 * Returns "false" on conflicts.
1904 static bool verify_local_cpu_caps(u16 scope_mask)
1907 bool cpu_has_cap, system_has_cap;
1908 const struct arm64_cpu_capabilities *caps;
1910 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1912 for (i = 0; i < ARM64_NCAPS; i++) {
1913 caps = cpu_hwcaps_ptrs[i];
1914 if (!caps || !(caps->type & scope_mask))
1917 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1918 system_has_cap = cpus_have_cap(caps->capability);
1920 if (system_has_cap) {
1922 * Check if the new CPU misses an advertised feature,
1923 * which is not safe to miss.
1925 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1928 * We have to issue cpu_enable() irrespective of
1929 * whether the CPU has it or not, as it is enabeld
1930 * system wide. It is upto the call back to take
1931 * appropriate action on this CPU.
1933 if (caps->cpu_enable)
1934 caps->cpu_enable(caps);
1937 * Check if the CPU has this capability if it isn't
1938 * safe to have when the system doesn't.
1940 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1945 if (i < ARM64_NCAPS) {
1946 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1947 smp_processor_id(), caps->capability,
1948 caps->desc, system_has_cap, cpu_has_cap);
1956 * Check for CPU features that are used in early boot
1957 * based on the Boot CPU value.
1959 static void check_early_cpu_features(void)
1961 verify_cpu_asid_bits();
1963 * Early features are used by the kernel already. If there
1964 * is a conflict, we cannot proceed further.
1966 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1971 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1974 for (; caps->matches; caps++)
1975 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1976 pr_crit("CPU%d: missing HWCAP: %s\n",
1977 smp_processor_id(), caps->desc);
1982 static void verify_sve_features(void)
1984 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1985 u64 zcr = read_zcr_features();
1987 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1988 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1990 if (len < safe_len || sve_verify_vq_map()) {
1991 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1992 smp_processor_id());
1996 /* Add checks on other ZCR bits here if necessary */
2001 * Run through the enabled system capabilities and enable() it on this CPU.
2002 * The capabilities were decided based on the available CPUs at the boot time.
2003 * Any new CPU should match the system wide status of the capability. If the
2004 * new CPU doesn't have a capability which the system now has enabled, we
2005 * cannot do anything to fix it up and could cause unexpected failures. So
2008 static void verify_local_cpu_capabilities(void)
2011 * The capabilities with SCOPE_BOOT_CPU are checked from
2012 * check_early_cpu_features(), as they need to be verified
2013 * on all secondary CPUs.
2015 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
2018 verify_local_elf_hwcaps(arm64_elf_hwcaps);
2020 if (system_supports_32bit_el0())
2021 verify_local_elf_hwcaps(compat_elf_hwcaps);
2023 if (system_supports_sve())
2024 verify_sve_features();
2027 void check_local_cpu_capabilities(void)
2030 * All secondary CPUs should conform to the early CPU features
2031 * in use by the kernel based on boot CPU.
2033 check_early_cpu_features();
2036 * If we haven't finalised the system capabilities, this CPU gets
2037 * a chance to update the errata work arounds and local features.
2038 * Otherwise, this CPU should verify that it has all the system
2039 * advertised capabilities.
2041 if (!sys_caps_initialised)
2042 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2044 verify_local_cpu_capabilities();
2047 static void __init setup_boot_cpu_capabilities(void)
2049 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2050 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2051 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2052 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2055 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2056 EXPORT_SYMBOL(arm64_const_caps_ready);
2058 static void __init mark_const_caps_ready(void)
2060 static_branch_enable(&arm64_const_caps_ready);
2063 bool this_cpu_has_cap(unsigned int n)
2065 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2066 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2069 return cap->matches(cap, SCOPE_LOCAL_CPU);
2075 void cpu_set_feature(unsigned int num)
2077 WARN_ON(num >= MAX_CPU_FEATURES);
2078 elf_hwcap |= BIT(num);
2080 EXPORT_SYMBOL_GPL(cpu_set_feature);
2082 bool cpu_have_feature(unsigned int num)
2084 WARN_ON(num >= MAX_CPU_FEATURES);
2085 return elf_hwcap & BIT(num);
2087 EXPORT_SYMBOL_GPL(cpu_have_feature);
2089 unsigned long cpu_get_elf_hwcap(void)
2092 * We currently only populate the first 32 bits of AT_HWCAP. Please
2093 * note that for userspace compatibility we guarantee that bits 62
2094 * and 63 will always be returned as 0.
2096 return lower_32_bits(elf_hwcap);
2099 unsigned long cpu_get_elf_hwcap2(void)
2101 return upper_32_bits(elf_hwcap);
2104 static void __init setup_system_capabilities(void)
2107 * We have finalised the system-wide safe feature
2108 * registers, finalise the capabilities that depend
2109 * on it. Also enable all the available capabilities,
2110 * that are not enabled already.
2112 update_cpu_capabilities(SCOPE_SYSTEM);
2113 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2116 void __init setup_cpu_features(void)
2120 setup_system_capabilities();
2121 mark_const_caps_ready();
2122 setup_elf_hwcaps(arm64_elf_hwcaps);
2124 if (system_supports_32bit_el0())
2125 setup_elf_hwcaps(compat_elf_hwcaps);
2127 if (system_uses_ttbr0_pan())
2128 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2131 minsigstksz_setup();
2133 /* Advertise that we have computed the system capabilities */
2134 set_sys_caps_initialised();
2137 * Check for sane CTR_EL0.CWG value.
2139 cwg = cache_type_cwg();
2141 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2145 static bool __maybe_unused
2146 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2148 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2151 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2153 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2157 * We emulate only the following system register space.
2158 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2159 * See Table C5-6 System instruction encodings for System register accesses,
2160 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2162 static inline bool __attribute_const__ is_emulated(u32 id)
2164 return (sys_reg_Op0(id) == 0x3 &&
2165 sys_reg_CRn(id) == 0x0 &&
2166 sys_reg_Op1(id) == 0x0 &&
2167 (sys_reg_CRm(id) == 0 ||
2168 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2172 * With CRm == 0, reg should be one of :
2173 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2175 static inline int emulate_id_reg(u32 id, u64 *valp)
2179 *valp = read_cpuid_id();
2182 *valp = SYS_MPIDR_SAFE_VAL;
2184 case SYS_REVIDR_EL1:
2185 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2195 static int emulate_sys_reg(u32 id, u64 *valp)
2197 struct arm64_ftr_reg *regp;
2199 if (!is_emulated(id))
2202 if (sys_reg_CRm(id) == 0)
2203 return emulate_id_reg(id, valp);
2205 regp = get_arm64_ftr_reg(id);
2207 *valp = arm64_ftr_reg_user_value(regp);
2210 * The untracked registers are either IMPLEMENTATION DEFINED
2211 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2217 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2222 rc = emulate_sys_reg(sys_reg, &val);
2224 pt_regs_write_reg(regs, rt, val);
2225 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2230 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2235 * sys_reg values are defined as used in mrs/msr instruction.
2236 * shift the imm value to get the encoding.
2238 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2239 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2240 return do_emulate_mrs(regs, sys_reg, rt);
2243 static struct undef_hook mrs_hook = {
2244 .instr_mask = 0xfff00000,
2245 .instr_val = 0xd5300000,
2246 .pstate_mask = PSR_AA32_MODE_MASK,
2247 .pstate_val = PSR_MODE_EL0t,
2251 static int __init enable_mrs_emulation(void)
2253 register_undef_hook(&mrs_hook);
2257 core_initcall(enable_mrs_emulation);
2259 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2262 if (__meltdown_safe)
2263 return sprintf(buf, "Not affected\n");
2265 if (arm64_kernel_unmapped_at_el0())
2266 return sprintf(buf, "Mitigation: PTI\n");
2268 return sprintf(buf, "Vulnerable\n");