1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
82 #include <asm/hwcap.h>
84 #include <asm/kvm_host.h>
85 #include <asm/mmu_context.h>
87 #include <asm/processor.h>
89 #include <asm/sysreg.h>
90 #include <asm/traps.h>
91 #include <asm/vectors.h>
94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
95 static unsigned long elf_hwcap __read_mostly;
98 #define COMPAT_ELF_HWCAP_DEFAULT \
99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
104 unsigned int compat_elf_hwcap2 __read_mostly;
107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
108 EXPORT_SYMBOL(cpu_hwcaps);
109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
111 /* Need also bit for ARM64_CB_PATCH */
112 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
114 bool arm64_use_ng_mappings = false;
115 EXPORT_SYMBOL(arm64_use_ng_mappings);
117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
123 static bool __read_mostly allow_mismatched_32bit_el0;
126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
127 * seen at least one CPU capable of 32-bit EL0.
129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
132 * Mask of CPUs supporting 32-bit EL0.
133 * Only valid if arm64_mismatched_32bit_el0 is enabled.
135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
138 * Flag to indicate if we have computed the system wide
139 * capabilities based on the boot time active CPUs. This
140 * will be used to determine if a new booting CPU should
141 * go through the verification process to make sure that it
142 * supports the system capabilities, without using a hotplug
143 * notifier. This is also used to decide if we could use
144 * the fast path for checking constant CPU caps.
146 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
147 EXPORT_SYMBOL(arm64_const_caps_ready);
148 static inline void finalize_system_capabilities(void)
150 static_branch_enable(&arm64_const_caps_ready);
153 void dump_cpu_features(void)
155 /* file-wide pr_fmt adds "CPU features: " prefix */
156 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
159 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
160 EXPORT_SYMBOL(cpu_hwcap_keys);
162 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
165 .visible = VISIBLE, \
170 .safe_val = SAFE_VAL, \
173 /* Define a feature with unsigned values */
174 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
175 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
177 /* Define a feature with a signed value */
178 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
179 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
181 #define ARM64_FTR_END \
186 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
188 static bool __system_matches_cap(unsigned int n);
191 * NOTE: Any changes to the visibility of features should be kept in
192 * sync with the documentation of the CPU feature register ABI.
194 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
212 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
220 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
222 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
227 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
234 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
237 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0),
245 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
256 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
257 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
265 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
278 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
292 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
294 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
296 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
300 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0),
303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0),
305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0),
307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0),
309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0),
311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0),
313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0),
318 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
323 * Page size not being supported at Stage-2 is not fatal. You
324 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
325 * your favourite nesting hypervisor.
327 * There is a small corner case where the hypervisor explicitly
328 * advertises a given granule size at Stage-2 (value 2) on some
329 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
330 * vCPUs. Although this is not forbidden by the architecture, it
331 * indicates that the hypervisor is being silly (or buggy).
333 * We make no effort to cope with this and pretend that if these
334 * fields are inconsistent across vCPUs, then it isn't worth
335 * trying to bring KVM up.
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
341 * We already refuse to boot CPUs that don't support our configured
342 * page size, so we can only detect mismatches for a page size other
343 * than the one we're currently using. Unfortunately, SoCs like this
344 * exist in the wild so, even though we don't like it, we'll have to go
345 * along with it and treat them as non-strict.
347 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
348 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
352 /* Linux shouldn't care about secure memory */
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
357 * Differing PARange is fine as long as all peripherals and memory are mapped
358 * within the minimum PARange of all CPUs
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
364 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
379 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
398 static const struct arm64_ftr_bits ftr_ctr[] = {
399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
406 * Linux can handle differing I-cache policies. Userspace JITs will
407 * make use of *minLine.
408 * If we have differing I-cache policies, report it as the weakest - VIPT.
410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
415 static struct arm64_ftr_override __ro_after_init no_override = { };
417 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
418 .name = "SYS_CTR_EL0",
420 .override = &no_override,
423 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
424 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
429 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
435 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
442 * We can instantiate multiple PMU instances with different levels
445 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
450 static const struct arm64_ftr_bits ftr_mvfr2[] = {
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
456 static const struct arm64_ftr_bits ftr_dczid[] = {
457 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
458 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
462 static const struct arm64_ftr_bits ftr_gmid[] = {
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
467 static const struct arm64_ftr_bits ftr_id_isar0[] = {
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
478 static const struct arm64_ftr_bits ftr_id_isar5[] = {
479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
488 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
498 * SpecSEI = 1 indicates that the PE might generate an SError on an
499 * external abort on speculative read. It is safe to assume that an
500 * SError might be generated than it will not be. Hence it has been
501 * classified as FTR_HIGHER_SAFE.
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
507 static const struct arm64_ftr_bits ftr_id_isar4[] = {
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
519 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
524 static const struct arm64_ftr_bits ftr_id_isar6[] = {
525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
535 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
545 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
557 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
563 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
564 /* [31:28] TraceFilt */
565 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
575 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
576 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
580 static const struct arm64_ftr_bits ftr_zcr[] = {
581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
582 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */
586 static const struct arm64_ftr_bits ftr_smcr[] = {
587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
588 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */
593 * Common ftr bits for a 32bit register with all hidden, strict
594 * attributes, with 4bit feature fields and a default safe value of
595 * 0. Covers the following 32bit registers:
596 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
598 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
610 /* Table for a single 32bit feature value */
611 static const struct arm64_ftr_bits ftr_single32[] = {
612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
616 static const struct arm64_ftr_bits ftr_raz[] = {
620 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
622 .reg = &(struct arm64_ftr_reg){ \
625 .ftr_bits = &((table)[0]), \
628 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
629 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
631 #define ARM64_FTR_REG(id, table) \
632 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
634 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
635 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
636 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
637 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
639 static const struct __ftr_reg_entry {
641 struct arm64_ftr_reg *reg;
642 } arm64_ftr_regs[] = {
644 /* Op1 = 0, CRn = 0, CRm = 1 */
645 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
646 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
647 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
648 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
649 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
650 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
651 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
653 /* Op1 = 0, CRn = 0, CRm = 2 */
654 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
655 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
656 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
657 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
658 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
659 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
660 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
661 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
663 /* Op1 = 0, CRn = 0, CRm = 3 */
664 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
665 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
666 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
667 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
668 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
669 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
671 /* Op1 = 0, CRn = 0, CRm = 4 */
672 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
673 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
674 &id_aa64pfr1_override),
675 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
676 ARM64_FTR_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0),
678 /* Op1 = 0, CRn = 0, CRm = 5 */
679 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
680 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
682 /* Op1 = 0, CRn = 0, CRm = 6 */
683 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
684 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
685 &id_aa64isar1_override),
686 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
687 &id_aa64isar2_override),
689 /* Op1 = 0, CRn = 0, CRm = 7 */
690 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
691 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
692 &id_aa64mmfr1_override),
693 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
695 /* Op1 = 0, CRn = 1, CRm = 2 */
696 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
697 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
699 /* Op1 = 1, CRn = 0, CRm = 0 */
700 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
702 /* Op1 = 3, CRn = 0, CRm = 0 */
703 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
704 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
706 /* Op1 = 3, CRn = 14, CRm = 0 */
707 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
710 static int search_cmp_ftr_reg(const void *id, const void *regp)
712 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
716 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
717 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
718 * ascending order of sys_id, we use binary search to find a matching
721 * returns - Upon success, matching ftr_reg entry for id.
722 * - NULL on failure. It is upto the caller to decide
723 * the impact of a failure.
725 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
727 const struct __ftr_reg_entry *ret;
729 ret = bsearch((const void *)(unsigned long)sys_id,
731 ARRAY_SIZE(arm64_ftr_regs),
732 sizeof(arm64_ftr_regs[0]),
740 * get_arm64_ftr_reg - Looks up a feature register entry using
741 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
743 * returns - Upon success, matching ftr_reg entry for id.
744 * - NULL on failure but with an WARN_ON().
746 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
748 struct arm64_ftr_reg *reg;
750 reg = get_arm64_ftr_reg_nowarn(sys_id);
753 * Requesting a non-existent register search is an error. Warn
754 * and let the caller handle it.
760 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
763 u64 mask = arm64_ftr_mask(ftrp);
766 reg |= (ftr_val << ftrp->shift) & mask;
770 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
775 switch (ftrp->type) {
777 ret = ftrp->safe_val;
782 case FTR_HIGHER_OR_ZERO_SAFE:
786 case FTR_HIGHER_SAFE:
796 static void __init sort_ftr_regs(void)
800 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
801 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
802 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
806 * Features here must be sorted in descending order with respect
807 * to their shift values and should not overlap with each other.
809 for (; ftr_bits->width != 0; ftr_bits++, j++) {
810 unsigned int width = ftr_reg->ftr_bits[j].width;
811 unsigned int shift = ftr_reg->ftr_bits[j].shift;
812 unsigned int prev_shift;
814 WARN((shift + width) > 64,
815 "%s has invalid feature at shift %d\n",
816 ftr_reg->name, shift);
819 * Skip the first feature. There is nothing to
820 * compare against for now.
825 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
826 WARN((shift + width) > prev_shift,
827 "%s has feature overlap at shift %d\n",
828 ftr_reg->name, shift);
832 * Skip the first register. There is nothing to
833 * compare against for now.
838 * Registers here must be sorted in ascending order with respect
839 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
842 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
847 * Initialise the CPU feature register from Boot CPU values.
848 * Also initiliases the strict_mask for the register.
849 * Any bits that are not covered by an arm64_ftr_bits entry are considered
850 * RES0 for the system-wide value, and must strictly match.
852 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
855 u64 strict_mask = ~0x0ULL;
859 const struct arm64_ftr_bits *ftrp;
860 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
865 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
866 u64 ftr_mask = arm64_ftr_mask(ftrp);
867 s64 ftr_new = arm64_ftr_value(ftrp, new);
868 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
870 if ((ftr_mask & reg->override->mask) == ftr_mask) {
871 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
874 if (ftr_ovr != tmp) {
875 /* Unsafe, remove the override */
876 reg->override->mask &= ~ftr_mask;
877 reg->override->val &= ~ftr_mask;
879 str = "ignoring override";
880 } else if (ftr_new != tmp) {
881 /* Override was valid */
884 } else if (ftr_ovr == tmp) {
885 /* Override was the safe value */
890 pr_warn("%s[%d:%d]: %s to %llx\n",
892 ftrp->shift + ftrp->width - 1,
893 ftrp->shift, str, tmp);
894 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
895 reg->override->val &= ~ftr_mask;
896 pr_warn("%s[%d:%d]: impossible override, ignored\n",
898 ftrp->shift + ftrp->width - 1,
902 val = arm64_ftr_set_value(ftrp, val, ftr_new);
904 valid_mask |= ftr_mask;
906 strict_mask &= ~ftr_mask;
908 user_mask |= ftr_mask;
910 reg->user_val = arm64_ftr_set_value(ftrp,
918 reg->strict_mask = strict_mask;
919 reg->user_mask = user_mask;
922 extern const struct arm64_cpu_capabilities arm64_errata[];
923 static const struct arm64_cpu_capabilities arm64_features[];
926 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
928 for (; caps->matches; caps++) {
929 if (WARN(caps->capability >= ARM64_NCAPS,
930 "Invalid capability %d\n", caps->capability))
932 if (WARN(cpu_hwcaps_ptrs[caps->capability],
933 "Duplicate entry for capability %d\n",
936 cpu_hwcaps_ptrs[caps->capability] = caps;
940 static void __init init_cpu_hwcaps_indirect_list(void)
942 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
943 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
946 static void __init setup_boot_cpu_capabilities(void);
948 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
950 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
951 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
952 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
953 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
954 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
955 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
956 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
957 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
958 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
959 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
960 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
961 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
962 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
963 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
964 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
965 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
966 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
967 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
968 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
969 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
970 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
973 void __init init_cpu_features(struct cpuinfo_arm64 *info)
975 /* Before we start using the tables, make sure it is sorted */
978 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
979 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
980 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
981 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
982 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
983 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
984 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
985 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
986 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
987 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
988 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
989 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
990 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
991 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
992 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
994 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
995 init_32bit_cpu_features(&info->aarch32);
997 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
998 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
999 vec_init_vq_map(ARM64_VEC_SVE);
1002 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
1003 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1004 if (IS_ENABLED(CONFIG_ARM64_SME))
1005 vec_init_vq_map(ARM64_VEC_SME);
1008 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1009 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1012 * Initialize the indirect array of CPU hwcaps capabilities pointers
1013 * before we handle the boot CPU below.
1015 init_cpu_hwcaps_indirect_list();
1018 * Detect and enable early CPU capabilities based on the boot CPU,
1019 * after we have initialised the CPU feature infrastructure.
1021 setup_boot_cpu_capabilities();
1024 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1026 const struct arm64_ftr_bits *ftrp;
1028 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1029 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1030 s64 ftr_new = arm64_ftr_value(ftrp, new);
1032 if (ftr_cur == ftr_new)
1034 /* Find a safe value */
1035 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1036 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1041 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1043 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1048 update_cpu_ftr_reg(regp, val);
1049 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1051 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1052 regp->name, boot, cpu, val);
1056 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1058 const struct arm64_ftr_bits *ftrp;
1059 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1064 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1065 if (ftrp->shift == field) {
1066 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1072 WARN_ON(!ftrp->width);
1075 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1076 struct cpuinfo_arm64 *boot)
1078 static bool boot_cpu_32bit_regs_overridden = false;
1080 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1083 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1086 boot->aarch32 = info->aarch32;
1087 init_32bit_cpu_features(&boot->aarch32);
1088 boot_cpu_32bit_regs_overridden = true;
1091 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1092 struct cpuinfo_32bit *boot)
1095 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1098 * If we don't have AArch32 at EL1, then relax the strictness of
1099 * EL1-dependent register fields to avoid spurious sanity check fails.
1101 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1102 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1103 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1104 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1105 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1106 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1107 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1110 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1111 info->reg_id_dfr0, boot->reg_id_dfr0);
1112 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1113 info->reg_id_dfr1, boot->reg_id_dfr1);
1114 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1115 info->reg_id_isar0, boot->reg_id_isar0);
1116 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1117 info->reg_id_isar1, boot->reg_id_isar1);
1118 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1119 info->reg_id_isar2, boot->reg_id_isar2);
1120 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1121 info->reg_id_isar3, boot->reg_id_isar3);
1122 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1123 info->reg_id_isar4, boot->reg_id_isar4);
1124 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1125 info->reg_id_isar5, boot->reg_id_isar5);
1126 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1127 info->reg_id_isar6, boot->reg_id_isar6);
1130 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1131 * ACTLR formats could differ across CPUs and therefore would have to
1132 * be trapped for virtualization anyway.
1134 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1135 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1136 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1137 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1138 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1139 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1140 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1141 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1142 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1143 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1144 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1145 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1146 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1147 info->reg_id_pfr0, boot->reg_id_pfr0);
1148 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1149 info->reg_id_pfr1, boot->reg_id_pfr1);
1150 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1151 info->reg_id_pfr2, boot->reg_id_pfr2);
1152 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1153 info->reg_mvfr0, boot->reg_mvfr0);
1154 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1155 info->reg_mvfr1, boot->reg_mvfr1);
1156 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1157 info->reg_mvfr2, boot->reg_mvfr2);
1163 * Update system wide CPU feature registers with the values from a
1164 * non-boot CPU. Also performs SANITY checks to make sure that there
1165 * aren't any insane variations from that of the boot CPU.
1167 void update_cpu_features(int cpu,
1168 struct cpuinfo_arm64 *info,
1169 struct cpuinfo_arm64 *boot)
1174 * The kernel can handle differing I-cache policies, but otherwise
1175 * caches should look identical. Userspace JITs will make use of
1178 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1179 info->reg_ctr, boot->reg_ctr);
1182 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1183 * could result in too much or too little memory being zeroed if a
1184 * process is preempted and migrated between CPUs.
1186 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1187 info->reg_dczid, boot->reg_dczid);
1189 /* If different, timekeeping will be broken (especially with KVM) */
1190 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1191 info->reg_cntfrq, boot->reg_cntfrq);
1194 * The kernel uses self-hosted debug features and expects CPUs to
1195 * support identical debug features. We presently need CTX_CMPs, WRPs,
1196 * and BRPs to be identical.
1197 * ID_AA64DFR1 is currently RES0.
1199 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1200 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1201 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1202 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1204 * Even in big.LITTLE, processors should be identical instruction-set
1207 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1208 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1209 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1210 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1211 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1212 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1215 * Differing PARange support is fine as long as all peripherals and
1216 * memory are mapped within the minimum PARange of all CPUs.
1217 * Linux should not care about secure memory.
1219 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1220 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1221 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1222 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1223 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1224 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1226 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1227 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1228 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1229 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1231 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1232 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1234 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1235 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1237 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1238 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1239 info->reg_zcr, boot->reg_zcr);
1241 /* Probe vector lengths, unless we already gave up on SVE */
1242 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1243 !system_capabilities_finalized())
1244 vec_update_vq_map(ARM64_VEC_SVE);
1247 if (id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {
1248 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1249 info->reg_smcr, boot->reg_smcr);
1251 /* Probe vector lengths, unless we already gave up on SME */
1252 if (id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1)) &&
1253 !system_capabilities_finalized())
1254 vec_update_vq_map(ARM64_VEC_SME);
1258 * The kernel uses the LDGM/STGM instructions and the number of tags
1259 * they read/write depends on the GMID_EL1.BS field. Check that the
1260 * value is the same on all CPUs.
1262 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1263 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1264 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1265 info->reg_gmid, boot->reg_gmid);
1269 * If we don't have AArch32 at all then skip the checks entirely
1270 * as the register values may be UNKNOWN and we're not going to be
1271 * using them for anything.
1273 * This relies on a sanitised view of the AArch64 ID registers
1274 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1276 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1277 lazy_init_32bit_cpu_features(info, boot);
1278 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1283 * Mismatched CPU features are a recipe for disaster. Don't even
1284 * pretend to support them.
1287 pr_warn_once("Unsupported CPU feature variation detected.\n");
1288 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1292 u64 read_sanitised_ftr_reg(u32 id)
1294 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1298 return regp->sys_val;
1300 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1302 #define read_sysreg_case(r) \
1303 case r: val = read_sysreg_s(r); break;
1306 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1307 * Read the system register on the current CPU
1309 u64 __read_sysreg_by_encoding(u32 sys_id)
1311 struct arm64_ftr_reg *regp;
1315 read_sysreg_case(SYS_ID_PFR0_EL1);
1316 read_sysreg_case(SYS_ID_PFR1_EL1);
1317 read_sysreg_case(SYS_ID_PFR2_EL1);
1318 read_sysreg_case(SYS_ID_DFR0_EL1);
1319 read_sysreg_case(SYS_ID_DFR1_EL1);
1320 read_sysreg_case(SYS_ID_MMFR0_EL1);
1321 read_sysreg_case(SYS_ID_MMFR1_EL1);
1322 read_sysreg_case(SYS_ID_MMFR2_EL1);
1323 read_sysreg_case(SYS_ID_MMFR3_EL1);
1324 read_sysreg_case(SYS_ID_MMFR4_EL1);
1325 read_sysreg_case(SYS_ID_MMFR5_EL1);
1326 read_sysreg_case(SYS_ID_ISAR0_EL1);
1327 read_sysreg_case(SYS_ID_ISAR1_EL1);
1328 read_sysreg_case(SYS_ID_ISAR2_EL1);
1329 read_sysreg_case(SYS_ID_ISAR3_EL1);
1330 read_sysreg_case(SYS_ID_ISAR4_EL1);
1331 read_sysreg_case(SYS_ID_ISAR5_EL1);
1332 read_sysreg_case(SYS_ID_ISAR6_EL1);
1333 read_sysreg_case(SYS_MVFR0_EL1);
1334 read_sysreg_case(SYS_MVFR1_EL1);
1335 read_sysreg_case(SYS_MVFR2_EL1);
1337 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1338 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1339 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1340 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1341 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1342 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1343 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1344 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1345 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1346 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1347 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1348 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1350 read_sysreg_case(SYS_CNTFRQ_EL0);
1351 read_sysreg_case(SYS_CTR_EL0);
1352 read_sysreg_case(SYS_DCZID_EL0);
1359 regp = get_arm64_ftr_reg(sys_id);
1361 val &= ~regp->override->mask;
1362 val |= (regp->override->val & regp->override->mask);
1368 #include <linux/irqchip/arm-gic-v3.h>
1371 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1373 int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1377 return val >= entry->min_field_value;
1381 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1385 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1386 if (scope == SCOPE_SYSTEM)
1387 val = read_sanitised_ftr_reg(entry->sys_reg);
1389 val = __read_sysreg_by_encoding(entry->sys_reg);
1391 return feature_matches(val, entry);
1394 const struct cpumask *system_32bit_el0_cpumask(void)
1396 if (!system_supports_32bit_el0())
1397 return cpu_none_mask;
1399 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1400 return cpu_32bit_el0_mask;
1402 return cpu_possible_mask;
1405 static int __init parse_32bit_el0_param(char *str)
1407 allow_mismatched_32bit_el0 = true;
1410 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1412 static ssize_t aarch32_el0_show(struct device *dev,
1413 struct device_attribute *attr, char *buf)
1415 const struct cpumask *mask = system_32bit_el0_cpumask();
1417 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1419 static const DEVICE_ATTR_RO(aarch32_el0);
1421 static int __init aarch32_el0_sysfs_init(void)
1423 if (!allow_mismatched_32bit_el0)
1426 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1428 device_initcall(aarch32_el0_sysfs_init);
1430 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1432 if (!has_cpuid_feature(entry, scope))
1433 return allow_mismatched_32bit_el0;
1435 if (scope == SCOPE_SYSTEM)
1436 pr_info("detected: 32-bit EL0 Support\n");
1441 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1445 if (!has_cpuid_feature(entry, scope))
1448 has_sre = gic_enable_sre();
1450 pr_warn_once("%s present but disabled by higher exception level\n",
1456 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1458 u32 midr = read_cpuid_id();
1460 /* Cavium ThunderX pass 1.x and 2.x */
1461 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1462 MIDR_CPU_VAR_REV(0, 0),
1463 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1466 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1468 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1470 return cpuid_feature_extract_signed_field(pfr0,
1471 ID_AA64PFR0_FP_SHIFT) < 0;
1474 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1479 if (scope == SCOPE_SYSTEM)
1480 ctr = arm64_ftr_reg_ctrel0.sys_val;
1482 ctr = read_cpuid_effective_cachetype();
1484 return ctr & BIT(CTR_IDC_SHIFT);
1487 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1490 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1491 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1492 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1495 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1496 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1499 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1504 if (scope == SCOPE_SYSTEM)
1505 ctr = arm64_ftr_reg_ctrel0.sys_val;
1507 ctr = read_cpuid_cachetype();
1509 return ctr & BIT(CTR_DIC_SHIFT);
1512 static bool __maybe_unused
1513 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1516 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1517 * may share TLB entries with a CPU stuck in the crashed
1520 if (is_kdump_kernel())
1523 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1526 return has_cpuid_feature(entry, scope);
1530 * This check is triggered during the early boot before the cpufeature
1531 * is initialised. Checking the status on the local CPU allows the boot
1532 * CPU to detect the need for non-global mappings and thus avoiding a
1533 * pagetable re-write after all the CPUs are booted. This check will be
1534 * anyway run on individual CPUs, allowing us to get the consistent
1535 * state once the SMP CPUs are up and thus make the switch to non-global
1536 * mappings if required.
1538 bool kaslr_requires_kpti(void)
1540 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1544 * E0PD does a similar job to KPTI so can be used instead
1547 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1548 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1549 if (cpuid_feature_extract_unsigned_field(mmfr2,
1550 ID_AA64MMFR2_E0PD_SHIFT))
1555 * Systems affected by Cavium erratum 24756 are incompatible
1558 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1559 extern const struct midr_range cavium_erratum_27456_cpus[];
1561 if (is_midr_in_range_list(read_cpuid_id(),
1562 cavium_erratum_27456_cpus))
1566 return kaslr_offset() > 0;
1569 static bool __meltdown_safe = true;
1570 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1572 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1575 /* List of CPUs that are not vulnerable and don't need KPTI */
1576 static const struct midr_range kpti_safe_list[] = {
1577 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1578 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1579 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1580 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1581 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1582 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1583 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1584 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1585 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1586 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1587 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1588 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1589 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1590 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1591 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1594 char const *str = "kpti command line option";
1597 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1599 /* Defer to CPU feature registers */
1600 if (has_cpuid_feature(entry, scope))
1601 meltdown_safe = true;
1604 __meltdown_safe = false;
1607 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1608 * ThunderX leads to apparent I-cache corruption of kernel text, which
1609 * ends as well as you might imagine. Don't even try. We cannot rely
1610 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1611 * because cpucap detection order may change. However, since we know
1612 * affected CPUs are always in a homogeneous configuration, it is
1613 * safe to rely on this_cpu_has_cap() here.
1615 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1616 str = "ARM64_WORKAROUND_CAVIUM_27456";
1620 /* Useful for KASLR robustness */
1621 if (kaslr_requires_kpti()) {
1622 if (!__kpti_forced) {
1628 if (cpu_mitigations_off() && !__kpti_forced) {
1629 str = "mitigations=off";
1633 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1634 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1639 if (__kpti_forced) {
1640 pr_info_once("kernel page table isolation forced %s by %s\n",
1641 __kpti_forced > 0 ? "ON" : "OFF", str);
1642 return __kpti_forced > 0;
1645 return !meltdown_safe;
1648 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1649 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1652 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1653 phys_addr_t size, pgprot_t prot,
1654 phys_addr_t (*pgtable_alloc)(int), int flags);
1656 static phys_addr_t kpti_ng_temp_alloc;
1658 static phys_addr_t kpti_ng_pgd_alloc(int shift)
1660 kpti_ng_temp_alloc -= PAGE_SIZE;
1661 return kpti_ng_temp_alloc;
1665 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1667 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1668 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1669 kpti_remap_fn *remap_fn;
1671 int cpu = smp_processor_id();
1672 int levels = CONFIG_PGTABLE_LEVELS;
1673 int order = order_base_2(levels);
1674 u64 kpti_ng_temp_pgd_pa = 0;
1675 pgd_t *kpti_ng_temp_pgd;
1678 if (__this_cpu_read(this_cpu_vector) == vectors) {
1679 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1681 __this_cpu_write(this_cpu_vector, v);
1685 * We don't need to rewrite the page-tables if either we've done
1686 * it already or we have KASLR enabled and therefore have not
1687 * created any global mappings at all.
1689 if (arm64_use_ng_mappings)
1692 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1695 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1696 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1697 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1700 // Create a minimal page table hierarchy that permits us to map
1701 // the swapper page tables temporarily as we traverse them.
1703 // The physical pages are laid out as follows:
1705 // +--------+-/-------+-/------ +-\\--------+
1706 // : PTE[] : | PMD[] : | PUD[] : || PGD[] :
1707 // +--------+-\-------+-\------ +-//--------+
1709 // The first page is mapped into this hierarchy at a PMD_SHIFT
1710 // aligned virtual address, so that we can manipulate the PTE
1711 // level entries while the mapping is active. The first entry
1712 // covers the PTE[] page itself, the remaining entries are free
1713 // to be used as a ad-hoc fixmap.
1715 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1716 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1717 kpti_ng_pgd_alloc, 0);
1720 cpu_install_idmap();
1721 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1722 cpu_uninstall_idmap();
1725 free_pages(alloc, order);
1726 arm64_use_ng_mappings = true;
1731 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1734 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1736 static int __init parse_kpti(char *str)
1739 int ret = strtobool(str, &enabled);
1744 __kpti_forced = enabled ? 1 : -1;
1747 early_param("kpti", parse_kpti);
1749 #ifdef CONFIG_ARM64_HW_AFDBM
1750 static inline void __cpu_enable_hw_dbm(void)
1752 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1754 write_sysreg(tcr, tcr_el1);
1756 local_flush_tlb_all();
1759 static bool cpu_has_broken_dbm(void)
1761 /* List of CPUs which have broken DBM support. */
1762 static const struct midr_range cpus[] = {
1763 #ifdef CONFIG_ARM64_ERRATUM_1024718
1764 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1765 /* Kryo4xx Silver (rdpe => r1p0) */
1766 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1768 #ifdef CONFIG_ARM64_ERRATUM_2051678
1769 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1774 return is_midr_in_range_list(read_cpuid_id(), cpus);
1777 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1779 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1780 !cpu_has_broken_dbm();
1783 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1785 if (cpu_can_use_dbm(cap))
1786 __cpu_enable_hw_dbm();
1789 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1792 static bool detected = false;
1794 * DBM is a non-conflicting feature. i.e, the kernel can safely
1795 * run a mix of CPUs with and without the feature. So, we
1796 * unconditionally enable the capability to allow any late CPU
1797 * to use the feature. We only enable the control bits on the
1798 * CPU, if it actually supports.
1800 * We have to make sure we print the "feature" detection only
1801 * when at least one CPU actually uses it. So check if this CPU
1802 * can actually use it and print the message exactly once.
1804 * This is safe as all CPUs (including secondary CPUs - due to the
1805 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1806 * goes through the "matches" check exactly once. Also if a CPU
1807 * matches the criteria, it is guaranteed that the CPU will turn
1808 * the DBM on, as the capability is unconditionally enabled.
1810 if (!detected && cpu_can_use_dbm(cap)) {
1812 pr_info("detected: Hardware dirty bit management\n");
1820 #ifdef CONFIG_ARM64_AMU_EXTN
1823 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1824 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1825 * information regarding all the events that it supports. When a CPU bit is
1826 * set in the cpumask, the user of this feature can only rely on the presence
1827 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1828 * counters are enabled or access to these counters is enabled by code
1829 * executed at higher exception levels (firmware).
1831 static struct cpumask amu_cpus __read_mostly;
1833 bool cpu_has_amu_feat(int cpu)
1835 return cpumask_test_cpu(cpu, &amu_cpus);
1838 int get_cpu_with_amu_feat(void)
1840 return cpumask_any(&amu_cpus);
1843 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1845 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1846 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1847 smp_processor_id());
1848 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1849 update_freq_counters_refs();
1853 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1857 * The AMU extension is a non-conflicting feature: the kernel can
1858 * safely run a mix of CPUs with and without support for the
1859 * activity monitors extension. Therefore, unconditionally enable
1860 * the capability to allow any late CPU to use the feature.
1862 * With this feature unconditionally enabled, the cpu_enable
1863 * function will be called for all CPUs that match the criteria,
1864 * including secondary and hotplugged, marking this feature as
1865 * present on that respective CPU. The enable function will also
1866 * print a detection message.
1872 int get_cpu_with_amu_feat(void)
1878 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1880 return is_kernel_in_hyp_mode();
1883 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1886 * Copy register values that aren't redirected by hardware.
1888 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1889 * this value to tpidr_el2 before we patch the code. Once we've done
1890 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1893 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1894 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1897 #ifdef CONFIG_ARM64_PAN
1898 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1901 * We modify PSTATE. This won't work from irq context as the PSTATE
1902 * is discarded once we return from the exception.
1904 WARN_ON_ONCE(in_interrupt());
1906 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1909 #endif /* CONFIG_ARM64_PAN */
1911 #ifdef CONFIG_ARM64_RAS_EXTN
1912 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1914 /* Firmware may have left a deferred SError in this register. */
1915 write_sysreg_s(0, SYS_DISR_EL1);
1917 #endif /* CONFIG_ARM64_RAS_EXTN */
1919 #ifdef CONFIG_ARM64_PTR_AUTH
1920 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1922 int boot_val, sec_val;
1924 /* We don't expect to be called with SCOPE_SYSTEM */
1925 WARN_ON(scope == SCOPE_SYSTEM);
1927 * The ptr-auth feature levels are not intercompatible with lower
1928 * levels. Hence we must match ptr-auth feature level of the secondary
1929 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1930 * from the sanitised register whereas direct register read is done for
1931 * the secondary CPUs.
1932 * The sanitised feature state is guaranteed to match that of the
1933 * boot CPU as a mismatched secondary CPU is parked before it gets
1934 * a chance to update the state, with the capability.
1936 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1937 entry->field_pos, entry->sign);
1938 if (scope & SCOPE_BOOT_CPU)
1939 return boot_val >= entry->min_field_value;
1940 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1941 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1942 entry->field_pos, entry->sign);
1943 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
1946 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1949 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1950 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
1951 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
1953 return apa || apa3 || api;
1956 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1959 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1960 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
1961 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
1963 return gpa || gpa3 || gpi;
1965 #endif /* CONFIG_ARM64_PTR_AUTH */
1967 #ifdef CONFIG_ARM64_E0PD
1968 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1970 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1971 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1973 #endif /* CONFIG_ARM64_E0PD */
1975 #ifdef CONFIG_ARM64_PSEUDO_NMI
1976 static bool enable_pseudo_nmi;
1978 static int __init early_enable_pseudo_nmi(char *p)
1980 return strtobool(p, &enable_pseudo_nmi);
1982 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1984 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1987 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1991 #ifdef CONFIG_ARM64_BTI
1992 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1995 * Use of X16/X17 for tail-calls and trampolines that jump to
1996 * function entry points using BR is a requirement for
1997 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1998 * So, be strict and forbid other BRs using other registers to
1999 * jump onto a PACIxSP instruction:
2001 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2004 #endif /* CONFIG_ARM64_BTI */
2006 #ifdef CONFIG_ARM64_MTE
2007 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2009 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2013 * Clear the tags in the zero page. This needs to be done via the
2014 * linear map which has the Tagged attribute.
2016 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
2017 mte_clear_page_tags(lm_alias(empty_zero_page));
2019 kasan_init_hw_tags_cpu();
2021 #endif /* CONFIG_ARM64_MTE */
2023 static void elf_hwcap_fixup(void)
2025 #ifdef CONFIG_ARM64_ERRATUM_1742098
2026 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
2027 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2028 #endif /* ARM64_ERRATUM_1742098 */
2032 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2034 return kvm_get_mode() == KVM_MODE_PROTECTED;
2036 #endif /* CONFIG_KVM */
2038 /* Internal helper functions to match cpu capability type */
2040 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2042 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2046 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2048 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2052 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2054 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2057 static const struct arm64_cpu_capabilities arm64_features[] = {
2059 .desc = "GIC system register CPU interface",
2060 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
2061 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2062 .matches = has_useable_gicv3_cpuif,
2063 .sys_reg = SYS_ID_AA64PFR0_EL1,
2064 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2066 .sign = FTR_UNSIGNED,
2067 .min_field_value = 1,
2070 .desc = "Enhanced Counter Virtualization",
2071 .capability = ARM64_HAS_ECV,
2072 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2073 .matches = has_cpuid_feature,
2074 .sys_reg = SYS_ID_AA64MMFR0_EL1,
2075 .field_pos = ID_AA64MMFR0_ECV_SHIFT,
2077 .sign = FTR_UNSIGNED,
2078 .min_field_value = 1,
2080 #ifdef CONFIG_ARM64_PAN
2082 .desc = "Privileged Access Never",
2083 .capability = ARM64_HAS_PAN,
2084 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2085 .matches = has_cpuid_feature,
2086 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2087 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2089 .sign = FTR_UNSIGNED,
2090 .min_field_value = 1,
2091 .cpu_enable = cpu_enable_pan,
2093 #endif /* CONFIG_ARM64_PAN */
2094 #ifdef CONFIG_ARM64_EPAN
2096 .desc = "Enhanced Privileged Access Never",
2097 .capability = ARM64_HAS_EPAN,
2098 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2099 .matches = has_cpuid_feature,
2100 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2101 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2103 .sign = FTR_UNSIGNED,
2104 .min_field_value = 3,
2106 #endif /* CONFIG_ARM64_EPAN */
2107 #ifdef CONFIG_ARM64_LSE_ATOMICS
2109 .desc = "LSE atomic instructions",
2110 .capability = ARM64_HAS_LSE_ATOMICS,
2111 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2112 .matches = has_cpuid_feature,
2113 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2114 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
2116 .sign = FTR_UNSIGNED,
2117 .min_field_value = 2,
2119 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2121 .desc = "Software prefetching using PRFM",
2122 .capability = ARM64_HAS_NO_HW_PREFETCH,
2123 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2124 .matches = has_no_hw_prefetch,
2127 .desc = "Virtualization Host Extensions",
2128 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2129 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2130 .matches = runs_at_el2,
2131 .cpu_enable = cpu_copy_el2regs,
2134 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2135 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2136 .matches = has_32bit_el0,
2137 .sys_reg = SYS_ID_AA64PFR0_EL1,
2138 .sign = FTR_UNSIGNED,
2139 .field_pos = ID_AA64PFR0_EL0_SHIFT,
2141 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2145 .desc = "32-bit EL1 Support",
2146 .capability = ARM64_HAS_32BIT_EL1,
2147 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2148 .matches = has_cpuid_feature,
2149 .sys_reg = SYS_ID_AA64PFR0_EL1,
2150 .sign = FTR_UNSIGNED,
2151 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2153 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2156 .desc = "Protected KVM",
2157 .capability = ARM64_KVM_PROTECTED_MODE,
2158 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2159 .matches = is_kvm_protected_mode,
2163 .desc = "Kernel page table isolation (KPTI)",
2164 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2165 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2167 * The ID feature fields below are used to indicate that
2168 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2171 .sys_reg = SYS_ID_AA64PFR0_EL1,
2172 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2174 .min_field_value = 1,
2175 .matches = unmap_kernel_at_el0,
2176 .cpu_enable = kpti_install_ng_mappings,
2179 /* FP/SIMD is not implemented */
2180 .capability = ARM64_HAS_NO_FPSIMD,
2181 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2182 .min_field_value = 0,
2183 .matches = has_no_fpsimd,
2185 #ifdef CONFIG_ARM64_PMEM
2187 .desc = "Data cache clean to Point of Persistence",
2188 .capability = ARM64_HAS_DCPOP,
2189 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2190 .matches = has_cpuid_feature,
2191 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2192 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2194 .min_field_value = 1,
2197 .desc = "Data cache clean to Point of Deep Persistence",
2198 .capability = ARM64_HAS_DCPODP,
2199 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2200 .matches = has_cpuid_feature,
2201 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2202 .sign = FTR_UNSIGNED,
2203 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2205 .min_field_value = 2,
2208 #ifdef CONFIG_ARM64_SVE
2210 .desc = "Scalable Vector Extension",
2211 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2212 .capability = ARM64_SVE,
2213 .sys_reg = SYS_ID_AA64PFR0_EL1,
2214 .sign = FTR_UNSIGNED,
2215 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2217 .min_field_value = ID_AA64PFR0_SVE,
2218 .matches = has_cpuid_feature,
2219 .cpu_enable = sve_kernel_enable,
2221 #endif /* CONFIG_ARM64_SVE */
2222 #ifdef CONFIG_ARM64_RAS_EXTN
2224 .desc = "RAS Extension Support",
2225 .capability = ARM64_HAS_RAS_EXTN,
2226 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2227 .matches = has_cpuid_feature,
2228 .sys_reg = SYS_ID_AA64PFR0_EL1,
2229 .sign = FTR_UNSIGNED,
2230 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2232 .min_field_value = ID_AA64PFR0_RAS_V1,
2233 .cpu_enable = cpu_clear_disr,
2235 #endif /* CONFIG_ARM64_RAS_EXTN */
2236 #ifdef CONFIG_ARM64_AMU_EXTN
2239 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2240 * Therefore, don't provide .desc as we don't want the detection
2241 * message to be shown until at least one CPU is detected to
2242 * support the feature.
2244 .capability = ARM64_HAS_AMU_EXTN,
2245 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2247 .sys_reg = SYS_ID_AA64PFR0_EL1,
2248 .sign = FTR_UNSIGNED,
2249 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2251 .min_field_value = ID_AA64PFR0_AMU,
2252 .cpu_enable = cpu_amu_enable,
2254 #endif /* CONFIG_ARM64_AMU_EXTN */
2256 .desc = "Data cache clean to the PoU not required for I/D coherence",
2257 .capability = ARM64_HAS_CACHE_IDC,
2258 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2259 .matches = has_cache_idc,
2260 .cpu_enable = cpu_emulate_effective_ctr,
2263 .desc = "Instruction cache invalidation not required for I/D coherence",
2264 .capability = ARM64_HAS_CACHE_DIC,
2265 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2266 .matches = has_cache_dic,
2269 .desc = "Stage-2 Force Write-Back",
2270 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2271 .capability = ARM64_HAS_STAGE2_FWB,
2272 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2273 .sign = FTR_UNSIGNED,
2274 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2276 .min_field_value = 1,
2277 .matches = has_cpuid_feature,
2280 .desc = "ARMv8.4 Translation Table Level",
2281 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2282 .capability = ARM64_HAS_ARMv8_4_TTL,
2283 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2284 .sign = FTR_UNSIGNED,
2285 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2287 .min_field_value = 1,
2288 .matches = has_cpuid_feature,
2291 .desc = "TLB range maintenance instructions",
2292 .capability = ARM64_HAS_TLB_RANGE,
2293 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2294 .matches = has_cpuid_feature,
2295 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2296 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
2298 .sign = FTR_UNSIGNED,
2299 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
2301 #ifdef CONFIG_ARM64_HW_AFDBM
2304 * Since we turn this on always, we don't want the user to
2305 * think that the feature is available when it may not be.
2306 * So hide the description.
2308 * .desc = "Hardware pagetable Dirty Bit Management",
2311 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2312 .capability = ARM64_HW_DBM,
2313 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2314 .sign = FTR_UNSIGNED,
2315 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2317 .min_field_value = 2,
2318 .matches = has_hw_dbm,
2319 .cpu_enable = cpu_enable_hw_dbm,
2323 .desc = "CRC32 instructions",
2324 .capability = ARM64_HAS_CRC32,
2325 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2326 .matches = has_cpuid_feature,
2327 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2328 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
2330 .min_field_value = 1,
2333 .desc = "Speculative Store Bypassing Safe (SSBS)",
2334 .capability = ARM64_SSBS,
2335 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2336 .matches = has_cpuid_feature,
2337 .sys_reg = SYS_ID_AA64PFR1_EL1,
2338 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2340 .sign = FTR_UNSIGNED,
2341 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2343 #ifdef CONFIG_ARM64_CNP
2345 .desc = "Common not Private translations",
2346 .capability = ARM64_HAS_CNP,
2347 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2348 .matches = has_useable_cnp,
2349 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2350 .sign = FTR_UNSIGNED,
2351 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2353 .min_field_value = 1,
2354 .cpu_enable = cpu_enable_cnp,
2358 .desc = "Speculation barrier (SB)",
2359 .capability = ARM64_HAS_SB,
2360 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2361 .matches = has_cpuid_feature,
2362 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2363 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2365 .sign = FTR_UNSIGNED,
2366 .min_field_value = 1,
2368 #ifdef CONFIG_ARM64_PTR_AUTH
2370 .desc = "Address authentication (architected QARMA5 algorithm)",
2371 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2372 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2373 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2374 .sign = FTR_UNSIGNED,
2375 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2377 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2378 .matches = has_address_auth_cpucap,
2381 .desc = "Address authentication (architected QARMA3 algorithm)",
2382 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2383 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2384 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2385 .sign = FTR_UNSIGNED,
2386 .field_pos = ID_AA64ISAR2_APA3_SHIFT,
2388 .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
2389 .matches = has_address_auth_cpucap,
2392 .desc = "Address authentication (IMP DEF algorithm)",
2393 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2394 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2395 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2396 .sign = FTR_UNSIGNED,
2397 .field_pos = ID_AA64ISAR1_API_SHIFT,
2399 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2400 .matches = has_address_auth_cpucap,
2403 .capability = ARM64_HAS_ADDRESS_AUTH,
2404 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2405 .matches = has_address_auth_metacap,
2408 .desc = "Generic authentication (architected QARMA5 algorithm)",
2409 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2410 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2411 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2412 .sign = FTR_UNSIGNED,
2413 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2415 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2416 .matches = has_cpuid_feature,
2419 .desc = "Generic authentication (architected QARMA3 algorithm)",
2420 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2421 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2422 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2423 .sign = FTR_UNSIGNED,
2424 .field_pos = ID_AA64ISAR2_GPA3_SHIFT,
2426 .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
2427 .matches = has_cpuid_feature,
2430 .desc = "Generic authentication (IMP DEF algorithm)",
2431 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2432 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2433 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2434 .sign = FTR_UNSIGNED,
2435 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2437 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2438 .matches = has_cpuid_feature,
2441 .capability = ARM64_HAS_GENERIC_AUTH,
2442 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2443 .matches = has_generic_auth,
2445 #endif /* CONFIG_ARM64_PTR_AUTH */
2446 #ifdef CONFIG_ARM64_PSEUDO_NMI
2449 * Depends on having GICv3
2451 .desc = "IRQ priority masking",
2452 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2453 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2454 .matches = can_use_gic_priorities,
2455 .sys_reg = SYS_ID_AA64PFR0_EL1,
2456 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2458 .sign = FTR_UNSIGNED,
2459 .min_field_value = 1,
2462 #ifdef CONFIG_ARM64_E0PD
2465 .capability = ARM64_HAS_E0PD,
2466 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2467 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2468 .sign = FTR_UNSIGNED,
2470 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2471 .matches = has_cpuid_feature,
2472 .min_field_value = 1,
2473 .cpu_enable = cpu_enable_e0pd,
2476 #ifdef CONFIG_ARCH_RANDOM
2478 .desc = "Random Number Generator",
2479 .capability = ARM64_HAS_RNG,
2480 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2481 .matches = has_cpuid_feature,
2482 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2483 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
2485 .sign = FTR_UNSIGNED,
2486 .min_field_value = 1,
2489 #ifdef CONFIG_ARM64_BTI
2491 .desc = "Branch Target Identification",
2492 .capability = ARM64_BTI,
2493 #ifdef CONFIG_ARM64_BTI_KERNEL
2494 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2498 .matches = has_cpuid_feature,
2499 .cpu_enable = bti_enable,
2500 .sys_reg = SYS_ID_AA64PFR1_EL1,
2501 .field_pos = ID_AA64PFR1_BT_SHIFT,
2503 .min_field_value = ID_AA64PFR1_BT_BTI,
2504 .sign = FTR_UNSIGNED,
2507 #ifdef CONFIG_ARM64_MTE
2509 .desc = "Memory Tagging Extension",
2510 .capability = ARM64_MTE,
2511 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2512 .matches = has_cpuid_feature,
2513 .sys_reg = SYS_ID_AA64PFR1_EL1,
2514 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2516 .min_field_value = ID_AA64PFR1_MTE,
2517 .sign = FTR_UNSIGNED,
2518 .cpu_enable = cpu_enable_mte,
2521 .desc = "Asymmetric MTE Tag Check Fault",
2522 .capability = ARM64_MTE_ASYMM,
2523 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2524 .matches = has_cpuid_feature,
2525 .sys_reg = SYS_ID_AA64PFR1_EL1,
2526 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2528 .min_field_value = ID_AA64PFR1_MTE_ASYMM,
2529 .sign = FTR_UNSIGNED,
2531 #endif /* CONFIG_ARM64_MTE */
2533 .desc = "RCpc load-acquire (LDAPR)",
2534 .capability = ARM64_HAS_LDAPR,
2535 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2536 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2537 .sign = FTR_UNSIGNED,
2538 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2540 .matches = has_cpuid_feature,
2541 .min_field_value = 1,
2543 #ifdef CONFIG_ARM64_SME
2545 .desc = "Scalable Matrix Extension",
2546 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2547 .capability = ARM64_SME,
2548 .sys_reg = SYS_ID_AA64PFR1_EL1,
2549 .sign = FTR_UNSIGNED,
2550 .field_pos = ID_AA64PFR1_SME_SHIFT,
2552 .min_field_value = ID_AA64PFR1_SME,
2553 .matches = has_cpuid_feature,
2554 .cpu_enable = sme_kernel_enable,
2556 /* FA64 should be sorted after the base SME capability */
2559 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2560 .capability = ARM64_SME_FA64,
2561 .sys_reg = SYS_ID_AA64SMFR0_EL1,
2562 .sign = FTR_UNSIGNED,
2563 .field_pos = ID_AA64SMFR0_FA64_SHIFT,
2565 .min_field_value = ID_AA64SMFR0_FA64,
2566 .matches = has_cpuid_feature,
2567 .cpu_enable = fa64_kernel_enable,
2569 #endif /* CONFIG_ARM64_SME */
2571 .desc = "WFx with timeout",
2572 .capability = ARM64_HAS_WFXT,
2573 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2574 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2575 .sign = FTR_UNSIGNED,
2576 .field_pos = ID_AA64ISAR2_WFXT_SHIFT,
2578 .matches = has_cpuid_feature,
2579 .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
2584 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2585 .matches = has_cpuid_feature, \
2587 .field_pos = field, \
2588 .field_width = width, \
2590 .min_field_value = min_value,
2592 #define __HWCAP_CAP(name, cap_type, cap) \
2594 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2595 .hwcap_type = cap_type, \
2598 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \
2600 __HWCAP_CAP(#cap, cap_type, cap) \
2601 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2604 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2606 __HWCAP_CAP(#cap, cap_type, cap) \
2607 .matches = cpucap_multi_entry_cap_matches, \
2608 .match_list = list, \
2611 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2613 __HWCAP_CAP(#cap, cap_type, cap) \
2617 #ifdef CONFIG_ARM64_PTR_AUTH
2618 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2620 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2622 ID_AA64ISAR1_APA_ARCHITECTED)
2625 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
2626 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
2629 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2630 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2635 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2637 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2638 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2641 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
2642 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
2645 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2646 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2652 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2653 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2654 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2655 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2656 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2657 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2658 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2659 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2660 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2661 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2662 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2663 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2664 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2665 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2666 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2667 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2668 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2669 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2670 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2671 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2672 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2673 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2674 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2675 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2676 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2677 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2678 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2679 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2680 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2681 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2682 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2683 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2684 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2685 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2686 #ifdef CONFIG_ARM64_SVE
2687 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2688 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2689 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2690 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2691 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2692 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2693 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2694 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2695 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2696 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2697 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2699 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2700 #ifdef CONFIG_ARM64_BTI
2701 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2703 #ifdef CONFIG_ARM64_PTR_AUTH
2704 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2705 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2707 #ifdef CONFIG_ARM64_MTE
2708 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2709 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2710 #endif /* CONFIG_ARM64_MTE */
2711 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2712 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2713 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2714 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2715 #ifdef CONFIG_ARM64_SME
2716 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
2717 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2718 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2719 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2720 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2721 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2722 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2723 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2724 #endif /* CONFIG_ARM64_SME */
2728 #ifdef CONFIG_COMPAT
2729 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2732 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2733 * in line with that of arm32 as in vfp_init(). We make sure that the
2734 * check is future proof, by making sure value is non-zero.
2738 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2739 if (scope == SCOPE_SYSTEM)
2740 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2742 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2744 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2745 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2746 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2750 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2751 #ifdef CONFIG_COMPAT
2752 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2753 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2754 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2755 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2756 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2757 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2758 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2759 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2760 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2761 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2766 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2768 switch (cap->hwcap_type) {
2770 cpu_set_feature(cap->hwcap);
2772 #ifdef CONFIG_COMPAT
2773 case CAP_COMPAT_HWCAP:
2774 compat_elf_hwcap |= (u32)cap->hwcap;
2776 case CAP_COMPAT_HWCAP2:
2777 compat_elf_hwcap2 |= (u32)cap->hwcap;
2786 /* Check if we have a particular HWCAP enabled */
2787 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2791 switch (cap->hwcap_type) {
2793 rc = cpu_have_feature(cap->hwcap);
2795 #ifdef CONFIG_COMPAT
2796 case CAP_COMPAT_HWCAP:
2797 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2799 case CAP_COMPAT_HWCAP2:
2800 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2811 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2813 /* We support emulation of accesses to CPU ID feature registers */
2814 cpu_set_named_feature(CPUID);
2815 for (; hwcaps->matches; hwcaps++)
2816 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2817 cap_set_elf_hwcap(hwcaps);
2820 static void update_cpu_capabilities(u16 scope_mask)
2823 const struct arm64_cpu_capabilities *caps;
2825 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2826 for (i = 0; i < ARM64_NCAPS; i++) {
2827 caps = cpu_hwcaps_ptrs[i];
2828 if (!caps || !(caps->type & scope_mask) ||
2829 cpus_have_cap(caps->capability) ||
2830 !caps->matches(caps, cpucap_default_scope(caps)))
2834 pr_info("detected: %s\n", caps->desc);
2835 cpus_set_cap(caps->capability);
2837 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2838 set_bit(caps->capability, boot_capabilities);
2843 * Enable all the available capabilities on this CPU. The capabilities
2844 * with BOOT_CPU scope are handled separately and hence skipped here.
2846 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2849 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2851 for_each_available_cap(i) {
2852 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2857 if (!(cap->type & non_boot_scope))
2860 if (cap->cpu_enable)
2861 cap->cpu_enable(cap);
2867 * Run through the enabled capabilities and enable() it on all active
2870 static void __init enable_cpu_capabilities(u16 scope_mask)
2873 const struct arm64_cpu_capabilities *caps;
2876 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2877 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2879 for (i = 0; i < ARM64_NCAPS; i++) {
2882 caps = cpu_hwcaps_ptrs[i];
2883 if (!caps || !(caps->type & scope_mask))
2885 num = caps->capability;
2886 if (!cpus_have_cap(num))
2889 /* Ensure cpus_have_const_cap(num) works */
2890 static_branch_enable(&cpu_hwcap_keys[num]);
2892 if (boot_scope && caps->cpu_enable)
2894 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2895 * before any secondary CPU boots. Thus, each secondary
2896 * will enable the capability as appropriate via
2897 * check_local_cpu_capabilities(). The only exception is
2898 * the boot CPU, for which the capability must be
2899 * enabled here. This approach avoids costly
2900 * stop_machine() calls for this case.
2902 caps->cpu_enable(caps);
2906 * For all non-boot scope capabilities, use stop_machine()
2907 * as it schedules the work allowing us to modify PSTATE,
2908 * instead of on_each_cpu() which uses an IPI, giving us a
2909 * PSTATE that disappears when we return.
2912 stop_machine(cpu_enable_non_boot_scope_capabilities,
2913 NULL, cpu_online_mask);
2917 * Run through the list of capabilities to check for conflicts.
2918 * If the system has already detected a capability, take necessary
2919 * action on this CPU.
2921 static void verify_local_cpu_caps(u16 scope_mask)
2924 bool cpu_has_cap, system_has_cap;
2925 const struct arm64_cpu_capabilities *caps;
2927 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2929 for (i = 0; i < ARM64_NCAPS; i++) {
2930 caps = cpu_hwcaps_ptrs[i];
2931 if (!caps || !(caps->type & scope_mask))
2934 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2935 system_has_cap = cpus_have_cap(caps->capability);
2937 if (system_has_cap) {
2939 * Check if the new CPU misses an advertised feature,
2940 * which is not safe to miss.
2942 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2945 * We have to issue cpu_enable() irrespective of
2946 * whether the CPU has it or not, as it is enabeld
2947 * system wide. It is upto the call back to take
2948 * appropriate action on this CPU.
2950 if (caps->cpu_enable)
2951 caps->cpu_enable(caps);
2954 * Check if the CPU has this capability if it isn't
2955 * safe to have when the system doesn't.
2957 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2962 if (i < ARM64_NCAPS) {
2963 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2964 smp_processor_id(), caps->capability,
2965 caps->desc, system_has_cap, cpu_has_cap);
2967 if (cpucap_panic_on_conflict(caps))
2975 * Check for CPU features that are used in early boot
2976 * based on the Boot CPU value.
2978 static void check_early_cpu_features(void)
2980 verify_cpu_asid_bits();
2982 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2986 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2989 for (; caps->matches; caps++)
2990 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2991 pr_crit("CPU%d: missing HWCAP: %s\n",
2992 smp_processor_id(), caps->desc);
2997 static void verify_local_elf_hwcaps(void)
2999 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3001 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3002 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3005 static void verify_sve_features(void)
3007 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
3008 u64 zcr = read_zcr_features();
3010 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
3011 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
3013 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
3014 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3015 smp_processor_id());
3019 /* Add checks on other ZCR bits here if necessary */
3022 static void verify_sme_features(void)
3024 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
3025 u64 smcr = read_smcr_features();
3027 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
3028 unsigned int len = smcr & SMCR_ELx_LEN_MASK;
3030 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
3031 pr_crit("CPU%d: SME: vector length support mismatch\n",
3032 smp_processor_id());
3036 /* Add checks on other SMCR bits here if necessary */
3039 static void verify_hyp_capabilities(void)
3041 u64 safe_mmfr1, mmfr0, mmfr1;
3042 int parange, ipa_max;
3043 unsigned int safe_vmid_bits, vmid_bits;
3045 if (!IS_ENABLED(CONFIG_KVM))
3048 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3049 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3050 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3052 /* Verify VMID bits */
3053 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3054 vmid_bits = get_vmid_bits(mmfr1);
3055 if (vmid_bits < safe_vmid_bits) {
3056 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3060 /* Verify IPA range */
3061 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3062 ID_AA64MMFR0_PARANGE_SHIFT);
3063 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3064 if (ipa_max < get_kvm_ipa_limit()) {
3065 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3071 * Run through the enabled system capabilities and enable() it on this CPU.
3072 * The capabilities were decided based on the available CPUs at the boot time.
3073 * Any new CPU should match the system wide status of the capability. If the
3074 * new CPU doesn't have a capability which the system now has enabled, we
3075 * cannot do anything to fix it up and could cause unexpected failures. So
3078 static void verify_local_cpu_capabilities(void)
3081 * The capabilities with SCOPE_BOOT_CPU are checked from
3082 * check_early_cpu_features(), as they need to be verified
3083 * on all secondary CPUs.
3085 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3086 verify_local_elf_hwcaps();
3088 if (system_supports_sve())
3089 verify_sve_features();
3091 if (system_supports_sme())
3092 verify_sme_features();
3094 if (is_hyp_mode_available())
3095 verify_hyp_capabilities();
3098 void check_local_cpu_capabilities(void)
3101 * All secondary CPUs should conform to the early CPU features
3102 * in use by the kernel based on boot CPU.
3104 check_early_cpu_features();
3107 * If we haven't finalised the system capabilities, this CPU gets
3108 * a chance to update the errata work arounds and local features.
3109 * Otherwise, this CPU should verify that it has all the system
3110 * advertised capabilities.
3112 if (!system_capabilities_finalized())
3113 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3115 verify_local_cpu_capabilities();
3118 static void __init setup_boot_cpu_capabilities(void)
3120 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3121 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3122 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3123 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3126 bool this_cpu_has_cap(unsigned int n)
3128 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3129 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3132 return cap->matches(cap, SCOPE_LOCAL_CPU);
3137 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3140 * This helper function is used in a narrow window when,
3141 * - The system wide safe registers are set with all the SMP CPUs and,
3142 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
3143 * In all other cases cpus_have_{const_}cap() should be used.
3145 static bool __maybe_unused __system_matches_cap(unsigned int n)
3147 if (n < ARM64_NCAPS) {
3148 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3151 return cap->matches(cap, SCOPE_SYSTEM);
3156 void cpu_set_feature(unsigned int num)
3158 WARN_ON(num >= MAX_CPU_FEATURES);
3159 elf_hwcap |= BIT(num);
3162 bool cpu_have_feature(unsigned int num)
3164 WARN_ON(num >= MAX_CPU_FEATURES);
3165 return elf_hwcap & BIT(num);
3167 EXPORT_SYMBOL_GPL(cpu_have_feature);
3169 unsigned long cpu_get_elf_hwcap(void)
3172 * We currently only populate the first 32 bits of AT_HWCAP. Please
3173 * note that for userspace compatibility we guarantee that bits 62
3174 * and 63 will always be returned as 0.
3176 return lower_32_bits(elf_hwcap);
3179 unsigned long cpu_get_elf_hwcap2(void)
3181 return upper_32_bits(elf_hwcap);
3184 static void __init setup_system_capabilities(void)
3187 * We have finalised the system-wide safe feature
3188 * registers, finalise the capabilities that depend
3189 * on it. Also enable all the available capabilities,
3190 * that are not enabled already.
3192 update_cpu_capabilities(SCOPE_SYSTEM);
3193 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3196 void __init setup_cpu_features(void)
3200 setup_system_capabilities();
3201 setup_elf_hwcaps(arm64_elf_hwcaps);
3203 if (system_supports_32bit_el0()) {
3204 setup_elf_hwcaps(compat_elf_hwcaps);
3208 if (system_uses_ttbr0_pan())
3209 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3213 minsigstksz_setup();
3215 /* Advertise that we have computed the system capabilities */
3216 finalize_system_capabilities();
3219 * Check for sane CTR_EL0.CWG value.
3221 cwg = cache_type_cwg();
3223 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3227 static int enable_mismatched_32bit_el0(unsigned int cpu)
3230 * The first 32-bit-capable CPU we detected and so can no longer
3231 * be offlined by userspace. -1 indicates we haven't yet onlined
3232 * a 32-bit-capable CPU.
3234 static int lucky_winner = -1;
3236 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3237 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3240 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3241 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3244 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3247 if (lucky_winner >= 0)
3251 * We've detected a mismatch. We need to keep one of our CPUs with
3252 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3253 * every CPU in the system for a 32-bit task.
3255 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3257 get_cpu_device(lucky_winner)->offline_disabled = true;
3258 setup_elf_hwcaps(compat_elf_hwcaps);
3260 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3265 static int __init init_32bit_el0_mask(void)
3267 if (!allow_mismatched_32bit_el0)
3270 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3273 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3274 "arm64/mismatched_32bit_el0:online",
3275 enable_mismatched_32bit_el0, NULL);
3277 subsys_initcall_sync(init_32bit_el0_mask);
3279 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3281 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
3285 * We emulate only the following system register space.
3286 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3287 * See Table C5-6 System instruction encodings for System register accesses,
3288 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3290 static inline bool __attribute_const__ is_emulated(u32 id)
3292 return (sys_reg_Op0(id) == 0x3 &&
3293 sys_reg_CRn(id) == 0x0 &&
3294 sys_reg_Op1(id) == 0x0 &&
3295 (sys_reg_CRm(id) == 0 ||
3296 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3300 * With CRm == 0, reg should be one of :
3301 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3303 static inline int emulate_id_reg(u32 id, u64 *valp)
3307 *valp = read_cpuid_id();
3310 *valp = SYS_MPIDR_SAFE_VAL;
3312 case SYS_REVIDR_EL1:
3313 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3323 static int emulate_sys_reg(u32 id, u64 *valp)
3325 struct arm64_ftr_reg *regp;
3327 if (!is_emulated(id))
3330 if (sys_reg_CRm(id) == 0)
3331 return emulate_id_reg(id, valp);
3333 regp = get_arm64_ftr_reg_nowarn(id);
3335 *valp = arm64_ftr_reg_user_value(regp);
3338 * The untracked registers are either IMPLEMENTATION DEFINED
3339 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3345 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3350 rc = emulate_sys_reg(sys_reg, &val);
3352 pt_regs_write_reg(regs, rt, val);
3353 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3358 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3363 * sys_reg values are defined as used in mrs/msr instruction.
3364 * shift the imm value to get the encoding.
3366 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3367 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3368 return do_emulate_mrs(regs, sys_reg, rt);
3371 static struct undef_hook mrs_hook = {
3372 .instr_mask = 0xffff0000,
3373 .instr_val = 0xd5380000,
3374 .pstate_mask = PSR_AA32_MODE_MASK,
3375 .pstate_val = PSR_MODE_EL0t,
3379 static int __init enable_mrs_emulation(void)
3381 register_undef_hook(&mrs_hook);
3385 core_initcall(enable_mrs_emulation);
3387 enum mitigation_state arm64_get_meltdown_state(void)
3389 if (__meltdown_safe)
3390 return SPECTRE_UNAFFECTED;
3392 if (arm64_kernel_unmapped_at_el0())
3393 return SPECTRE_MITIGATED;
3395 return SPECTRE_VULNERABLE;
3398 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3401 switch (arm64_get_meltdown_state()) {
3402 case SPECTRE_UNAFFECTED:
3403 return sprintf(buf, "Not affected\n");
3405 case SPECTRE_MITIGATED:
3406 return sprintf(buf, "Mitigation: PTI\n");
3409 return sprintf(buf, "Vulnerable\n");