arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/processor.h>
  31 #include <asm/sysreg.h>
  32 #include <asm/virt.h>
  33
  34 unsigned long elf_hwcap __read_mostly;
  35 EXPORT_SYMBOL_GPL(elf_hwcap);
  36
  37 #ifdef CONFIG_COMPAT
  38 #define COMPAT_ELF_HWCAP_DEFAULT        \
  39                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  40                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  41                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  42                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  43                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  44                                  COMPAT_HWCAP_LPAE)
  45 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  46 unsigned int compat_elf_hwcap2 __read_mostly;
  47 #endif
  48
  49 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  50 EXPORT_SYMBOL(cpu_hwcaps);
  51
  52 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  53         {                                               \
  54                 .sign = SIGNED,                         \
  55                 .strict = STRICT,                       \
  56                 .type = TYPE,                           \
  57                 .shift = SHIFT,                         \
  58                 .width = WIDTH,                         \
  59                 .safe_val = SAFE_VAL,                   \
  60         }
  61
  62 /* Define a feature with signed values */
  63 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  65
  66 /* Define a feature with unsigned value */
  67 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  68         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  69
  70 #define ARM64_FTR_END                                   \
  71         {                                               \
  72                 .width = 0,                             \
  73         }
  74
  75 /* meta feature for alternatives */
  76 static bool __maybe_unused
  77 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
  78
  79 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  87         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  88         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  89         ARM64_FTR_END,
  90 };
  91
  92 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  95         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
  96         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  97         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  99         /* Linux doesn't care about the EL3 */
 100         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 101         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 102         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 104         ARM64_FTR_END,
 105 };
 106
 107 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 109         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 110         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 111         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 112         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 113         /* Linux shouldn't care about secure memory */
 114         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 115         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 116         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 117         /*
 118          * Differing PARange is fine as long as all peripherals and memory are mapped
 119          * within the minimum PARange of all CPUs
 120          */
 121         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 122         ARM64_FTR_END,
 123 };
 124
 125 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 133         ARM64_FTR_END,
 134 };
 135
 136 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 137         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 138         ARM64_FTR_END,
 139 };
 140
 141 static struct arm64_ftr_bits ftr_ctr[] = {
 142         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RAO */
 143         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 144         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),        /* CWG */
 145         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
 146         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 147         /*
 148          * Linux can handle differing I-cache policies. Userspace JITs will
 149          * make use of *minLine
 150          */
 151         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 152         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 153         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 154         ARM64_FTR_END,
 155 };
 156
 157 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 158         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 159         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 160         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 161         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 162         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 163         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 164         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 166         ARM64_FTR_END,
 167 };
 168
 169 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 170         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 171         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 172         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 173         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 174         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 175         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 176         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 177         ARM64_FTR_END,
 178 };
 179
 180 static struct arm64_ftr_bits ftr_mvfr2[] = {
 181         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 182         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 184         ARM64_FTR_END,
 185 };
 186
 187 static struct arm64_ftr_bits ftr_dczid[] = {
 188         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 189         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 191         ARM64_FTR_END,
 192 };
 193
 194
 195 static struct arm64_ftr_bits ftr_id_isar5[] = {
 196         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 199         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 200         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 201         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 203         ARM64_FTR_END,
 204 };
 205
 206 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 207         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 208         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 210         ARM64_FTR_END,
 211 };
 212
 213 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 214         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 215         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 216         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 217         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 219         ARM64_FTR_END,
 220 };
 221
 222 /*
 223  * Common ftr bits for a 32bit register with all hidden, strict
 224  * attributes, with 4bit feature fields and a default safe value of
 225  * 0. Covers the following 32bit registers:
 226  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 227  */
 228 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 229         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 230         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 232         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 233         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 234         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 235         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 236         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 237         ARM64_FTR_END,
 238 };
 239
 240 static struct arm64_ftr_bits ftr_generic[] = {
 241         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 242         ARM64_FTR_END,
 243 };
 244
 245 static struct arm64_ftr_bits ftr_generic32[] = {
 246         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 247         ARM64_FTR_END,
 248 };
 249
 250 static struct arm64_ftr_bits ftr_aa64raz[] = {
 251         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 252         ARM64_FTR_END,
 253 };
 254
 255 #define ARM64_FTR_REG(id, table)                \
 256         {                                       \
 257                 .sys_id = id,                   \
 258                 .name = #id,                    \
 259                 .ftr_bits = &((table)[0]),      \
 260         }
 261
 262 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 263
 264         /* Op1 = 0, CRn = 0, CRm = 1 */
 265         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 266         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 267         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 268         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 269         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 270         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 271         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 272
 273         /* Op1 = 0, CRn = 0, CRm = 2 */
 274         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 275         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 276         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 277         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 278         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 279         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 280         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 281
 282         /* Op1 = 0, CRn = 0, CRm = 3 */
 283         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 284         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 285         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 286
 287         /* Op1 = 0, CRn = 0, CRm = 4 */
 288         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 289         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 290
 291         /* Op1 = 0, CRn = 0, CRm = 5 */
 292         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 293         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 294
 295         /* Op1 = 0, CRn = 0, CRm = 6 */
 296         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 297         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 298
 299         /* Op1 = 0, CRn = 0, CRm = 7 */
 300         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 301         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 302         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 303
 304         /* Op1 = 3, CRn = 0, CRm = 0 */
 305         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 306         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 307
 308         /* Op1 = 3, CRn = 14, CRm = 0 */
 309         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 310 };
 311
 312 static int search_cmp_ftr_reg(const void *id, const void *regp)
 313 {
 314         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 315 }
 316
 317 /*
 318  * get_arm64_ftr_reg - Lookup a feature register entry using its
 319  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 320  * ascending order of sys_id , we use binary search to find a matching
 321  * entry.
 322  *
 323  * returns - Upon success,  matching ftr_reg entry for id.
 324  *         - NULL on failure. It is upto the caller to decide
 325  *           the impact of a failure.
 326  */
 327 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 328 {
 329         return bsearch((const void *)(unsigned long)sys_id,
 330                         arm64_ftr_regs,
 331                         ARRAY_SIZE(arm64_ftr_regs),
 332                         sizeof(arm64_ftr_regs[0]),
 333                         search_cmp_ftr_reg);
 334 }
 335
 336 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 337 {
 338         u64 mask = arm64_ftr_mask(ftrp);
 339
 340         reg &= ~mask;
 341         reg |= (ftr_val << ftrp->shift) & mask;
 342         return reg;
 343 }
 344
 345 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 346 {
 347         s64 ret = 0;
 348
 349         switch (ftrp->type) {
 350         case FTR_EXACT:
 351                 ret = ftrp->safe_val;
 352                 break;
 353         case FTR_LOWER_SAFE:
 354                 ret = new < cur ? new : cur;
 355                 break;
 356         case FTR_HIGHER_SAFE:
 357                 ret = new > cur ? new : cur;
 358                 break;
 359         default:
 360                 BUG();
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 367 {
 368         return ((const struct arm64_ftr_reg *)a)->sys_id -
 369                  ((const struct arm64_ftr_reg *)b)->sys_id;
 370 }
 371
 372 static void __init swap_ftr_regs(void *a, void *b, int size)
 373 {
 374         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 375         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 376         *(struct arm64_ftr_reg *)b = tmp;
 377 }
 378
 379 static void __init sort_ftr_regs(void)
 380 {
 381         /* Keep the array sorted so that we can do the binary search */
 382         sort(arm64_ftr_regs,
 383                 ARRAY_SIZE(arm64_ftr_regs),
 384                 sizeof(arm64_ftr_regs[0]),
 385                 sort_cmp_ftr_regs,
 386                 swap_ftr_regs);
 387 }
 388
 389 /*
 390  * Initialise the CPU feature register from Boot CPU values.
 391  * Also initiliases the strict_mask for the register.
 392  */
 393 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 394 {
 395         u64 val = 0;
 396         u64 strict_mask = ~0x0ULL;
 397         struct arm64_ftr_bits *ftrp;
 398         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 399
 400         BUG_ON(!reg);
 401
 402         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 403                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 404
 405                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 406                 if (!ftrp->strict)
 407                         strict_mask &= ~arm64_ftr_mask(ftrp);
 408         }
 409         reg->sys_val = val;
 410         reg->strict_mask = strict_mask;
 411 }
 412
 413 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 414 {
 415         /* Before we start using the tables, make sure it is sorted */
 416         sort_ftr_regs();
 417
 418         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 419         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 420         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 421         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 422         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 423         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 424         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 425         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 426         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 427         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 428         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 429         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 430         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 431         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 432         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 433         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 434         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 435         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 436         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 437         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 438         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 439         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 440         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 441         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 442         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 443         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 444         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 445         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 446 }
 447
 448 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 449 {
 450         struct arm64_ftr_bits *ftrp;
 451
 452         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 453                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 454                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 455
 456                 if (ftr_cur == ftr_new)
 457                         continue;
 458                 /* Find a safe value */
 459                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 460                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 461         }
 462
 463 }
 464
 465 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 466 {
 467         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 468
 469         BUG_ON(!regp);
 470         update_cpu_ftr_reg(regp, val);
 471         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 472                 return 0;
 473         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 474                         regp->name, boot, cpu, val);
 475         return 1;
 476 }
 477
 478 /*
 479  * Update system wide CPU feature registers with the values from a
 480  * non-boot CPU. Also performs SANITY checks to make sure that there
 481  * aren't any insane variations from that of the boot CPU.
 482  */
 483 void update_cpu_features(int cpu,
 484                          struct cpuinfo_arm64 *info,
 485                          struct cpuinfo_arm64 *boot)
 486 {
 487         int taint = 0;
 488
 489         /*
 490          * The kernel can handle differing I-cache policies, but otherwise
 491          * caches should look identical. Userspace JITs will make use of
 492          * *minLine.
 493          */
 494         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 495                                       info->reg_ctr, boot->reg_ctr);
 496
 497         /*
 498          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 499          * could result in too much or too little memory being zeroed if a
 500          * process is preempted and migrated between CPUs.
 501          */
 502         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 503                                       info->reg_dczid, boot->reg_dczid);
 504
 505         /* If different, timekeeping will be broken (especially with KVM) */
 506         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 507                                       info->reg_cntfrq, boot->reg_cntfrq);
 508
 509         /*
 510          * The kernel uses self-hosted debug features and expects CPUs to
 511          * support identical debug features. We presently need CTX_CMPs, WRPs,
 512          * and BRPs to be identical.
 513          * ID_AA64DFR1 is currently RES0.
 514          */
 515         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 516                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 517         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 518                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 519         /*
 520          * Even in big.LITTLE, processors should be identical instruction-set
 521          * wise.
 522          */
 523         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 524                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 525         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 526                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 527
 528         /*
 529          * Differing PARange support is fine as long as all peripherals and
 530          * memory are mapped within the minimum PARange of all CPUs.
 531          * Linux should not care about secure memory.
 532          */
 533         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 534                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 535         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 536                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 537         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 538                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 539
 540         /*
 541          * EL3 is not our concern.
 542          * ID_AA64PFR1 is currently RES0.
 543          */
 544         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 545                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 546         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 547                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 548
 549         /*
 550          * If we have AArch32, we care about 32-bit features for compat. These
 551          * registers should be RES0 otherwise.
 552          */
 553         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 554                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 555         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 556                                         info->reg_id_isar0, boot->reg_id_isar0);
 557         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 558                                         info->reg_id_isar1, boot->reg_id_isar1);
 559         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 560                                         info->reg_id_isar2, boot->reg_id_isar2);
 561         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 562                                         info->reg_id_isar3, boot->reg_id_isar3);
 563         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 564                                         info->reg_id_isar4, boot->reg_id_isar4);
 565         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 566                                         info->reg_id_isar5, boot->reg_id_isar5);
 567
 568         /*
 569          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 570          * ACTLR formats could differ across CPUs and therefore would have to
 571          * be trapped for virtualization anyway.
 572          */
 573         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 574                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 575         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 576                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 577         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 578                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 579         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 580                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 581         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 582                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 583         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 584                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 585         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 586                                         info->reg_mvfr0, boot->reg_mvfr0);
 587         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 588                                         info->reg_mvfr1, boot->reg_mvfr1);
 589         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 590                                         info->reg_mvfr2, boot->reg_mvfr2);
 591
 592         /*
 593          * Mismatched CPU features are a recipe for disaster. Don't even
 594          * pretend to support them.
 595          */
 596         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 597                         "Unsupported CPU feature variation.\n");
 598 }
 599
 600 u64 read_system_reg(u32 id)
 601 {
 602         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 603
 604         /* We shouldn't get a request for an unsupported register */
 605         BUG_ON(!regp);
 606         return regp->sys_val;
 607 }
 608
 609 #include <linux/irqchip/arm-gic-v3.h>
 610
 611 static bool
 612 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 613 {
 614         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 615
 616         return val >= entry->min_field_value;
 617 }
 618
 619 static bool
 620 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 621 {
 622         u64 val;
 623
 624         val = read_system_reg(entry->sys_reg);
 625         return feature_matches(val, entry);
 626 }
 627
 628 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 629 {
 630         bool has_sre;
 631
 632         if (!has_cpuid_feature(entry))
 633                 return false;
 634
 635         has_sre = gic_enable_sre();
 636         if (!has_sre)
 637                 pr_warn_once("%s present but disabled by higher exception level\n",
 638                              entry->desc);
 639
 640         return has_sre;
 641 }
 642
 643 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 644 {
 645         u32 midr = read_cpuid_id();
 646         u32 rv_min, rv_max;
 647
 648         /* Cavium ThunderX pass 1.x and 2.x */
 649         rv_min = 0;
 650         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 651
 652         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 653 }
 654
 655 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
 656 {
 657         return is_kernel_in_hyp_mode();
 658 }
 659
 660 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 661 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 662
 663 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry)
 664 {
 665         /* Forced on command line? */
 666         if (__kpti_forced) {
 667                 pr_info_once("kernel page table isolation forced %s by command line option\n",
 668                              __kpti_forced > 0 ? "ON" : "OFF");
 669                 return __kpti_forced > 0;
 670         }
 671
 672         /* Useful for KASLR robustness */
 673         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 674                 return true;
 675
 676         return false;
 677 }
 678
 679 static int __init parse_kpti(char *str)
 680 {
 681         bool enabled;
 682         int ret = strtobool(str, &enabled);
 683
 684         if (ret)
 685                 return ret;
 686
 687         __kpti_forced = enabled ? 1 : -1;
 688         return 0;
 689 }
 690 __setup("kpti=", parse_kpti);
 691 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
 692
 693 static const struct arm64_cpu_capabilities arm64_features[] = {
 694         {
 695                 .desc = "GIC system register CPU interface",
 696                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 697                 .matches = has_useable_gicv3_cpuif,
 698                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 699                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 700                 .min_field_value = 1,
 701         },
 702 #ifdef CONFIG_ARM64_PAN
 703         {
 704                 .desc = "Privileged Access Never",
 705                 .capability = ARM64_HAS_PAN,
 706                 .matches = has_cpuid_feature,
 707                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 708                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 709                 .min_field_value = 1,
 710                 .enable = cpu_enable_pan,
 711         },
 712 #endif /* CONFIG_ARM64_PAN */
 713 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 714         {
 715                 .desc = "LSE atomic instructions",
 716                 .capability = ARM64_HAS_LSE_ATOMICS,
 717                 .matches = has_cpuid_feature,
 718                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 719                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 720                 .min_field_value = 2,
 721         },
 722 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 723         {
 724                 .desc = "Software prefetching using PRFM",
 725                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 726                 .matches = has_no_hw_prefetch,
 727         },
 728 #ifdef CONFIG_ARM64_UAO
 729         {
 730                 .desc = "User Access Override",
 731                 .capability = ARM64_HAS_UAO,
 732                 .matches = has_cpuid_feature,
 733                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 734                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 735                 .min_field_value = 1,
 736                 .enable = cpu_enable_uao,
 737         },
 738 #endif /* CONFIG_ARM64_UAO */
 739 #ifdef CONFIG_ARM64_PAN
 740         {
 741                 .capability = ARM64_ALT_PAN_NOT_UAO,
 742                 .matches = cpufeature_pan_not_uao,
 743         },
 744 #endif /* CONFIG_ARM64_PAN */
 745         {
 746                 .desc = "Virtualization Host Extensions",
 747                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 748                 .matches = runs_at_el2,
 749         },
 750 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 751         {
 752                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
 753                 .matches = unmap_kernel_at_el0,
 754         },
 755 #endif
 756         {
 757                 .desc = "32-bit EL0 Support",
 758                 .capability = ARM64_HAS_32BIT_EL0,
 759                 .matches = has_cpuid_feature,
 760                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 761                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 762                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 763         },
 764         {},
 765 };
 766
 767 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 768         {                                                       \
 769                 .desc = #cap,                                   \
 770                 .matches = has_cpuid_feature,                   \
 771                 .sys_reg = reg,                                 \
 772                 .field_pos = field,                             \
 773                 .min_field_value = min_value,                   \
 774                 .hwcap_type = type,                             \
 775                 .hwcap = cap,                                   \
 776         }
 777
 778 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 779         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 780         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 781         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 782         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 783         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 784         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 785         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 786         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 787 #ifdef CONFIG_COMPAT
 788         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 789         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 790         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 791         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 792         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 793 #endif
 794         {},
 795 };
 796
 797 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 798 {
 799         switch (cap->hwcap_type) {
 800         case CAP_HWCAP:
 801                 elf_hwcap |= cap->hwcap;
 802                 break;
 803 #ifdef CONFIG_COMPAT
 804         case CAP_COMPAT_HWCAP:
 805                 compat_elf_hwcap |= (u32)cap->hwcap;
 806                 break;
 807         case CAP_COMPAT_HWCAP2:
 808                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 809                 break;
 810 #endif
 811         default:
 812                 WARN_ON(1);
 813                 break;
 814         }
 815 }
 816
 817 /* Check if we have a particular HWCAP enabled */
 818 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 819 {
 820         bool rc;
 821
 822         switch (cap->hwcap_type) {
 823         case CAP_HWCAP:
 824                 rc = (elf_hwcap & cap->hwcap) != 0;
 825                 break;
 826 #ifdef CONFIG_COMPAT
 827         case CAP_COMPAT_HWCAP:
 828                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 829                 break;
 830         case CAP_COMPAT_HWCAP2:
 831                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 832                 break;
 833 #endif
 834         default:
 835                 WARN_ON(1);
 836                 rc = false;
 837         }
 838
 839         return rc;
 840 }
 841
 842 static void __init setup_cpu_hwcaps(void)
 843 {
 844         int i;
 845         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 846
 847         for (i = 0; hwcaps[i].matches; i++)
 848                 if (hwcaps[i].matches(&hwcaps[i]))
 849                         cap_set_hwcap(&hwcaps[i]);
 850 }
 851
 852 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 853                             const char *info)
 854 {
 855         int i;
 856
 857         for (i = 0; caps[i].matches; i++) {
 858                 if (!caps[i].matches(&caps[i]))
 859                         continue;
 860
 861                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 862                         pr_info("%s %s\n", info, caps[i].desc);
 863                 cpus_set_cap(caps[i].capability);
 864         }
 865 }
 866
 867 /*
 868  * Run through the enabled capabilities and enable() it on all active
 869  * CPUs
 870  */
 871 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 872 {
 873         int i;
 874
 875         for (i = 0; caps[i].matches; i++)
 876                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 877                         /*
 878                          * Use stop_machine() as it schedules the work allowing
 879                          * us to modify PSTATE, instead of on_each_cpu() which
 880                          * uses an IPI, giving us a PSTATE that disappears when
 881                          * we return.
 882                          */
 883                         stop_machine(caps[i].enable, (void *)&caps[i],
 884                                                         cpu_online_mask);
 885 }
 886
 887 #ifdef CONFIG_HOTPLUG_CPU
 888
 889 /*
 890  * Flag to indicate if we have computed the system wide
 891  * capabilities based on the boot time active CPUs. This
 892  * will be used to determine if a new booting CPU should
 893  * go through the verification process to make sure that it
 894  * supports the system capabilities, without using a hotplug
 895  * notifier.
 896  */
 897 static bool sys_caps_initialised;
 898
 899 static inline void set_sys_caps_initialised(void)
 900 {
 901         sys_caps_initialised = true;
 902 }
 903
 904 /*
 905  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 906  */
 907 static u64 __raw_read_system_reg(u32 sys_id)
 908 {
 909         switch (sys_id) {
 910         case SYS_ID_PFR0_EL1:           return read_cpuid(SYS_ID_PFR0_EL1);
 911         case SYS_ID_PFR1_EL1:           return read_cpuid(SYS_ID_PFR1_EL1);
 912         case SYS_ID_DFR0_EL1:           return read_cpuid(SYS_ID_DFR0_EL1);
 913         case SYS_ID_MMFR0_EL1:          return read_cpuid(SYS_ID_MMFR0_EL1);
 914         case SYS_ID_MMFR1_EL1:          return read_cpuid(SYS_ID_MMFR1_EL1);
 915         case SYS_ID_MMFR2_EL1:          return read_cpuid(SYS_ID_MMFR2_EL1);
 916         case SYS_ID_MMFR3_EL1:          return read_cpuid(SYS_ID_MMFR3_EL1);
 917         case SYS_ID_ISAR0_EL1:          return read_cpuid(SYS_ID_ISAR0_EL1);
 918         case SYS_ID_ISAR1_EL1:          return read_cpuid(SYS_ID_ISAR1_EL1);
 919         case SYS_ID_ISAR2_EL1:          return read_cpuid(SYS_ID_ISAR2_EL1);
 920         case SYS_ID_ISAR3_EL1:          return read_cpuid(SYS_ID_ISAR3_EL1);
 921         case SYS_ID_ISAR4_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 922         case SYS_ID_ISAR5_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 923         case SYS_MVFR0_EL1:             return read_cpuid(SYS_MVFR0_EL1);
 924         case SYS_MVFR1_EL1:             return read_cpuid(SYS_MVFR1_EL1);
 925         case SYS_MVFR2_EL1:             return read_cpuid(SYS_MVFR2_EL1);
 926
 927         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 928         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 929         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 930         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 931         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(SYS_ID_AA64MMFR0_EL1);
 932         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(SYS_ID_AA64MMFR1_EL1);
 933         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(SYS_ID_AA64MMFR2_EL1);
 934         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(SYS_ID_AA64ISAR0_EL1);
 935         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(SYS_ID_AA64ISAR1_EL1);
 936
 937         case SYS_CNTFRQ_EL0:            return read_cpuid(SYS_CNTFRQ_EL0);
 938         case SYS_CTR_EL0:               return read_cpuid(SYS_CTR_EL0);
 939         case SYS_DCZID_EL0:             return read_cpuid(SYS_DCZID_EL0);
 940         default:
 941                 BUG();
 942                 return 0;
 943         }
 944 }
 945
 946 /*
 947  * Park the CPU which doesn't have the capability as advertised
 948  * by the system.
 949  */
 950 static void fail_incapable_cpu(char *cap_type,
 951                                  const struct arm64_cpu_capabilities *cap)
 952 {
 953         int cpu = smp_processor_id();
 954
 955         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 956         /* Mark this CPU absent */
 957         set_cpu_present(cpu, 0);
 958
 959         /* Check if we can park ourselves */
 960         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 961                 cpu_ops[cpu]->cpu_die(cpu);
 962         asm(
 963         "1:     wfe\n"
 964         "       wfi\n"
 965         "       b       1b");
 966 }
 967
 968 /*
 969  * Run through the enabled system capabilities and enable() it on this CPU.
 970  * The capabilities were decided based on the available CPUs at the boot time.
 971  * Any new CPU should match the system wide status of the capability. If the
 972  * new CPU doesn't have a capability which the system now has enabled, we
 973  * cannot do anything to fix it up and could cause unexpected failures. So
 974  * we park the CPU.
 975  */
 976 void verify_local_cpu_capabilities(void)
 977 {
 978         int i;
 979         const struct arm64_cpu_capabilities *caps;
 980
 981         /*
 982          * If we haven't computed the system capabilities, there is nothing
 983          * to verify.
 984          */
 985         if (!sys_caps_initialised)
 986                 return;
 987
 988         caps = arm64_features;
 989         for (i = 0; caps[i].matches; i++) {
 990                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 991                         continue;
 992                 /*
 993                  * If the new CPU misses an advertised feature, we cannot proceed
 994                  * further, park the cpu.
 995                  */
 996                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
 997                         fail_incapable_cpu("arm64_features", &caps[i]);
 998                 if (caps[i].enable)
 999                         caps[i].enable((void *)&caps[i]);
1000         }
1001
1002         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
1003                 if (!cpus_have_hwcap(&caps[i]))
1004                         continue;
1005                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
1006                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
1007         }
1008 }
1009
1010 #else   /* !CONFIG_HOTPLUG_CPU */
1011
1012 static inline void set_sys_caps_initialised(void)
1013 {
1014 }
1015
1016 #endif  /* CONFIG_HOTPLUG_CPU */
1017
1018 static void __init setup_feature_capabilities(void)
1019 {
1020         update_cpu_capabilities(arm64_features, "detected feature:");
1021         enable_cpu_capabilities(arm64_features);
1022 }
1023
1024 void __init setup_cpu_features(void)
1025 {
1026         u32 cwg;
1027         int cls;
1028
1029         /* Set the CPU feature capabilies */
1030         setup_feature_capabilities();
1031         enable_errata_workarounds();
1032         setup_cpu_hwcaps();
1033
1034         /* Advertise that we have computed the system capabilities */
1035         set_sys_caps_initialised();
1036
1037         /*
1038          * Check for sane CTR_EL0.CWG value.
1039          */
1040         cwg = cache_type_cwg();
1041         cls = cache_line_size();
1042         if (!cwg)
1043                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1044                         cls);
1045         if (ARCH_DMA_MINALIGN < cls)
1046                 pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
1047                         ARCH_DMA_MINALIGN, cls);
1048 }
1049
1050 static bool __maybe_unused
1051 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1052 {
1053         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1054 }