arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/processor.h>
  31 #include <asm/sysreg.h>
  32 #include <asm/virt.h>
  33
  34 unsigned long elf_hwcap __read_mostly;
  35 EXPORT_SYMBOL_GPL(elf_hwcap);
  36
  37 #ifdef CONFIG_COMPAT
  38 #define COMPAT_ELF_HWCAP_DEFAULT        \
  39                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  40                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  41                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  42                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  43                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  44                                  COMPAT_HWCAP_LPAE)
  45 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  46 unsigned int compat_elf_hwcap2 __read_mostly;
  47 #endif
  48
  49 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  50 EXPORT_SYMBOL(cpu_hwcaps);
  51
  52 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  53         {                                               \
  54                 .sign = SIGNED,                         \
  55                 .strict = STRICT,                       \
  56                 .type = TYPE,                           \
  57                 .shift = SHIFT,                         \
  58                 .width = WIDTH,                         \
  59                 .safe_val = SAFE_VAL,                   \
  60         }
  61
  62 /* Define a feature with signed values */
  63 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  65
  66 /* Define a feature with unsigned value */
  67 #define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  68         __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  69
  70 #define ARM64_FTR_END                                   \
  71         {                                               \
  72                 .width = 0,                             \
  73         }
  74
  75 /* meta feature for alternatives */
  76 static bool __maybe_unused
  77 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
  78
  79 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  87         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  88         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  89         ARM64_FTR_END,
  90 };
  91
  92 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  95         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
  96         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  97         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  99         /* Linux doesn't care about the EL3 */
 100         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 101         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 102         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 103         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 104         ARM64_FTR_END,
 105 };
 106
 107 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 109         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 110         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 111         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 112         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 113         /* Linux shouldn't care about secure memory */
 114         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 115         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 116         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 117         /*
 118          * Differing PARange is fine as long as all peripherals and memory are mapped
 119          * within the minimum PARange of all CPUs
 120          */
 121         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 122         ARM64_FTR_END,
 123 };
 124
 125 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 133         ARM64_FTR_END,
 134 };
 135
 136 static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 137         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 138         ARM64_FTR_END,
 139 };
 140
 141 static struct arm64_ftr_bits ftr_ctr[] = {
 142         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),      /* RES1 */
 143         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
 144         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
 145         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
 146         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0),        /* CWG */
 147         U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0),        /* ERG */
 148         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
 149         /*
 150          * Linux can handle differing I-cache policies. Userspace JITs will
 151          * make use of *minLine
 152          */
 153         U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),   /* L1Ip */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 155         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),  /* IminLine */
 156         ARM64_FTR_END,
 157 };
 158
 159 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 160         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 161         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 162         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 163         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 164         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 166         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 167         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 168         ARM64_FTR_END,
 169 };
 170
 171 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 172         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 173         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 174         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 175         U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 176         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 177         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 178         U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 179         ARM64_FTR_END,
 180 };
 181
 182 static struct arm64_ftr_bits ftr_mvfr2[] = {
 183         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 184         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 185         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 186         ARM64_FTR_END,
 187 };
 188
 189 static struct arm64_ftr_bits ftr_dczid[] = {
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 193         ARM64_FTR_END,
 194 };
 195
 196
 197 static struct arm64_ftr_bits ftr_id_isar5[] = {
 198         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 199         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 200         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 201         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 202         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 203         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 205         ARM64_FTR_END,
 206 };
 207
 208 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 211         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 212         ARM64_FTR_END,
 213 };
 214
 215 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 216         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 217         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 218         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 219         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 220         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 221         ARM64_FTR_END,
 222 };
 223
 224 /*
 225  * Common ftr bits for a 32bit register with all hidden, strict
 226  * attributes, with 4bit feature fields and a default safe value of
 227  * 0. Covers the following 32bit registers:
 228  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 229  */
 230 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 231         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 232         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 233         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 234         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 235         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 236         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 237         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 238         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 239         ARM64_FTR_END,
 240 };
 241
 242 static struct arm64_ftr_bits ftr_generic[] = {
 243         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 244         ARM64_FTR_END,
 245 };
 246
 247 static struct arm64_ftr_bits ftr_generic32[] = {
 248         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 249         ARM64_FTR_END,
 250 };
 251
 252 static struct arm64_ftr_bits ftr_aa64raz[] = {
 253         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 254         ARM64_FTR_END,
 255 };
 256
 257 #define ARM64_FTR_REG(id, table)                \
 258         {                                       \
 259                 .sys_id = id,                   \
 260                 .name = #id,                    \
 261                 .ftr_bits = &((table)[0]),      \
 262         }
 263
 264 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 265
 266         /* Op1 = 0, CRn = 0, CRm = 1 */
 267         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 268         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 269         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 270         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 271         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 272         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 273         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 274
 275         /* Op1 = 0, CRn = 0, CRm = 2 */
 276         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 277         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 278         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 279         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 280         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 281         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 282         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 283
 284         /* Op1 = 0, CRn = 0, CRm = 3 */
 285         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 286         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 287         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 288
 289         /* Op1 = 0, CRn = 0, CRm = 4 */
 290         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 291         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 292
 293         /* Op1 = 0, CRn = 0, CRm = 5 */
 294         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 295         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 296
 297         /* Op1 = 0, CRn = 0, CRm = 6 */
 298         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 299         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 300
 301         /* Op1 = 0, CRn = 0, CRm = 7 */
 302         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 303         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 304         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 305
 306         /* Op1 = 3, CRn = 0, CRm = 0 */
 307         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 308         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 309
 310         /* Op1 = 3, CRn = 14, CRm = 0 */
 311         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 312 };
 313
 314 static int search_cmp_ftr_reg(const void *id, const void *regp)
 315 {
 316         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 317 }
 318
 319 /*
 320  * get_arm64_ftr_reg - Lookup a feature register entry using its
 321  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 322  * ascending order of sys_id , we use binary search to find a matching
 323  * entry.
 324  *
 325  * returns - Upon success,  matching ftr_reg entry for id.
 326  *         - NULL on failure. It is upto the caller to decide
 327  *           the impact of a failure.
 328  */
 329 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 330 {
 331         return bsearch((const void *)(unsigned long)sys_id,
 332                         arm64_ftr_regs,
 333                         ARRAY_SIZE(arm64_ftr_regs),
 334                         sizeof(arm64_ftr_regs[0]),
 335                         search_cmp_ftr_reg);
 336 }
 337
 338 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 339 {
 340         u64 mask = arm64_ftr_mask(ftrp);
 341
 342         reg &= ~mask;
 343         reg |= (ftr_val << ftrp->shift) & mask;
 344         return reg;
 345 }
 346
 347 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 348 {
 349         s64 ret = 0;
 350
 351         switch (ftrp->type) {
 352         case FTR_EXACT:
 353                 ret = ftrp->safe_val;
 354                 break;
 355         case FTR_LOWER_SAFE:
 356                 ret = new < cur ? new : cur;
 357                 break;
 358         case FTR_HIGHER_OR_ZERO_SAFE:
 359                 if (!cur || !new)
 360                         break;
 361                 /* Fallthrough */
 362         case FTR_HIGHER_SAFE:
 363                 ret = new > cur ? new : cur;
 364                 break;
 365         default:
 366                 BUG();
 367         }
 368
 369         return ret;
 370 }
 371
 372 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 373 {
 374         return ((const struct arm64_ftr_reg *)a)->sys_id -
 375                  ((const struct arm64_ftr_reg *)b)->sys_id;
 376 }
 377
 378 static void __init swap_ftr_regs(void *a, void *b, int size)
 379 {
 380         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 381         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 382         *(struct arm64_ftr_reg *)b = tmp;
 383 }
 384
 385 static void __init sort_ftr_regs(void)
 386 {
 387         /* Keep the array sorted so that we can do the binary search */
 388         sort(arm64_ftr_regs,
 389                 ARRAY_SIZE(arm64_ftr_regs),
 390                 sizeof(arm64_ftr_regs[0]),
 391                 sort_cmp_ftr_regs,
 392                 swap_ftr_regs);
 393 }
 394
 395 /*
 396  * Initialise the CPU feature register from Boot CPU values.
 397  * Also initiliases the strict_mask for the register.
 398  */
 399 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 400 {
 401         u64 val = 0;
 402         u64 strict_mask = ~0x0ULL;
 403         struct arm64_ftr_bits *ftrp;
 404         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 405
 406         BUG_ON(!reg);
 407
 408         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 409                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 410
 411                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 412                 if (!ftrp->strict)
 413                         strict_mask &= ~arm64_ftr_mask(ftrp);
 414         }
 415         reg->sys_val = val;
 416         reg->strict_mask = strict_mask;
 417 }
 418
 419 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 420 {
 421         /* Before we start using the tables, make sure it is sorted */
 422         sort_ftr_regs();
 423
 424         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 425         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 426         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 427         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 428         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 429         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 430         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 431         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 432         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 433         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 434         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 435         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 436         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 437         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 438         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 439         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 440         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 441         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 442         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 443         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 444         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 445         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 446         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 447         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 448         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 449         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 450         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 451         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 452 }
 453
 454 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 455 {
 456         struct arm64_ftr_bits *ftrp;
 457
 458         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 459                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 460                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 461
 462                 if (ftr_cur == ftr_new)
 463                         continue;
 464                 /* Find a safe value */
 465                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 466                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 467         }
 468
 469 }
 470
 471 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 472 {
 473         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 474
 475         BUG_ON(!regp);
 476         update_cpu_ftr_reg(regp, val);
 477         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 478                 return 0;
 479         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 480                         regp->name, boot, cpu, val);
 481         return 1;
 482 }
 483
 484 /*
 485  * Update system wide CPU feature registers with the values from a
 486  * non-boot CPU. Also performs SANITY checks to make sure that there
 487  * aren't any insane variations from that of the boot CPU.
 488  */
 489 void update_cpu_features(int cpu,
 490                          struct cpuinfo_arm64 *info,
 491                          struct cpuinfo_arm64 *boot)
 492 {
 493         int taint = 0;
 494
 495         /*
 496          * The kernel can handle differing I-cache policies, but otherwise
 497          * caches should look identical. Userspace JITs will make use of
 498          * *minLine.
 499          */
 500         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 501                                       info->reg_ctr, boot->reg_ctr);
 502
 503         /*
 504          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 505          * could result in too much or too little memory being zeroed if a
 506          * process is preempted and migrated between CPUs.
 507          */
 508         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 509                                       info->reg_dczid, boot->reg_dczid);
 510
 511         /* If different, timekeeping will be broken (especially with KVM) */
 512         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 513                                       info->reg_cntfrq, boot->reg_cntfrq);
 514
 515         /*
 516          * The kernel uses self-hosted debug features and expects CPUs to
 517          * support identical debug features. We presently need CTX_CMPs, WRPs,
 518          * and BRPs to be identical.
 519          * ID_AA64DFR1 is currently RES0.
 520          */
 521         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 522                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 523         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 524                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 525         /*
 526          * Even in big.LITTLE, processors should be identical instruction-set
 527          * wise.
 528          */
 529         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 530                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 531         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 532                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 533
 534         /*
 535          * Differing PARange support is fine as long as all peripherals and
 536          * memory are mapped within the minimum PARange of all CPUs.
 537          * Linux should not care about secure memory.
 538          */
 539         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 540                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 541         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 542                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 543         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 544                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 545
 546         /*
 547          * EL3 is not our concern.
 548          * ID_AA64PFR1 is currently RES0.
 549          */
 550         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 551                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 552         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 553                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 554
 555         /*
 556          * If we have AArch32, we care about 32-bit features for compat. These
 557          * registers should be RES0 otherwise.
 558          */
 559         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 560                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 561         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 562                                         info->reg_id_isar0, boot->reg_id_isar0);
 563         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 564                                         info->reg_id_isar1, boot->reg_id_isar1);
 565         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 566                                         info->reg_id_isar2, boot->reg_id_isar2);
 567         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 568                                         info->reg_id_isar3, boot->reg_id_isar3);
 569         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 570                                         info->reg_id_isar4, boot->reg_id_isar4);
 571         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 572                                         info->reg_id_isar5, boot->reg_id_isar5);
 573
 574         /*
 575          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 576          * ACTLR formats could differ across CPUs and therefore would have to
 577          * be trapped for virtualization anyway.
 578          */
 579         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 580                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 581         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 582                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 583         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 584                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 585         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 586                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 587         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 588                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 589         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 590                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 591         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 592                                         info->reg_mvfr0, boot->reg_mvfr0);
 593         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 594                                         info->reg_mvfr1, boot->reg_mvfr1);
 595         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 596                                         info->reg_mvfr2, boot->reg_mvfr2);
 597
 598         /*
 599          * Mismatched CPU features are a recipe for disaster. Don't even
 600          * pretend to support them.
 601          */
 602         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 603                         "Unsupported CPU feature variation.\n");
 604 }
 605
 606 u64 read_system_reg(u32 id)
 607 {
 608         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 609
 610         /* We shouldn't get a request for an unsupported register */
 611         BUG_ON(!regp);
 612         return regp->sys_val;
 613 }
 614
 615 #include <linux/irqchip/arm-gic-v3.h>
 616
 617 static bool
 618 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 619 {
 620         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 621
 622         return val >= entry->min_field_value;
 623 }
 624
 625 static bool
 626 has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
 627 {
 628         u64 val;
 629
 630         val = read_system_reg(entry->sys_reg);
 631         return feature_matches(val, entry);
 632 }
 633
 634 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
 635 {
 636         bool has_sre;
 637
 638         if (!has_cpuid_feature(entry))
 639                 return false;
 640
 641         has_sre = gic_enable_sre();
 642         if (!has_sre)
 643                 pr_warn_once("%s present but disabled by higher exception level\n",
 644                              entry->desc);
 645
 646         return has_sre;
 647 }
 648
 649 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
 650 {
 651         u32 midr = read_cpuid_id();
 652         u32 rv_min, rv_max;
 653
 654         /* Cavium ThunderX pass 1.x and 2.x */
 655         rv_min = 0;
 656         rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
 657
 658         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
 659 }
 660
 661 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
 662 {
 663         return is_kernel_in_hyp_mode();
 664 }
 665
 666 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 667 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 668
 669 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry)
 670 {
 671         /* Forced on command line? */
 672         if (__kpti_forced) {
 673                 pr_info_once("kernel page table isolation forced %s by command line option\n",
 674                              __kpti_forced > 0 ? "ON" : "OFF");
 675                 return __kpti_forced > 0;
 676         }
 677
 678         /* Useful for KASLR robustness */
 679         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 680                 return true;
 681
 682         return false;
 683 }
 684
 685 static int __init parse_kpti(char *str)
 686 {
 687         bool enabled;
 688         int ret = strtobool(str, &enabled);
 689
 690         if (ret)
 691                 return ret;
 692
 693         __kpti_forced = enabled ? 1 : -1;
 694         return 0;
 695 }
 696 __setup("kpti=", parse_kpti);
 697 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
 698
 699 static const struct arm64_cpu_capabilities arm64_features[] = {
 700         {
 701                 .desc = "GIC system register CPU interface",
 702                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 703                 .matches = has_useable_gicv3_cpuif,
 704                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 705                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 706                 .min_field_value = 1,
 707         },
 708 #ifdef CONFIG_ARM64_PAN
 709         {
 710                 .desc = "Privileged Access Never",
 711                 .capability = ARM64_HAS_PAN,
 712                 .matches = has_cpuid_feature,
 713                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 714                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 715                 .min_field_value = 1,
 716                 .enable = cpu_enable_pan,
 717         },
 718 #endif /* CONFIG_ARM64_PAN */
 719 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 720         {
 721                 .desc = "LSE atomic instructions",
 722                 .capability = ARM64_HAS_LSE_ATOMICS,
 723                 .matches = has_cpuid_feature,
 724                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 725                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 726                 .min_field_value = 2,
 727         },
 728 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 729         {
 730                 .desc = "Software prefetching using PRFM",
 731                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 732                 .matches = has_no_hw_prefetch,
 733         },
 734 #ifdef CONFIG_ARM64_UAO
 735         {
 736                 .desc = "User Access Override",
 737                 .capability = ARM64_HAS_UAO,
 738                 .matches = has_cpuid_feature,
 739                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 740                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 741                 .min_field_value = 1,
 742                 .enable = cpu_enable_uao,
 743         },
 744 #endif /* CONFIG_ARM64_UAO */
 745 #ifdef CONFIG_ARM64_PAN
 746         {
 747                 .capability = ARM64_ALT_PAN_NOT_UAO,
 748                 .matches = cpufeature_pan_not_uao,
 749         },
 750 #endif /* CONFIG_ARM64_PAN */
 751         {
 752                 .desc = "Virtualization Host Extensions",
 753                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 754                 .matches = runs_at_el2,
 755         },
 756 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 757         {
 758                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
 759                 .matches = unmap_kernel_at_el0,
 760         },
 761 #endif
 762         {
 763                 .desc = "32-bit EL0 Support",
 764                 .capability = ARM64_HAS_32BIT_EL0,
 765                 .matches = has_cpuid_feature,
 766                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 767                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 768                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 769         },
 770         {},
 771 };
 772
 773 #define HWCAP_CAP(reg, field, min_value, type, cap)             \
 774         {                                                       \
 775                 .desc = #cap,                                   \
 776                 .matches = has_cpuid_feature,                   \
 777                 .sys_reg = reg,                                 \
 778                 .field_pos = field,                             \
 779                 .min_field_value = min_value,                   \
 780                 .hwcap_type = type,                             \
 781                 .hwcap = cap,                                   \
 782         }
 783
 784 static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
 785         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
 786         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
 787         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
 788         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
 789         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
 790         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
 791         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
 792         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
 793 #ifdef CONFIG_COMPAT
 794         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 795         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 796         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 797         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 798         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 799 #endif
 800         {},
 801 };
 802
 803 static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
 804 {
 805         switch (cap->hwcap_type) {
 806         case CAP_HWCAP:
 807                 elf_hwcap |= cap->hwcap;
 808                 break;
 809 #ifdef CONFIG_COMPAT
 810         case CAP_COMPAT_HWCAP:
 811                 compat_elf_hwcap |= (u32)cap->hwcap;
 812                 break;
 813         case CAP_COMPAT_HWCAP2:
 814                 compat_elf_hwcap2 |= (u32)cap->hwcap;
 815                 break;
 816 #endif
 817         default:
 818                 WARN_ON(1);
 819                 break;
 820         }
 821 }
 822
 823 /* Check if we have a particular HWCAP enabled */
 824 static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
 825 {
 826         bool rc;
 827
 828         switch (cap->hwcap_type) {
 829         case CAP_HWCAP:
 830                 rc = (elf_hwcap & cap->hwcap) != 0;
 831                 break;
 832 #ifdef CONFIG_COMPAT
 833         case CAP_COMPAT_HWCAP:
 834                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
 835                 break;
 836         case CAP_COMPAT_HWCAP2:
 837                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
 838                 break;
 839 #endif
 840         default:
 841                 WARN_ON(1);
 842                 rc = false;
 843         }
 844
 845         return rc;
 846 }
 847
 848 static void __init setup_cpu_hwcaps(void)
 849 {
 850         int i;
 851         const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
 852
 853         for (i = 0; hwcaps[i].matches; i++)
 854                 if (hwcaps[i].matches(&hwcaps[i]))
 855                         cap_set_hwcap(&hwcaps[i]);
 856 }
 857
 858 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 859                             const char *info)
 860 {
 861         int i;
 862
 863         for (i = 0; caps[i].matches; i++) {
 864                 if (!caps[i].matches(&caps[i]))
 865                         continue;
 866
 867                 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
 868                         pr_info("%s %s\n", info, caps[i].desc);
 869                 cpus_set_cap(caps[i].capability);
 870         }
 871 }
 872
 873 /*
 874  * Run through the enabled capabilities and enable() it on all active
 875  * CPUs
 876  */
 877 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 878 {
 879         int i;
 880
 881         for (i = 0; caps[i].matches; i++)
 882                 if (caps[i].enable && cpus_have_cap(caps[i].capability))
 883                         /*
 884                          * Use stop_machine() as it schedules the work allowing
 885                          * us to modify PSTATE, instead of on_each_cpu() which
 886                          * uses an IPI, giving us a PSTATE that disappears when
 887                          * we return.
 888                          */
 889                         stop_machine(caps[i].enable, (void *)&caps[i],
 890                                                         cpu_online_mask);
 891 }
 892
 893 #ifdef CONFIG_HOTPLUG_CPU
 894
 895 /*
 896  * Flag to indicate if we have computed the system wide
 897  * capabilities based on the boot time active CPUs. This
 898  * will be used to determine if a new booting CPU should
 899  * go through the verification process to make sure that it
 900  * supports the system capabilities, without using a hotplug
 901  * notifier.
 902  */
 903 static bool sys_caps_initialised;
 904
 905 static inline void set_sys_caps_initialised(void)
 906 {
 907         sys_caps_initialised = true;
 908 }
 909
 910 /*
 911  * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
 912  */
 913 static u64 __raw_read_system_reg(u32 sys_id)
 914 {
 915         switch (sys_id) {
 916         case SYS_ID_PFR0_EL1:           return read_cpuid(SYS_ID_PFR0_EL1);
 917         case SYS_ID_PFR1_EL1:           return read_cpuid(SYS_ID_PFR1_EL1);
 918         case SYS_ID_DFR0_EL1:           return read_cpuid(SYS_ID_DFR0_EL1);
 919         case SYS_ID_MMFR0_EL1:          return read_cpuid(SYS_ID_MMFR0_EL1);
 920         case SYS_ID_MMFR1_EL1:          return read_cpuid(SYS_ID_MMFR1_EL1);
 921         case SYS_ID_MMFR2_EL1:          return read_cpuid(SYS_ID_MMFR2_EL1);
 922         case SYS_ID_MMFR3_EL1:          return read_cpuid(SYS_ID_MMFR3_EL1);
 923         case SYS_ID_ISAR0_EL1:          return read_cpuid(SYS_ID_ISAR0_EL1);
 924         case SYS_ID_ISAR1_EL1:          return read_cpuid(SYS_ID_ISAR1_EL1);
 925         case SYS_ID_ISAR2_EL1:          return read_cpuid(SYS_ID_ISAR2_EL1);
 926         case SYS_ID_ISAR3_EL1:          return read_cpuid(SYS_ID_ISAR3_EL1);
 927         case SYS_ID_ISAR4_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 928         case SYS_ID_ISAR5_EL1:          return read_cpuid(SYS_ID_ISAR4_EL1);
 929         case SYS_MVFR0_EL1:             return read_cpuid(SYS_MVFR0_EL1);
 930         case SYS_MVFR1_EL1:             return read_cpuid(SYS_MVFR1_EL1);
 931         case SYS_MVFR2_EL1:             return read_cpuid(SYS_MVFR2_EL1);
 932
 933         case SYS_ID_AA64PFR0_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 934         case SYS_ID_AA64PFR1_EL1:       return read_cpuid(SYS_ID_AA64PFR0_EL1);
 935         case SYS_ID_AA64DFR0_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 936         case SYS_ID_AA64DFR1_EL1:       return read_cpuid(SYS_ID_AA64DFR0_EL1);
 937         case SYS_ID_AA64MMFR0_EL1:      return read_cpuid(SYS_ID_AA64MMFR0_EL1);
 938         case SYS_ID_AA64MMFR1_EL1:      return read_cpuid(SYS_ID_AA64MMFR1_EL1);
 939         case SYS_ID_AA64MMFR2_EL1:      return read_cpuid(SYS_ID_AA64MMFR2_EL1);
 940         case SYS_ID_AA64ISAR0_EL1:      return read_cpuid(SYS_ID_AA64ISAR0_EL1);
 941         case SYS_ID_AA64ISAR1_EL1:      return read_cpuid(SYS_ID_AA64ISAR1_EL1);
 942
 943         case SYS_CNTFRQ_EL0:            return read_cpuid(SYS_CNTFRQ_EL0);
 944         case SYS_CTR_EL0:               return read_cpuid(SYS_CTR_EL0);
 945         case SYS_DCZID_EL0:             return read_cpuid(SYS_DCZID_EL0);
 946         default:
 947                 BUG();
 948                 return 0;
 949         }
 950 }
 951
 952 /*
 953  * Park the CPU which doesn't have the capability as advertised
 954  * by the system.
 955  */
 956 static void fail_incapable_cpu(char *cap_type,
 957                                  const struct arm64_cpu_capabilities *cap)
 958 {
 959         int cpu = smp_processor_id();
 960
 961         pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc);
 962         /* Mark this CPU absent */
 963         set_cpu_present(cpu, 0);
 964
 965         /* Check if we can park ourselves */
 966         if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
 967                 cpu_ops[cpu]->cpu_die(cpu);
 968         asm(
 969         "1:     wfe\n"
 970         "       wfi\n"
 971         "       b       1b");
 972 }
 973
 974 /*
 975  * Run through the enabled system capabilities and enable() it on this CPU.
 976  * The capabilities were decided based on the available CPUs at the boot time.
 977  * Any new CPU should match the system wide status of the capability. If the
 978  * new CPU doesn't have a capability which the system now has enabled, we
 979  * cannot do anything to fix it up and could cause unexpected failures. So
 980  * we park the CPU.
 981  */
 982 void verify_local_cpu_capabilities(void)
 983 {
 984         int i;
 985         const struct arm64_cpu_capabilities *caps;
 986
 987         /*
 988          * If we haven't computed the system capabilities, there is nothing
 989          * to verify.
 990          */
 991         if (!sys_caps_initialised)
 992                 return;
 993
 994         caps = arm64_features;
 995         for (i = 0; caps[i].matches; i++) {
 996                 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
 997                         continue;
 998                 /*
 999                  * If the new CPU misses an advertised feature, we cannot proceed
1000                  * further, park the cpu.
1001                  */
1002                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
1003                         fail_incapable_cpu("arm64_features", &caps[i]);
1004                 if (caps[i].enable)
1005                         caps[i].enable((void *)&caps[i]);
1006         }
1007
1008         for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
1009                 if (!cpus_have_hwcap(&caps[i]))
1010                         continue;
1011                 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i]))
1012                         fail_incapable_cpu("arm64_hwcaps", &caps[i]);
1013         }
1014 }
1015
1016 #else   /* !CONFIG_HOTPLUG_CPU */
1017
1018 static inline void set_sys_caps_initialised(void)
1019 {
1020 }
1021
1022 #endif  /* CONFIG_HOTPLUG_CPU */
1023
1024 static void __init setup_feature_capabilities(void)
1025 {
1026         update_cpu_capabilities(arm64_features, "detected feature:");
1027         enable_cpu_capabilities(arm64_features);
1028 }
1029
1030 void __init setup_cpu_features(void)
1031 {
1032         u32 cwg;
1033         int cls;
1034
1035         /* Set the CPU feature capabilies */
1036         setup_feature_capabilities();
1037         enable_errata_workarounds();
1038         setup_cpu_hwcaps();
1039
1040         /* Advertise that we have computed the system capabilities */
1041         set_sys_caps_initialised();
1042
1043         /*
1044          * Check for sane CTR_EL0.CWG value.
1045          */
1046         cwg = cache_type_cwg();
1047         cls = cache_line_size();
1048         if (!cwg)
1049                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1050                         cls);
1051         if (ARCH_DMA_MINALIGN < cls)
1052                 pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
1053                         ARCH_DMA_MINALIGN, cls);
1054 }
1055
1056 static bool __maybe_unused
1057 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1058 {
1059         return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1060 }