2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/arm-smccc.h>
22 #include <linux/init.h>
23 #include <linux/linkage.h>
25 #include <asm/alternative.h>
26 #include <asm/assembler.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/cpufeature.h>
29 #include <asm/errno.h>
32 #include <asm/memory.h>
34 #include <asm/processor.h>
35 #include <asm/ptrace.h>
36 #include <asm/thread_info.h>
37 #include <asm/asm-uaccess.h>
38 #include <asm/unistd.h>
41 * Context tracking subsystem. Used to instrument transitions
42 * between user and kernel mode.
45 #ifdef CONFIG_CONTEXT_TRACKING
46 bl context_tracking_user_exit
51 #ifdef CONFIG_CONTEXT_TRACKING
52 bl context_tracking_user_enter
65 .macro kernel_ventry, el, label, regsize = 64
67 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
68 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
77 alternative_else_nop_endif
80 sub sp, sp, #S_FRAME_SIZE
81 #ifdef CONFIG_VMAP_STACK
83 * Test whether the SP has overflowed, without corrupting a GPR.
84 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
86 add sp, sp, x0 // sp' = sp + x0
87 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
88 tbnz x0, #THREAD_SHIFT, 0f
89 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
90 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
95 * Either we've just detected an overflow, or we've taken an exception
96 * while on the overflow stack. Either way, we won't return to
97 * userspace, and can clobber EL0 registers to free up GPRs.
100 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
103 /* Recover the original x0 value and stash it in tpidrro_el0 */
107 /* Switch to the overflow stack */
108 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
111 * Check whether we were already on the overflow stack. This may happen
112 * after panic() re-enables interrupts.
114 mrs x0, tpidr_el0 // sp of interrupted context
115 sub x0, sp, x0 // delta with top of overflow stack
116 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
117 b.ne __bad_stack // no? -> bad stack pointer
119 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
126 .macro tramp_alias, dst, sym
127 mov_q \dst, TRAMP_VALIAS
128 add \dst, \dst, #(\sym - .entry.tramp.text)
131 // This macro corrupts x0-x3. It is the caller's duty
132 // to save/restore them if required.
133 .macro apply_ssbd, state, tmp1, tmp2
134 #ifdef CONFIG_ARM64_SSBD
135 alternative_cb arm64_enable_wa2_handling
136 b .L__asm_ssbd_skip\@
138 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
139 cbz \tmp2, .L__asm_ssbd_skip\@
140 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
141 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
142 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
144 alternative_cb arm64_update_smccc_conduit
145 nop // Patched to SMC/HVC #0
151 .macro kernel_entry, el, regsize = 64
153 mov w0, w0 // zero upper 32 bits of x0
155 stp x0, x1, [sp, #16 * 0]
156 stp x2, x3, [sp, #16 * 1]
157 stp x4, x5, [sp, #16 * 2]
158 stp x6, x7, [sp, #16 * 3]
159 stp x8, x9, [sp, #16 * 4]
160 stp x10, x11, [sp, #16 * 5]
161 stp x12, x13, [sp, #16 * 6]
162 stp x14, x15, [sp, #16 * 7]
163 stp x16, x17, [sp, #16 * 8]
164 stp x18, x19, [sp, #16 * 9]
165 stp x20, x21, [sp, #16 * 10]
166 stp x22, x23, [sp, #16 * 11]
167 stp x24, x25, [sp, #16 * 12]
168 stp x26, x27, [sp, #16 * 13]
169 stp x28, x29, [sp, #16 * 14]
173 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
174 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
175 disable_step_tsk x19, x20 // exceptions when scheduling.
177 apply_ssbd 1, x22, x23
179 mov x29, xzr // fp pointed to user-space
181 add x21, sp, #S_FRAME_SIZE
183 /* Save the task's original addr_limit and set USER_DS */
184 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
185 str x20, [sp, #S_ORIG_ADDR_LIMIT]
187 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
188 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
189 .endif /* \el == 0 */
192 stp lr, x21, [sp, #S_LR]
195 * In order to be able to dump the contents of struct pt_regs at the
196 * time the exception was taken (in case we attempt to walk the call
197 * stack later), chain it together with the stack frames.
200 stp xzr, xzr, [sp, #S_STACKFRAME]
202 stp x29, x22, [sp, #S_STACKFRAME]
204 add x29, sp, #S_STACKFRAME
206 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
208 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
209 * EL0, there is no need to check the state of TTBR0_EL1 since
210 * accesses are always enabled.
211 * Note that the meaning of this bit differs from the ARMv8.1 PAN
212 * feature as all TTBR0_EL1 accesses are disabled, not just those to
215 alternative_if ARM64_HAS_PAN
216 b 1f // skip TTBR0 PAN
217 alternative_else_nop_endif
221 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
222 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
223 b.eq 1f // TTBR0 access already disabled
224 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
227 __uaccess_ttbr0_disable x21
231 stp x22, x23, [sp, #S_PC]
233 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
236 str w21, [sp, #S_SYSCALLNO]
240 * Set sp_el0 to current thread_info.
247 * Registers that may be useful after this macro is invoked:
251 * x23 - aborted PSTATE
255 .macro kernel_exit, el
259 /* Restore the task's original addr_limit. */
260 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
261 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
263 /* No need to restore UAO, it will be restored from SPSR_EL1 */
266 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
271 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
273 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
276 alternative_if ARM64_HAS_PAN
277 b 2f // skip TTBR0 PAN
278 alternative_else_nop_endif
281 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
284 __uaccess_ttbr0_enable x0, x1
288 * Enable errata workarounds only if returning to user. The only
289 * workaround currently required for TTBR0_EL1 changes are for the
290 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
293 bl post_ttbr_update_workaround
297 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
303 ldr x23, [sp, #S_SP] // load return stack pointer
305 tst x22, #PSR_MODE32_BIT // native task?
308 #ifdef CONFIG_ARM64_ERRATUM_845719
309 alternative_if ARM64_WORKAROUND_845719
310 #ifdef CONFIG_PID_IN_CONTEXTIDR
311 mrs x29, contextidr_el1
312 msr contextidr_el1, x29
314 msr contextidr_el1, xzr
316 alternative_else_nop_endif
322 msr elr_el1, x21 // set up the return data
324 ldp x0, x1, [sp, #16 * 0]
325 ldp x2, x3, [sp, #16 * 1]
326 ldp x4, x5, [sp, #16 * 2]
327 ldp x6, x7, [sp, #16 * 3]
328 ldp x8, x9, [sp, #16 * 4]
329 ldp x10, x11, [sp, #16 * 5]
330 ldp x12, x13, [sp, #16 * 6]
331 ldp x14, x15, [sp, #16 * 7]
332 ldp x16, x17, [sp, #16 * 8]
333 ldp x18, x19, [sp, #16 * 9]
334 ldp x20, x21, [sp, #16 * 10]
335 ldp x22, x23, [sp, #16 * 11]
336 ldp x24, x25, [sp, #16 * 12]
337 ldp x26, x27, [sp, #16 * 13]
338 ldp x28, x29, [sp, #16 * 14]
340 add sp, sp, #S_FRAME_SIZE // restore sp
342 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on eret context synchronization
343 * when returning from IPI handler, and when returning to user-space.
347 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
348 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
351 tramp_alias x30, tramp_exit_native
354 tramp_alias x30, tramp_exit_compat
362 .macro irq_stack_entry
363 mov x19, sp // preserve the original sp
366 * Compare sp with the base of the task stack.
367 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
368 * and should switch to the irq stack.
370 ldr x25, [tsk, TSK_STACK]
372 and x25, x25, #~(THREAD_SIZE - 1)
375 ldr_this_cpu x25, irq_stack_ptr, x26
376 mov x26, #IRQ_STACK_SIZE
379 /* switch to the irq stack */
385 * x19 should be preserved between irq_stack_entry and
388 .macro irq_stack_exit
393 * These are the registers used in the syscall handler, and allow us to
394 * have in theory up to 7 arguments to a function - x0 to x6.
396 * x7 is reserved for the system call number in 32-bit mode.
398 wsc_nr .req w25 // number of system calls
399 xsc_nr .req x25 // number of system calls (zero-extended)
400 wscno .req w26 // syscall number
401 xscno .req x26 // syscall number (zero-extended)
402 stbl .req x27 // syscall table pointer
403 tsk .req x28 // current thread_info
406 * Interrupt handling.
409 ldr_l x1, handle_arch_irq
421 .pushsection ".entry.text", "ax"
425 kernel_ventry 1, sync_invalid // Synchronous EL1t
426 kernel_ventry 1, irq_invalid // IRQ EL1t
427 kernel_ventry 1, fiq_invalid // FIQ EL1t
428 kernel_ventry 1, error_invalid // Error EL1t
430 kernel_ventry 1, sync // Synchronous EL1h
431 kernel_ventry 1, irq // IRQ EL1h
432 kernel_ventry 1, fiq_invalid // FIQ EL1h
433 kernel_ventry 1, error // Error EL1h
435 kernel_ventry 0, sync // Synchronous 64-bit EL0
436 kernel_ventry 0, irq // IRQ 64-bit EL0
437 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
438 kernel_ventry 0, error // Error 64-bit EL0
441 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
442 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
443 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
444 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
446 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
447 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
448 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
449 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
453 #ifdef CONFIG_VMAP_STACK
455 * We detected an overflow in kernel_ventry, which switched to the
456 * overflow stack. Stash the exception regs, and head to our overflow
460 /* Restore the original x0 value */
464 * Store the original GPRs to the new stack. The orginal SP (minus
465 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
467 sub sp, sp, #S_FRAME_SIZE
470 add x0, x0, #S_FRAME_SIZE
473 /* Stash the regs for handle_bad_stack */
479 #endif /* CONFIG_VMAP_STACK */
482 * Invalid mode handlers
484 .macro inv_entry, el, reason, regsize = 64
485 kernel_entry \el, \regsize
494 inv_entry 0, BAD_SYNC
495 ENDPROC(el0_sync_invalid)
499 ENDPROC(el0_irq_invalid)
503 ENDPROC(el0_fiq_invalid)
506 inv_entry 0, BAD_ERROR
507 ENDPROC(el0_error_invalid)
510 el0_fiq_invalid_compat:
511 inv_entry 0, BAD_FIQ, 32
512 ENDPROC(el0_fiq_invalid_compat)
516 inv_entry 1, BAD_SYNC
517 ENDPROC(el1_sync_invalid)
521 ENDPROC(el1_irq_invalid)
525 ENDPROC(el1_fiq_invalid)
528 inv_entry 1, BAD_ERROR
529 ENDPROC(el1_error_invalid)
537 mrs x1, esr_el1 // read the syndrome register
538 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
539 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
541 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
543 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
545 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
547 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
549 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
551 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
557 * Fall through to the Data abort case
561 * Data abort handling
564 inherit_daif pstate=x23, tmp=x2
565 clear_address_tag x0, x3
566 mov x2, sp // struct pt_regs
572 * Stack or PC alignment exception handling
575 inherit_daif pstate=x23, tmp=x2
581 * Undefined instruction
583 inherit_daif pstate=x23, tmp=x2
589 * Debug exception handling
591 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
592 cinc x24, x24, eq // set bit '0'
593 tbz x24, #0, el1_inv // EL1 only
595 mov x2, sp // struct pt_regs
596 bl do_debug_exception
599 // TODO: add support for undefined instructions in kernel mode
600 inherit_daif pstate=x23, tmp=x2
612 #ifdef CONFIG_TRACE_IRQFLAGS
613 bl trace_hardirqs_off
618 #ifdef CONFIG_PREEMPT
619 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
620 cbnz w24, 1f // preempt count != 0
621 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
622 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
626 #ifdef CONFIG_TRACE_IRQFLAGS
632 #ifdef CONFIG_PREEMPT
635 1: bl preempt_schedule_irq // irq en/disable is done inside
636 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
637 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
647 mrs x25, esr_el1 // read the syndrome register
648 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
649 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
651 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
653 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
655 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
657 cmp x24, #ESR_ELx_EC_SVE // SVE access
659 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
661 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
663 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
665 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
667 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
669 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
677 mrs x25, esr_el1 // read the syndrome register
678 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
679 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
681 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
683 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
685 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
687 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
689 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
691 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
693 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
695 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
697 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
699 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
701 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
703 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
708 bl el0_svc_compat_handler
723 * Data abort handling
728 clear_address_tag x0, x26
735 * Instruction abort handling
739 #ifdef CONFIG_TRACE_IRQFLAGS
740 bl trace_hardirqs_off
746 bl do_el0_ia_bp_hardening
750 * Floating Point or Advanced SIMD access
760 * Scalable Vector Extension access
770 * Floating Point, Advanced SIMD or SVE exception
780 * Stack or PC alignment exception handling
784 #ifdef CONFIG_TRACE_IRQFLAGS
785 bl trace_hardirqs_off
795 * Undefined instruction
804 * System instructions, for trapped cache maintenance instructions
814 * Debug exception handling
816 tbnz x24, #0, el0_inv // EL0 only
820 bl do_debug_exception
839 #ifdef CONFIG_TRACE_IRQFLAGS
840 bl trace_hardirqs_off
844 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
846 bl do_el0_irq_bp_hardening
851 #ifdef CONFIG_TRACE_IRQFLAGS
879 * Ok, we need to do extra processing, enter the slow path.
884 #ifdef CONFIG_TRACE_IRQFLAGS
885 bl trace_hardirqs_on // enabled while in userspace
887 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
890 * "slow" syscall return path.
894 ldr x1, [tsk, #TSK_TI_FLAGS]
895 and x2, x1, #_TIF_WORK_MASK
896 cbnz x2, work_pending
898 enable_step_tsk x1, x2
912 .popsection // .entry.text
914 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
916 * Exception vectors trampoline.
918 .pushsection ".entry.tramp.text", "ax"
920 .macro tramp_map_kernel, tmp
922 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
923 bic \tmp, \tmp, #USER_ASID_FLAG
925 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
926 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
927 /* ASID already in \tmp[63:48] */
928 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
929 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
930 /* 2MB boundary containing the vectors, so we nobble the walk cache */
931 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
935 alternative_else_nop_endif
936 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
939 .macro tramp_unmap_kernel, tmp
941 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
942 orr \tmp, \tmp, #USER_ASID_FLAG
945 * We avoid running the post_ttbr_update_workaround here because
946 * it's only needed by Cavium ThunderX, which requires KPTI to be
951 .macro tramp_ventry, regsize = 64
955 msr tpidrro_el0, x30 // Restored in kernel_ventry
958 * Defend against branch aliasing attacks by pushing a dummy
959 * entry onto the return stack and using a RET instruction to
960 * enter the full-fat kernel vectors.
966 #ifdef CONFIG_RANDOMIZE_BASE
967 adr x30, tramp_vectors + PAGE_SIZE
968 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
973 prfm plil1strm, [x30, #(1b - tramp_vectors)]
975 add x30, x30, #(1b - tramp_vectors)
980 .macro tramp_exit, regsize = 64
981 adr x30, tramp_vectors
983 tramp_unmap_kernel x30
1005 ENTRY(tramp_exit_native)
1007 END(tramp_exit_native)
1009 ENTRY(tramp_exit_compat)
1011 END(tramp_exit_compat)
1014 .popsection // .entry.tramp.text
1015 #ifdef CONFIG_RANDOMIZE_BASE
1016 .pushsection ".rodata", "a"
1018 .globl __entry_tramp_data_start
1019 __entry_tramp_data_start:
1021 .popsection // .rodata
1022 #endif /* CONFIG_RANDOMIZE_BASE */
1023 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1026 * Register switch for AArch64. The callee-saved registers need to be saved
1027 * and restored. On entry:
1028 * x0 = previous task_struct (must be preserved across the switch)
1029 * x1 = next task_struct
1030 * Previous and next are guaranteed not to be the same.
1033 ENTRY(cpu_switch_to)
1034 mov x10, #THREAD_CPU_CONTEXT
1037 stp x19, x20, [x8], #16 // store callee-saved registers
1038 stp x21, x22, [x8], #16
1039 stp x23, x24, [x8], #16
1040 stp x25, x26, [x8], #16
1041 stp x27, x28, [x8], #16
1042 stp x29, x9, [x8], #16
1045 ldp x19, x20, [x8], #16 // restore callee-saved registers
1046 ldp x21, x22, [x8], #16
1047 ldp x23, x24, [x8], #16
1048 ldp x25, x26, [x8], #16
1049 ldp x27, x28, [x8], #16
1050 ldp x29, x9, [x8], #16
1055 ENDPROC(cpu_switch_to)
1056 NOKPROBE(cpu_switch_to)
1059 * This is how we return from a fork.
1061 ENTRY(ret_from_fork)
1063 cbz x19, 1f // not a kernel thread
1066 1: get_thread_info tsk
1068 ENDPROC(ret_from_fork)
1069 NOKPROBE(ret_from_fork)
1071 #ifdef CONFIG_ARM_SDE_INTERFACE
1073 #include <asm/sdei.h>
1074 #include <uapi/linux/arm_sdei.h>
1076 .macro sdei_handler_exit exit_mode
1077 /* On success, this call never returns... */
1078 cmp \exit_mode, #SDEI_EXIT_SMC
1086 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1088 * The regular SDEI entry point may have been unmapped along with the rest of
1089 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
1090 * argument accessible.
1092 * This clobbers x4, __sdei_handler() will restore this from firmware's
1096 .pushsection ".entry.tramp.text", "ax"
1097 ENTRY(__sdei_asm_entry_trampoline)
1099 tbz x4, #USER_ASID_BIT, 1f
1101 tramp_map_kernel tmp=x4
1106 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
1107 * the kernel on exit.
1109 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1111 #ifdef CONFIG_RANDOMIZE_BASE
1112 adr x4, tramp_vectors + PAGE_SIZE
1113 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1116 ldr x4, =__sdei_asm_handler
1119 ENDPROC(__sdei_asm_entry_trampoline)
1120 NOKPROBE(__sdei_asm_entry_trampoline)
1123 * Make the exit call and restore the original ttbr1_el1
1125 * x0 & x1: setup for the exit API call
1127 * x4: struct sdei_registered_event argument from registration time.
1129 ENTRY(__sdei_asm_exit_trampoline)
1130 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1133 tramp_unmap_kernel tmp=x4
1135 1: sdei_handler_exit exit_mode=x2
1136 ENDPROC(__sdei_asm_exit_trampoline)
1137 NOKPROBE(__sdei_asm_exit_trampoline)
1139 .popsection // .entry.tramp.text
1140 #ifdef CONFIG_RANDOMIZE_BASE
1141 .pushsection ".rodata", "a"
1142 __sdei_asm_trampoline_next_handler:
1143 .quad __sdei_asm_handler
1144 .popsection // .rodata
1145 #endif /* CONFIG_RANDOMIZE_BASE */
1146 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1149 * Software Delegated Exception entry point.
1152 * x1: struct sdei_registered_event argument from registration time.
1153 * x2: interrupted PC
1154 * x3: interrupted PSTATE
1155 * x4: maybe clobbered by the trampoline
1157 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1158 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1161 ENTRY(__sdei_asm_handler)
1162 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1163 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1164 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1165 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1166 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1167 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1168 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1169 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1170 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1171 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1172 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1173 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1174 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1175 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1177 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1181 #ifdef CONFIG_VMAP_STACK
1183 * entry.S may have been using sp as a scratch register, find whether
1184 * this is a normal or critical event and switch to the appropriate
1185 * stack for this CPU.
1187 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1189 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1191 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1192 2: mov x6, #SDEI_STACK_SIZE
1198 * We may have interrupted userspace, or a guest, or exit-from or
1199 * return-to either of these. We can't trust sp_el0, restore it.
1202 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1205 /* If we interrupted the kernel point to the previous stack/frame. */
1209 csel x29, x29, xzr, eq // fp, or zero
1210 csel x4, x2, xzr, eq // elr, or zero
1212 stp x29, x4, [sp, #-16]!
1215 add x0, x19, #SDEI_EVENT_INTREGS
1220 /* restore regs >x17 that we clobbered */
1221 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1222 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1223 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1224 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1227 mov x1, x0 // address to complete_and_resume
1228 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1230 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1231 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1234 ldr_l x2, sdei_exit_mode
1236 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1237 sdei_handler_exit exit_mode=x2
1238 alternative_else_nop_endif
1240 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1241 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1244 ENDPROC(__sdei_asm_handler)
1245 NOKPROBE(__sdei_asm_handler)
1246 #endif /* CONFIG_ARM_SDE_INTERFACE */