2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/thread_info.h>
33 #include <asm/asm-uaccess.h>
34 #include <asm/unistd.h>
37 * Context tracking subsystem. Used to instrument transitions
38 * between user and kernel mode.
40 .macro ct_user_exit, syscall = 0
41 #ifdef CONFIG_CONTEXT_TRACKING
42 bl context_tracking_user_exit
45 * Save/restore needed during syscalls. Restore syscall arguments from
46 * the values already saved on stack during kernel_entry.
49 ldp x2, x3, [sp, #S_X2]
50 ldp x4, x5, [sp, #S_X4]
51 ldp x6, x7, [sp, #S_X6]
57 #ifdef CONFIG_CONTEXT_TRACKING
58 bl context_tracking_user_enter
71 .macro kernel_ventry label
73 sub sp, sp, #S_FRAME_SIZE
77 .macro kernel_entry, el, regsize = 64
79 mov w0, w0 // zero upper 32 bits of x0
81 stp x0, x1, [sp, #16 * 0]
82 stp x2, x3, [sp, #16 * 1]
83 stp x4, x5, [sp, #16 * 2]
84 stp x6, x7, [sp, #16 * 3]
85 stp x8, x9, [sp, #16 * 4]
86 stp x10, x11, [sp, #16 * 5]
87 stp x12, x13, [sp, #16 * 6]
88 stp x14, x15, [sp, #16 * 7]
89 stp x16, x17, [sp, #16 * 8]
90 stp x18, x19, [sp, #16 * 9]
91 stp x20, x21, [sp, #16 * 10]
92 stp x22, x23, [sp, #16 * 11]
93 stp x24, x25, [sp, #16 * 12]
94 stp x26, x27, [sp, #16 * 13]
95 stp x28, x29, [sp, #16 * 14]
100 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
101 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
102 disable_step_tsk x19, x20 // exceptions when scheduling.
104 mov x29, xzr // fp pointed to user-space
106 add x21, sp, #S_FRAME_SIZE
108 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
109 ldr x20, [tsk, #TI_ADDR_LIMIT]
110 str x20, [sp, #S_ORIG_ADDR_LIMIT]
111 mov x20, #TASK_SIZE_64
112 str x20, [tsk, #TI_ADDR_LIMIT]
113 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
114 .endif /* \el == 0 */
117 stp lr, x21, [sp, #S_LR]
118 stp x22, x23, [sp, #S_PC]
121 * Set syscallno to -1 by default (overridden later if real syscall).
125 str x21, [sp, #S_SYSCALLNO]
129 * Set sp_el0 to current thread_info.
136 * Registers that may be useful after this macro is invoked:
140 * x23 - aborted PSTATE
144 .macro kernel_exit, el
146 /* Restore the task's original addr_limit. */
147 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
148 str x20, [tsk, #TI_ADDR_LIMIT]
150 /* No need to restore UAO, it will be restored from SPSR_EL1 */
153 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
156 ldr x23, [sp, #S_SP] // load return stack pointer
158 #ifdef CONFIG_ARM64_ERRATUM_845719
159 alternative_if ARM64_WORKAROUND_845719
161 #ifdef CONFIG_PID_IN_CONTEXTIDR
162 mrs x29, contextidr_el1
163 msr contextidr_el1, x29
165 msr contextidr_el1, xzr
168 alternative_else_nop_endif
171 msr elr_el1, x21 // set up the return data
173 ldp x0, x1, [sp, #16 * 0]
174 ldp x2, x3, [sp, #16 * 1]
175 ldp x4, x5, [sp, #16 * 2]
176 ldp x6, x7, [sp, #16 * 3]
177 ldp x8, x9, [sp, #16 * 4]
178 ldp x10, x11, [sp, #16 * 5]
179 ldp x12, x13, [sp, #16 * 6]
180 ldp x14, x15, [sp, #16 * 7]
181 ldp x16, x17, [sp, #16 * 8]
182 ldp x18, x19, [sp, #16 * 9]
183 ldp x20, x21, [sp, #16 * 10]
184 ldp x22, x23, [sp, #16 * 11]
185 ldp x24, x25, [sp, #16 * 12]
186 ldp x26, x27, [sp, #16 * 13]
187 ldp x28, x29, [sp, #16 * 14]
189 add sp, sp, #S_FRAME_SIZE // restore sp
190 eret // return to kernel
193 .macro get_thread_info, rd
197 .macro irq_stack_entry
198 mov x19, sp // preserve the original sp
201 * Compare sp with the current thread_info, if the top
202 * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and
203 * should switch to the irq stack.
205 and x25, x19, #~(THREAD_SIZE - 1)
209 this_cpu_ptr irq_stack, x25, x26
210 mov x26, #IRQ_STACK_START_SP
213 /* switch to the irq stack */
217 * Add a dummy stack frame, this non-standard format is fixed up
220 stp x29, x19, [sp, #-16]!
227 * x19 should be preserved between irq_stack_entry and
230 .macro irq_stack_exit
235 * These are the registers used in the syscall handler, and allow us to
236 * have in theory up to 7 arguments to a function - x0 to x6.
238 * x7 is reserved for the system call number in 32-bit mode.
240 sc_nr .req x25 // number of system calls
241 scno .req x26 // syscall number
242 stbl .req x27 // syscall table pointer
243 tsk .req x28 // current thread_info
246 * Interrupt handling.
249 ldr_l x1, handle_arch_irq
261 .pushsection ".entry.text", "ax"
265 kernel_ventry el1_sync_invalid // Synchronous EL1t
266 kernel_ventry el1_irq_invalid // IRQ EL1t
267 kernel_ventry el1_fiq_invalid // FIQ EL1t
268 kernel_ventry el1_error_invalid // Error EL1t
270 kernel_ventry el1_sync // Synchronous EL1h
271 kernel_ventry el1_irq // IRQ EL1h
272 kernel_ventry el1_fiq_invalid // FIQ EL1h
273 kernel_ventry el1_error_invalid // Error EL1h
275 kernel_ventry el0_sync // Synchronous 64-bit EL0
276 kernel_ventry el0_irq // IRQ 64-bit EL0
277 kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0
278 kernel_ventry el0_error_invalid // Error 64-bit EL0
281 kernel_ventry el0_sync_compat // Synchronous 32-bit EL0
282 kernel_ventry el0_irq_compat // IRQ 32-bit EL0
283 kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
284 kernel_ventry el0_error_invalid_compat // Error 32-bit EL0
286 kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0
287 kernel_ventry el0_irq_invalid // IRQ 32-bit EL0
288 kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0
289 kernel_ventry el0_error_invalid // Error 32-bit EL0
294 * Invalid mode handlers
296 .macro inv_entry, el, reason, regsize = 64
297 kernel_entry \el, \regsize
305 inv_entry 0, BAD_SYNC
306 ENDPROC(el0_sync_invalid)
310 ENDPROC(el0_irq_invalid)
314 ENDPROC(el0_fiq_invalid)
317 inv_entry 0, BAD_ERROR
318 ENDPROC(el0_error_invalid)
321 el0_fiq_invalid_compat:
322 inv_entry 0, BAD_FIQ, 32
323 ENDPROC(el0_fiq_invalid_compat)
325 el0_error_invalid_compat:
326 inv_entry 0, BAD_ERROR, 32
327 ENDPROC(el0_error_invalid_compat)
331 inv_entry 1, BAD_SYNC
332 ENDPROC(el1_sync_invalid)
336 ENDPROC(el1_irq_invalid)
340 ENDPROC(el1_fiq_invalid)
343 inv_entry 1, BAD_ERROR
344 ENDPROC(el1_error_invalid)
352 mrs x1, esr_el1 // read the syndrome register
353 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
354 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
356 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
358 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
360 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
362 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
364 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
366 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
372 * Fall through to the Data abort case
376 * Data abort handling
380 // re-enable interrupts if they were enabled in the aborted context
381 tbnz x23, #7, 1f // PSR_I_BIT
384 clear_address_tag x0, x3
385 mov x2, sp // struct pt_regs
388 // disable interrupts before pulling preserved data off the stack
393 * Stack or PC alignment exception handling
401 * Undefined instruction
408 * Debug exception handling
410 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
411 cinc x24, x24, eq // set bit '0'
412 tbz x24, #0, el1_inv // EL1 only
414 mov x2, sp // struct pt_regs
415 bl do_debug_exception
418 // TODO: add support for undefined instructions in kernel mode
430 #ifdef CONFIG_TRACE_IRQFLAGS
431 bl trace_hardirqs_off
436 #ifdef CONFIG_PREEMPT
437 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
438 cbnz w24, 1f // preempt count != 0
439 ldr x0, [tsk, #TI_FLAGS] // get flags
440 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
444 #ifdef CONFIG_TRACE_IRQFLAGS
450 #ifdef CONFIG_PREEMPT
453 1: bl preempt_schedule_irq // irq en/disable is done inside
454 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
455 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
465 mrs x25, esr_el1 // read the syndrome register
466 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
467 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
469 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
471 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
473 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
475 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
477 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
479 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
481 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
483 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
485 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
493 mrs x25, esr_el1 // read the syndrome register
494 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
495 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
497 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
499 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
501 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
503 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
505 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
507 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
509 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
511 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
513 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
515 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
517 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
519 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
524 * AArch32 syscall handling
526 adrp stbl, compat_sys_call_table // load compat syscall table pointer
527 uxtw scno, w7 // syscall number in w7 (r7)
528 mov sc_nr, #__NR_compat_syscalls
539 * Data abort handling
542 // enable interrupts before calling the main handler
545 clear_address_tag x0, x26
552 * Instruction abort handling
555 // enable interrupts before calling the main handler
565 * Floating Point or Advanced SIMD access
575 * Floating Point or Advanced SIMD exception
585 * Stack or PC alignment exception handling
588 // enable interrupts before calling the main handler
598 * Undefined instruction
600 // enable interrupts before calling the main handler
608 * System instructions, for trapped cache maintenance instructions
618 * Debug exception handling
620 tbnz x24, #0, el0_inv // EL0 only
624 bl do_debug_exception
643 #ifdef CONFIG_TRACE_IRQFLAGS
644 bl trace_hardirqs_off
650 #ifdef CONFIG_TRACE_IRQFLAGS
657 * Register switch for AArch64. The callee-saved registers need to be saved
658 * and restored. On entry:
659 * x0 = previous task_struct (must be preserved across the switch)
660 * x1 = next task_struct
661 * Previous and next are guaranteed not to be the same.
665 mov x10, #THREAD_CPU_CONTEXT
668 stp x19, x20, [x8], #16 // store callee-saved registers
669 stp x21, x22, [x8], #16
670 stp x23, x24, [x8], #16
671 stp x25, x26, [x8], #16
672 stp x27, x28, [x8], #16
673 stp x29, x9, [x8], #16
676 ldp x19, x20, [x8], #16 // restore callee-saved registers
677 ldp x21, x22, [x8], #16
678 ldp x23, x24, [x8], #16
679 ldp x25, x26, [x8], #16
680 ldp x27, x28, [x8], #16
681 ldp x29, x9, [x8], #16
684 and x9, x9, #~(THREAD_SIZE - 1)
687 ENDPROC(cpu_switch_to)
690 * This is the fast syscall return path. We do as little as possible here,
691 * and this includes saving x0 back into the kernel stack.
694 disable_irq // disable interrupts
695 str x0, [sp, #S_X0] // returned x0
696 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
697 and x2, x1, #_TIF_SYSCALL_WORK
698 cbnz x2, ret_fast_syscall_trace
699 and x2, x1, #_TIF_WORK_MASK
700 cbnz x2, work_pending
701 enable_step_tsk x1, x2
703 ret_fast_syscall_trace:
704 enable_irq // enable interrupts
705 b __sys_trace_return_skipped // we already saved x0
708 * Ok, we need to do extra processing, enter the slow path.
713 #ifdef CONFIG_TRACE_IRQFLAGS
714 bl trace_hardirqs_on // enabled while in userspace
716 ldr x1, [tsk, #TI_FLAGS] // re-check for single-step
719 * "slow" syscall return path.
722 disable_irq // disable interrupts
723 ldr x1, [tsk, #TI_FLAGS]
724 and x2, x1, #_TIF_WORK_MASK
725 cbnz x2, work_pending
727 enable_step_tsk x1, x2
732 * This is how we return from a fork.
736 cbz x19, 1f // not a kernel thread
739 1: get_thread_info tsk
741 ENDPROC(ret_from_fork)
748 adrp stbl, sys_call_table // load syscall table pointer
749 uxtw scno, w8 // syscall number in w8
750 mov sc_nr, #__NR_syscalls
751 el0_svc_naked: // compat entry point
752 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
756 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
757 tst x16, #_TIF_SYSCALL_WORK
759 cmp scno, sc_nr // check upper syscall limit
761 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
762 blr x16 // call sys_* routine
771 * This is the really slow path. We're going to be doing context
772 * switches, and waiting for our parent to respond.
775 mov w0, #-1 // set default errno for
776 cmp scno, x0 // user-issued syscall(-1)
781 bl syscall_trace_enter
782 cmp w0, #-1 // skip the syscall?
783 b.eq __sys_trace_return_skipped
784 uxtw scno, w0 // syscall number (possibly new)
785 mov x1, sp // pointer to regs
786 cmp scno, sc_nr // check upper syscall limit
788 ldp x0, x1, [sp] // restore the syscall args
789 ldp x2, x3, [sp, #S_X2]
790 ldp x4, x5, [sp, #S_X4]
791 ldp x6, x7, [sp, #S_X6]
792 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
793 blr x16 // call sys_* routine
796 str x0, [sp, #S_X0] // save returned x0
797 __sys_trace_return_skipped:
799 bl syscall_trace_exit
807 .popsection // .entry.text
810 * Special system call wrappers.
812 ENTRY(sys_rt_sigreturn_wrapper)
815 ENDPROC(sys_rt_sigreturn_wrapper)