arch/arm64/kernel/traps.c

   1 /*
   2  * Based on arch/arm/kernel/traps.c
   3  *
   4  * Copyright (C) 1995-2009 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/bug.h>
  21 #include <linux/signal.h>
  22 #include <linux/personality.h>
  23 #include <linux/kallsyms.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/hardirq.h>
  27 #include <linux/kdebug.h>
  28 #include <linux/module.h>
  29 #include <linux/kexec.h>
  30 #include <linux/delay.h>
  31 #include <linux/init.h>
  32 #include <linux/sched/signal.h>
  33 #include <linux/sched/debug.h>
  34 #include <linux/sched/task_stack.h>
  35 #include <linux/sizes.h>
  36 #include <linux/syscalls.h>
  37 #include <linux/mm_types.h>
  38
  39 #include <asm/atomic.h>
  40 #include <asm/bug.h>
  41 #include <asm/cpufeature.h>
  42 #include <asm/daifflags.h>
  43 #include <asm/debug-monitors.h>
  44 #include <asm/esr.h>
  45 #include <asm/insn.h>
  46 #include <asm/traps.h>
  47 #include <asm/smp.h>
  48 #include <asm/stack_pointer.h>
  49 #include <asm/stacktrace.h>
  50 #include <asm/exception.h>
  51 #include <asm/system_misc.h>
  52 #include <asm/sysreg.h>
  53
  54 static const char *handler[]= {
  55         "Synchronous Abort",
  56         "IRQ",
  57         "FIQ",
  58         "Error"
  59 };
  60
  61 int show_unhandled_signals = 0;
  62
  63 static void dump_backtrace_entry(unsigned long where)
  64 {
  65         printk(" %pS\n", (void *)where);
  66 }
  67
  68 static void __dump_instr(const char *lvl, struct pt_regs *regs)
  69 {
  70         unsigned long addr = instruction_pointer(regs);
  71         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
  72         int i;
  73
  74         for (i = -4; i < 1; i++) {
  75                 unsigned int val, bad;
  76
  77                 bad = get_user(val, &((u32 *)addr)[i]);
  78
  79                 if (!bad)
  80                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
  81                 else {
  82                         p += sprintf(p, "bad PC value");
  83                         break;
  84                 }
  85         }
  86         printk("%sCode: %s\n", lvl, str);
  87 }
  88
  89 static void dump_instr(const char *lvl, struct pt_regs *regs)
  90 {
  91         if (!user_mode(regs)) {
  92                 mm_segment_t fs = get_fs();
  93                 set_fs(KERNEL_DS);
  94                 __dump_instr(lvl, regs);
  95                 set_fs(fs);
  96         } else {
  97                 __dump_instr(lvl, regs);
  98         }
  99 }
 100
 101 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 102 {
 103         struct stackframe frame;
 104         int skip;
 105
 106         pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
 107
 108         if (!tsk)
 109                 tsk = current;
 110
 111         if (!try_get_task_stack(tsk))
 112                 return;
 113
 114         if (tsk == current) {
 115                 frame.fp = (unsigned long)__builtin_frame_address(0);
 116                 frame.pc = (unsigned long)dump_backtrace;
 117         } else {
 118                 /*
 119                  * task blocked in __switch_to
 120                  */
 121                 frame.fp = thread_saved_fp(tsk);
 122                 frame.pc = thread_saved_pc(tsk);
 123         }
 124 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 125         frame.graph = tsk->curr_ret_stack;
 126 #endif
 127
 128         skip = !!regs;
 129         printk("Call trace:\n");
 130         do {
 131                 /* skip until specified stack frame */
 132                 if (!skip) {
 133                         dump_backtrace_entry(frame.pc);
 134                 } else if (frame.fp == regs->regs[29]) {
 135                         skip = 0;
 136                         /*
 137                          * Mostly, this is the case where this function is
 138                          * called in panic/abort. As exception handler's
 139                          * stack frame does not contain the corresponding pc
 140                          * at which an exception has taken place, use regs->pc
 141                          * instead.
 142                          */
 143                         dump_backtrace_entry(regs->pc);
 144                 }
 145         } while (!unwind_frame(tsk, &frame));
 146
 147         put_task_stack(tsk);
 148 }
 149
 150 void show_stack(struct task_struct *tsk, unsigned long *sp)
 151 {
 152         dump_backtrace(NULL, tsk);
 153         barrier();
 154 }
 155
 156 #ifdef CONFIG_PREEMPT
 157 #define S_PREEMPT " PREEMPT"
 158 #else
 159 #define S_PREEMPT ""
 160 #endif
 161 #define S_SMP " SMP"
 162
 163 static int __die(const char *str, int err, struct pt_regs *regs)
 164 {
 165         struct task_struct *tsk = current;
 166         static int die_counter;
 167         int ret;
 168
 169         pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
 170                  str, err, ++die_counter);
 171
 172         /* trap and error numbers are mostly meaningless on ARM */
 173         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 174         if (ret == NOTIFY_STOP)
 175                 return ret;
 176
 177         print_modules();
 178         __show_regs(regs);
 179         pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
 180                  TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk),
 181                  end_of_stack(tsk));
 182
 183         if (!user_mode(regs)) {
 184                 dump_backtrace(regs, tsk);
 185                 dump_instr(KERN_EMERG, regs);
 186         }
 187
 188         return ret;
 189 }
 190
 191 static DEFINE_RAW_SPINLOCK(die_lock);
 192
 193 /*
 194  * This function is protected against re-entrancy.
 195  */
 196 void die(const char *str, struct pt_regs *regs, int err)
 197 {
 198         int ret;
 199         unsigned long flags;
 200
 201         raw_spin_lock_irqsave(&die_lock, flags);
 202
 203         oops_enter();
 204
 205         console_verbose();
 206         bust_spinlocks(1);
 207         ret = __die(str, err, regs);
 208
 209         if (regs && kexec_should_crash(current))
 210                 crash_kexec(regs);
 211
 212         bust_spinlocks(0);
 213         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 214         oops_exit();
 215
 216         if (in_interrupt())
 217                 panic("Fatal exception in interrupt");
 218         if (panic_on_oops)
 219                 panic("Fatal exception");
 220
 221         raw_spin_unlock_irqrestore(&die_lock, flags);
 222
 223         if (ret != NOTIFY_STOP)
 224                 do_exit(SIGSEGV);
 225 }
 226
 227 static void arm64_show_signal(int signo, const char *str)
 228 {
 229         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 230                                       DEFAULT_RATELIMIT_BURST);
 231         struct task_struct *tsk = current;
 232         unsigned int esr = tsk->thread.fault_code;
 233         struct pt_regs *regs = task_pt_regs(tsk);
 234
 235         /* Leave if the signal won't be shown */
 236         if (!show_unhandled_signals ||
 237             !unhandled_signal(tsk, signo) ||
 238             !__ratelimit(&rs))
 239                 return;
 240
 241         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 242         if (esr)
 243                 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
 244
 245         pr_cont("%s", str);
 246         print_vma_addr(KERN_CONT " in ", regs->pc);
 247         pr_cont("\n");
 248         __show_regs(regs);
 249 }
 250
 251 void arm64_force_sig_fault(int signo, int code, void __user *addr,
 252                            const char *str)
 253 {
 254         arm64_show_signal(signo, str);
 255         force_sig_fault(signo, code, addr, current);
 256 }
 257
 258 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
 259                             const char *str)
 260 {
 261         arm64_show_signal(SIGBUS, str);
 262         force_sig_mceerr(code, addr, lsb, current);
 263 }
 264
 265 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
 266                                        const char *str)
 267 {
 268         arm64_show_signal(SIGTRAP, str);
 269         force_sig_ptrace_errno_trap(errno, addr);
 270 }
 271
 272 void arm64_notify_die(const char *str, struct pt_regs *regs,
 273                       int signo, int sicode, void __user *addr,
 274                       int err)
 275 {
 276         if (user_mode(regs)) {
 277                 WARN_ON(regs != current_pt_regs());
 278                 current->thread.fault_address = 0;
 279                 current->thread.fault_code = err;
 280
 281                 arm64_force_sig_fault(signo, sicode, addr, str);
 282         } else {
 283                 die(str, regs, err);
 284         }
 285 }
 286
 287 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 288 {
 289         regs->pc += size;
 290
 291         /*
 292          * If we were single stepping, we want to get the step exception after
 293          * we return from the trap.
 294          */
 295         if (user_mode(regs))
 296                 user_fastforward_single_step(current);
 297 }
 298
 299 static LIST_HEAD(undef_hook);
 300 static DEFINE_RAW_SPINLOCK(undef_lock);
 301
 302 void register_undef_hook(struct undef_hook *hook)
 303 {
 304         unsigned long flags;
 305
 306         raw_spin_lock_irqsave(&undef_lock, flags);
 307         list_add(&hook->node, &undef_hook);
 308         raw_spin_unlock_irqrestore(&undef_lock, flags);
 309 }
 310
 311 void unregister_undef_hook(struct undef_hook *hook)
 312 {
 313         unsigned long flags;
 314
 315         raw_spin_lock_irqsave(&undef_lock, flags);
 316         list_del(&hook->node);
 317         raw_spin_unlock_irqrestore(&undef_lock, flags);
 318 }
 319
 320 static int call_undef_hook(struct pt_regs *regs)
 321 {
 322         struct undef_hook *hook;
 323         unsigned long flags;
 324         u32 instr;
 325         int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
 326         void __user *pc = (void __user *)instruction_pointer(regs);
 327
 328         if (!user_mode(regs))
 329                 return 1;
 330
 331         if (compat_thumb_mode(regs)) {
 332                 /* 16-bit Thumb instruction */
 333                 __le16 instr_le;
 334                 if (get_user(instr_le, (__le16 __user *)pc))
 335                         goto exit;
 336                 instr = le16_to_cpu(instr_le);
 337                 if (aarch32_insn_is_wide(instr)) {
 338                         u32 instr2;
 339
 340                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 341                                 goto exit;
 342                         instr2 = le16_to_cpu(instr_le);
 343                         instr = (instr << 16) | instr2;
 344                 }
 345         } else {
 346                 /* 32-bit ARM instruction */
 347                 __le32 instr_le;
 348                 if (get_user(instr_le, (__le32 __user *)pc))
 349                         goto exit;
 350                 instr = le32_to_cpu(instr_le);
 351         }
 352
 353         raw_spin_lock_irqsave(&undef_lock, flags);
 354         list_for_each_entry(hook, &undef_hook, node)
 355                 if ((instr & hook->instr_mask) == hook->instr_val &&
 356                         (regs->pstate & hook->pstate_mask) == hook->pstate_val)
 357                         fn = hook->fn;
 358
 359         raw_spin_unlock_irqrestore(&undef_lock, flags);
 360 exit:
 361         return fn ? fn(regs, instr) : 1;
 362 }
 363
 364 void force_signal_inject(int signal, int code, unsigned long address)
 365 {
 366         const char *desc;
 367         struct pt_regs *regs = current_pt_regs();
 368
 369         switch (signal) {
 370         case SIGILL:
 371                 desc = "undefined instruction";
 372                 break;
 373         case SIGSEGV:
 374                 desc = "illegal memory access";
 375                 break;
 376         default:
 377                 desc = "unknown or unrecoverable error";
 378                 break;
 379         }
 380
 381         /* Force signals we don't understand to SIGKILL */
 382         if (WARN_ON(signal != SIGKILL &&
 383                     siginfo_layout(signal, code) != SIL_FAULT)) {
 384                 signal = SIGKILL;
 385         }
 386
 387         arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
 388 }
 389
 390 /*
 391  * Set up process info to signal segmentation fault - called on access error.
 392  */
 393 void arm64_notify_segfault(unsigned long addr)
 394 {
 395         int code;
 396
 397         down_read(&current->mm->mmap_sem);
 398         if (find_vma(current->mm, addr) == NULL)
 399                 code = SEGV_MAPERR;
 400         else
 401                 code = SEGV_ACCERR;
 402         up_read(&current->mm->mmap_sem);
 403
 404         force_signal_inject(SIGSEGV, code, addr);
 405 }
 406
 407 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 408 {
 409         /* check for AArch32 breakpoint instructions */
 410         if (!aarch32_break_handler(regs))
 411                 return;
 412
 413         if (call_undef_hook(regs) == 0)
 414                 return;
 415
 416         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 417 }
 418
 419 void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
 420 {
 421         sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
 422 }
 423
 424 #define __user_cache_maint(insn, address, res)                  \
 425         if (address >= user_addr_max()) {                       \
 426                 res = -EFAULT;                                  \
 427         } else {                                                \
 428                 uaccess_ttbr0_enable();                         \
 429                 asm volatile (                                  \
 430                         "1:     " insn ", %1\n"                 \
 431                         "       mov     %w0, #0\n"              \
 432                         "2:\n"                                  \
 433                         "       .pushsection .fixup,\"ax\"\n"   \
 434                         "       .align  2\n"                    \
 435                         "3:     mov     %w0, %w2\n"             \
 436                         "       b       2b\n"                   \
 437                         "       .popsection\n"                  \
 438                         _ASM_EXTABLE(1b, 3b)                    \
 439                         : "=r" (res)                            \
 440                         : "r" (address), "i" (-EFAULT));        \
 441                 uaccess_ttbr0_disable();                        \
 442         }
 443
 444 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
 445 {
 446         unsigned long address;
 447         int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
 448         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 449         int ret = 0;
 450
 451         address = untagged_addr(pt_regs_read_reg(regs, rt));
 452
 453         switch (crm) {
 454         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 455                 __user_cache_maint("dc civac", address, ret);
 456                 break;
 457         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 458                 __user_cache_maint("dc civac", address, ret);
 459                 break;
 460         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 461                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 462                 break;
 463         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 464                 __user_cache_maint("dc civac", address, ret);
 465                 break;
 466         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 467                 __user_cache_maint("ic ivau", address, ret);
 468                 break;
 469         default:
 470                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 471                 return;
 472         }
 473
 474         if (ret)
 475                 arm64_notify_segfault(address);
 476         else
 477                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 478 }
 479
 480 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
 481 {
 482         int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
 483         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 484
 485         pt_regs_write_reg(regs, rt, val);
 486
 487         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 488 }
 489
 490 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 491 {
 492         int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
 493
 494         pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
 495         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 496 }
 497
 498 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 499 {
 500         int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
 501
 502         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 503         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 504 }
 505
 506 struct sys64_hook {
 507         unsigned int esr_mask;
 508         unsigned int esr_val;
 509         void (*handler)(unsigned int esr, struct pt_regs *regs);
 510 };
 511
 512 static struct sys64_hook sys64_hooks[] = {
 513         {
 514                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 515                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 516                 .handler = user_cache_maint_handler,
 517         },
 518         {
 519                 /* Trap read access to CTR_EL0 */
 520                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 521                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 522                 .handler = ctr_read_handler,
 523         },
 524         {
 525                 /* Trap read access to CNTVCT_EL0 */
 526                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 527                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 528                 .handler = cntvct_read_handler,
 529         },
 530         {
 531                 /* Trap read access to CNTFRQ_EL0 */
 532                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 533                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 534                 .handler = cntfrq_read_handler,
 535         },
 536         {},
 537 };
 538
 539 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
 540 {
 541         struct sys64_hook *hook;
 542
 543         for (hook = sys64_hooks; hook->handler; hook++)
 544                 if ((hook->esr_mask & esr) == hook->esr_val) {
 545                         hook->handler(esr, regs);
 546                         return;
 547                 }
 548
 549         /*
 550          * New SYS instructions may previously have been undefined at EL0. Fall
 551          * back to our usual undefined instruction handler so that we handle
 552          * these consistently.
 553          */
 554         do_undefinstr(regs);
 555 }
 556
 557 static const char *esr_class_str[] = {
 558         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 559         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 560         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 561         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 562         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 563         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 564         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 565         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 566         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 567         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 568         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 569         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 570         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 571         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 572         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 573         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 574         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 575         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 576         [ESR_ELx_EC_SVE]                = "SVE",
 577         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 578         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 579         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 580         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 581         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 582         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 583         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 584         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 585         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 586         [ESR_ELx_EC_SERROR]             = "SError",
 587         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 588         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 589         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 590         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 591         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 592         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 593         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 594         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 595         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 596 };
 597
 598 const char *esr_get_class_string(u32 esr)
 599 {
 600         return esr_class_str[ESR_ELx_EC(esr)];
 601 }
 602
 603 /*
 604  * bad_mode handles the impossible case in the exception vector. This is always
 605  * fatal.
 606  */
 607 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 608 {
 609         console_verbose();
 610
 611         pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
 612                 handler[reason], smp_processor_id(), esr,
 613                 esr_get_class_string(esr));
 614
 615         die("Oops - bad mode", regs, 0);
 616         local_daif_mask();
 617         panic("bad mode");
 618 }
 619
 620 /*
 621  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 622  * exceptions taken from EL0. Unlike bad_mode, this returns.
 623  */
 624 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
 625 {
 626         void __user *pc = (void __user *)instruction_pointer(regs);
 627
 628         current->thread.fault_address = 0;
 629         current->thread.fault_code = esr;
 630
 631         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 632                               "Bad EL0 synchronous exception");
 633 }
 634
 635 #ifdef CONFIG_VMAP_STACK
 636
 637 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 638         __aligned(16);
 639
 640 asmlinkage void handle_bad_stack(struct pt_regs *regs)
 641 {
 642         unsigned long tsk_stk = (unsigned long)current->stack;
 643         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 644         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 645         unsigned int esr = read_sysreg(esr_el1);
 646         unsigned long far = read_sysreg(far_el1);
 647
 648         console_verbose();
 649         pr_emerg("Insufficient stack space to handle exception!");
 650
 651         pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
 652         pr_emerg("FAR: 0x%016lx\n", far);
 653
 654         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 655                  tsk_stk, tsk_stk + THREAD_SIZE);
 656         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 657                  irq_stk, irq_stk + THREAD_SIZE);
 658         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 659                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 660
 661         __show_regs(regs);
 662
 663         /*
 664          * We use nmi_panic to limit the potential for recusive overflows, and
 665          * to get a better stack trace.
 666          */
 667         nmi_panic(NULL, "kernel stack overflow");
 668         cpu_park_loop();
 669 }
 670 #endif
 671
 672 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
 673 {
 674         console_verbose();
 675
 676         pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
 677                 smp_processor_id(), esr, esr_get_class_string(esr));
 678         if (regs)
 679                 __show_regs(regs);
 680
 681         nmi_panic(regs, "Asynchronous SError Interrupt");
 682
 683         cpu_park_loop();
 684         unreachable();
 685 }
 686
 687 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
 688 {
 689         u32 aet = arm64_ras_serror_get_severity(esr);
 690
 691         switch (aet) {
 692         case ESR_ELx_AET_CE:    /* corrected error */
 693         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 694                 /*
 695                  * The CPU can make progress. We may take UEO again as
 696                  * a more severe error.
 697                  */
 698                 return false;
 699
 700         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 701         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 702                 /*
 703                  * The CPU can't make progress. The exception may have
 704                  * been imprecise.
 705                  */
 706                 return true;
 707
 708         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 709         default:
 710                 /* Error has been silently propagated */
 711                 arm64_serror_panic(regs, esr);
 712         }
 713 }
 714
 715 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
 716 {
 717         nmi_enter();
 718
 719         /* non-RAS errors are not containable */
 720         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 721                 arm64_serror_panic(regs, esr);
 722
 723         nmi_exit();
 724 }
 725
 726 void __pte_error(const char *file, int line, unsigned long val)
 727 {
 728         pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
 729 }
 730
 731 void __pmd_error(const char *file, int line, unsigned long val)
 732 {
 733         pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
 734 }
 735
 736 void __pud_error(const char *file, int line, unsigned long val)
 737 {
 738         pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
 739 }
 740
 741 void __pgd_error(const char *file, int line, unsigned long val)
 742 {
 743         pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
 744 }
 745
 746 /* GENERIC_BUG traps */
 747
 748 int is_valid_bugaddr(unsigned long addr)
 749 {
 750         /*
 751          * bug_handler() only called for BRK #BUG_BRK_IMM.
 752          * So the answer is trivial -- any spurious instances with no
 753          * bug table entry will be rejected by report_bug() and passed
 754          * back to the debug-monitors code and handled as a fatal
 755          * unexpected debug exception.
 756          */
 757         return 1;
 758 }
 759
 760 static int bug_handler(struct pt_regs *regs, unsigned int esr)
 761 {
 762         if (user_mode(regs))
 763                 return DBG_HOOK_ERROR;
 764
 765         switch (report_bug(regs->pc, regs)) {
 766         case BUG_TRAP_TYPE_BUG:
 767                 die("Oops - BUG", regs, 0);
 768                 break;
 769
 770         case BUG_TRAP_TYPE_WARN:
 771                 break;
 772
 773         default:
 774                 /* unknown/unrecognised bug trap type */
 775                 return DBG_HOOK_ERROR;
 776         }
 777
 778         /* If thread survives, skip over the BUG instruction and continue: */
 779         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 780         return DBG_HOOK_HANDLED;
 781 }
 782
 783 static struct break_hook bug_break_hook = {
 784         .esr_val = 0xf2000000 | BUG_BRK_IMM,
 785         .esr_mask = 0xffffffff,
 786         .fn = bug_handler,
 787 };
 788
 789 /*
 790  * Initial handler for AArch64 BRK exceptions
 791  * This handler only used until debug_traps_init().
 792  */
 793 int __init early_brk64(unsigned long addr, unsigned int esr,
 794                 struct pt_regs *regs)
 795 {
 796         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
 797 }
 798
 799 /* This registration must happen early, before debug_traps_init(). */
 800 void __init trap_init(void)
 801 {
 802         register_break_hook(&bug_break_hook);
 803 }