arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/uaccess.h>
  26 #include <asm/kvm_arm.h>
  27 #include <asm/kvm_host.h>
  28 #include <asm/kvm_emulate.h>
  29 #include <asm/kvm_coproc.h>
  30 #include <asm/kvm_mmu.h>
  31 #include <asm/cacheflush.h>
  32 #include <asm/cputype.h>
  33 #include <asm/debug-monitors.h>
  34 #include <trace/events/kvm.h>
  35
  36 #include "sys_regs.h"
  37
  38 /*
  39  * All of this file is extremly similar to the ARM coproc.c, but the
  40  * types are different. My gut feeling is that it should be pretty
  41  * easy to merge, but that would be an ABI breakage -- again. VFP
  42  * would also need to be abstracted.
  43  *
  44  * For AArch32, we only take care of what is being trapped. Anything
  45  * that has to do with init and userspace access has to go via the
  46  * 64bit interface.
  47  */
  48
  49 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  50 static u32 cache_levels;
  51
  52 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  53 #define CSSELR_MAX 12
  54
  55 /* Which cache CCSIDR represents depends on CSSELR value. */
  56 static u32 get_ccsidr(u32 csselr)
  57 {
  58         u32 ccsidr;
  59
  60         /* Make sure noone else changes CSSELR during this! */
  61         local_irq_disable();
  62         /* Put value into CSSELR */
  63         asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
  64         isb();
  65         /* Read result out of CCSIDR */
  66         asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
  67         local_irq_enable();
  68
  69         return ccsidr;
  70 }
  71
  72 static void do_dc_cisw(u32 val)
  73 {
  74         asm volatile("dc cisw, %x0" : : "r" (val));
  75         dsb(ish);
  76 }
  77
  78 static void do_dc_csw(u32 val)
  79 {
  80         asm volatile("dc csw, %x0" : : "r" (val));
  81         dsb(ish);
  82 }
  83
  84 /* See note at ARM ARM B1.14.4 */
  85 static bool access_dcsw(struct kvm_vcpu *vcpu,
  86                         const struct sys_reg_params *p,
  87                         const struct sys_reg_desc *r)
  88 {
  89         unsigned long val;
  90         int cpu;
  91
  92         if (!p->is_write)
  93                 return read_from_write_only(vcpu, p);
  94
  95         cpu = get_cpu();
  96
  97         cpumask_setall(&vcpu->arch.require_dcache_flush);
  98         cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  99
 100         /* If we were already preempted, take the long way around */
 101         if (cpu != vcpu->arch.last_pcpu) {
 102                 flush_cache_all();
 103                 goto done;
 104         }
 105
 106         val = *vcpu_reg(vcpu, p->Rt);
 107
 108         switch (p->CRm) {
 109         case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
 110         case 14:                /* DCCISW */
 111                 do_dc_cisw(val);
 112                 break;
 113
 114         case 10:                /* DCCSW */
 115                 do_dc_csw(val);
 116                 break;
 117         }
 118
 119 done:
 120         put_cpu();
 121
 122         return true;
 123 }
 124
 125 /*
 126  * Generic accessor for VM registers. Only called as long as HCR_TVM
 127  * is set.
 128  */
 129 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 130                           const struct sys_reg_params *p,
 131                           const struct sys_reg_desc *r)
 132 {
 133         unsigned long val;
 134
 135         BUG_ON(!p->is_write);
 136
 137         val = *vcpu_reg(vcpu, p->Rt);
 138         if (!p->is_aarch32 || !p->is_32bit)
 139                 vcpu_sys_reg(vcpu, r->reg) = val;
 140         else
 141                 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
 142
 143         return true;
 144 }
 145
 146 /*
 147  * SCTLR_EL1 accessor. Only called as long as HCR_TVM is set.  If the
 148  * guest enables the MMU, we stop trapping the VM sys_regs and leave
 149  * it in complete control of the caches.
 150  */
 151 static bool access_sctlr(struct kvm_vcpu *vcpu,
 152                          const struct sys_reg_params *p,
 153                          const struct sys_reg_desc *r)
 154 {
 155         access_vm_reg(vcpu, p, r);
 156
 157         if (vcpu_has_cache_enabled(vcpu)) {     /* MMU+Caches enabled? */
 158                 vcpu->arch.hcr_el2 &= ~HCR_TVM;
 159                 stage2_flush_vm(vcpu->kvm);
 160         }
 161
 162         return true;
 163 }
 164
 165 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 166                         const struct sys_reg_params *p,
 167                         const struct sys_reg_desc *r)
 168 {
 169         if (p->is_write)
 170                 return ignore_write(vcpu, p);
 171         else
 172                 return read_zero(vcpu, p);
 173 }
 174
 175 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 176                            const struct sys_reg_params *p,
 177                            const struct sys_reg_desc *r)
 178 {
 179         if (p->is_write) {
 180                 return ignore_write(vcpu, p);
 181         } else {
 182                 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
 183                 return true;
 184         }
 185 }
 186
 187 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 188                                    const struct sys_reg_params *p,
 189                                    const struct sys_reg_desc *r)
 190 {
 191         if (p->is_write) {
 192                 return ignore_write(vcpu, p);
 193         } else {
 194                 u32 val;
 195                 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
 196                 *vcpu_reg(vcpu, p->Rt) = val;
 197                 return true;
 198         }
 199 }
 200
 201 /*
 202  * We want to avoid world-switching all the DBG registers all the
 203  * time:
 204  *
 205  * - If we've touched any debug register, it is likely that we're
 206  *   going to touch more of them. It then makes sense to disable the
 207  *   traps and start doing the save/restore dance
 208  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 209  *   then mandatory to save/restore the registers, as the guest
 210  *   depends on them.
 211  *
 212  * For this, we use a DIRTY bit, indicating the guest has modified the
 213  * debug registers, used as follow:
 214  *
 215  * On guest entry:
 216  * - If the dirty bit is set (because we're coming back from trapping),
 217  *   disable the traps, save host registers, restore guest registers.
 218  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 219  *   set the dirty bit, disable the traps, save host registers,
 220  *   restore guest registers.
 221  * - Otherwise, enable the traps
 222  *
 223  * On guest exit:
 224  * - If the dirty bit is set, save guest registers, restore host
 225  *   registers and clear the dirty bit. This ensure that the host can
 226  *   now use the debug registers.
 227  */
 228 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 229                             const struct sys_reg_params *p,
 230                             const struct sys_reg_desc *r)
 231 {
 232         if (p->is_write) {
 233                 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
 234                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 235         } else {
 236                 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
 237         }
 238
 239         return true;
 240 }
 241
 242 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 243 {
 244         u64 amair;
 245
 246         asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
 247         vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
 248 }
 249
 250 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 251 {
 252         /*
 253          * Simply map the vcpu_id into the Aff0 field of the MPIDR.
 254          */
 255         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
 256 }
 257
 258 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 259 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 260         /* DBGBVRn_EL1 */                                               \
 261         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 262           trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 },         \
 263         /* DBGBCRn_EL1 */                                               \
 264         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 265           trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 },         \
 266         /* DBGWVRn_EL1 */                                               \
 267         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 268           trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 },         \
 269         /* DBGWCRn_EL1 */                                               \
 270         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 271           trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
 272
 273 /*
 274  * Architected system registers.
 275  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 276  *
 277  * We could trap ID_DFR0 and tell the guest we don't support performance
 278  * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
 279  * NAKed, so it will read the PMCR anyway.
 280  *
 281  * Therefore we tell the guest we have 0 counters.  Unfortunately, we
 282  * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 283  * all PM registers, which doesn't crash the guest kernel at least.
 284  *
 285  * Debug handling: We do trap most, if not all debug related system
 286  * registers. The implementation is good enough to ensure that a guest
 287  * can use these with minimal performance degradation. The drawback is
 288  * that we don't implement any of the external debug, none of the
 289  * OSlock protocol. This should be revisited if we ever encounter a
 290  * more demanding guest...
 291  */
 292 static const struct sys_reg_desc sys_reg_descs[] = {
 293         /* DC ISW */
 294         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 295           access_dcsw },
 296         /* DC CSW */
 297         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 298           access_dcsw },
 299         /* DC CISW */
 300         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 301           access_dcsw },
 302
 303         DBG_BCR_BVR_WCR_WVR_EL1(0),
 304         DBG_BCR_BVR_WCR_WVR_EL1(1),
 305         /* MDCCINT_EL1 */
 306         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 307           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 308         /* MDSCR_EL1 */
 309         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 310           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 311         DBG_BCR_BVR_WCR_WVR_EL1(2),
 312         DBG_BCR_BVR_WCR_WVR_EL1(3),
 313         DBG_BCR_BVR_WCR_WVR_EL1(4),
 314         DBG_BCR_BVR_WCR_WVR_EL1(5),
 315         DBG_BCR_BVR_WCR_WVR_EL1(6),
 316         DBG_BCR_BVR_WCR_WVR_EL1(7),
 317         DBG_BCR_BVR_WCR_WVR_EL1(8),
 318         DBG_BCR_BVR_WCR_WVR_EL1(9),
 319         DBG_BCR_BVR_WCR_WVR_EL1(10),
 320         DBG_BCR_BVR_WCR_WVR_EL1(11),
 321         DBG_BCR_BVR_WCR_WVR_EL1(12),
 322         DBG_BCR_BVR_WCR_WVR_EL1(13),
 323         DBG_BCR_BVR_WCR_WVR_EL1(14),
 324         DBG_BCR_BVR_WCR_WVR_EL1(15),
 325
 326         /* MDRAR_EL1 */
 327         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 328           trap_raz_wi },
 329         /* OSLAR_EL1 */
 330         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 331           trap_raz_wi },
 332         /* OSLSR_EL1 */
 333         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 334           trap_oslsr_el1 },
 335         /* OSDLR_EL1 */
 336         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 337           trap_raz_wi },
 338         /* DBGPRCR_EL1 */
 339         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 340           trap_raz_wi },
 341         /* DBGCLAIMSET_EL1 */
 342         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 343           trap_raz_wi },
 344         /* DBGCLAIMCLR_EL1 */
 345         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 346           trap_raz_wi },
 347         /* DBGAUTHSTATUS_EL1 */
 348         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 349           trap_dbgauthstatus_el1 },
 350
 351         /* TEECR32_EL1 */
 352         { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 353           NULL, reset_val, TEECR32_EL1, 0 },
 354         /* TEEHBR32_EL1 */
 355         { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
 356           NULL, reset_val, TEEHBR32_EL1, 0 },
 357
 358         /* MDCCSR_EL1 */
 359         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 360           trap_raz_wi },
 361         /* DBGDTR_EL0 */
 362         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 363           trap_raz_wi },
 364         /* DBGDTR[TR]X_EL0 */
 365         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 366           trap_raz_wi },
 367
 368         /* DBGVCR32_EL2 */
 369         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 370           NULL, reset_val, DBGVCR32_EL2, 0 },
 371
 372         /* MPIDR_EL1 */
 373         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 374           NULL, reset_mpidr, MPIDR_EL1 },
 375         /* SCTLR_EL1 */
 376         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 377           access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },
 378         /* CPACR_EL1 */
 379         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 380           NULL, reset_val, CPACR_EL1, 0 },
 381         /* TTBR0_EL1 */
 382         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 383           access_vm_reg, reset_unknown, TTBR0_EL1 },
 384         /* TTBR1_EL1 */
 385         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 386           access_vm_reg, reset_unknown, TTBR1_EL1 },
 387         /* TCR_EL1 */
 388         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 389           access_vm_reg, reset_val, TCR_EL1, 0 },
 390
 391         /* AFSR0_EL1 */
 392         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 393           access_vm_reg, reset_unknown, AFSR0_EL1 },
 394         /* AFSR1_EL1 */
 395         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 396           access_vm_reg, reset_unknown, AFSR1_EL1 },
 397         /* ESR_EL1 */
 398         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 399           access_vm_reg, reset_unknown, ESR_EL1 },
 400         /* FAR_EL1 */
 401         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 402           access_vm_reg, reset_unknown, FAR_EL1 },
 403         /* PAR_EL1 */
 404         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 405           NULL, reset_unknown, PAR_EL1 },
 406
 407         /* PMINTENSET_EL1 */
 408         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 409           trap_raz_wi },
 410         /* PMINTENCLR_EL1 */
 411         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 412           trap_raz_wi },
 413
 414         /* MAIR_EL1 */
 415         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 416           access_vm_reg, reset_unknown, MAIR_EL1 },
 417         /* AMAIR_EL1 */
 418         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 419           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 420
 421         /* VBAR_EL1 */
 422         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 423           NULL, reset_val, VBAR_EL1, 0 },
 424         /* CONTEXTIDR_EL1 */
 425         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 426           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 427         /* TPIDR_EL1 */
 428         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 429           NULL, reset_unknown, TPIDR_EL1 },
 430
 431         /* CNTKCTL_EL1 */
 432         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 433           NULL, reset_val, CNTKCTL_EL1, 0},
 434
 435         /* CSSELR_EL1 */
 436         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 437           NULL, reset_unknown, CSSELR_EL1 },
 438
 439         /* PMCR_EL0 */
 440         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 441           trap_raz_wi },
 442         /* PMCNTENSET_EL0 */
 443         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 444           trap_raz_wi },
 445         /* PMCNTENCLR_EL0 */
 446         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 447           trap_raz_wi },
 448         /* PMOVSCLR_EL0 */
 449         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 450           trap_raz_wi },
 451         /* PMSWINC_EL0 */
 452         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
 453           trap_raz_wi },
 454         /* PMSELR_EL0 */
 455         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
 456           trap_raz_wi },
 457         /* PMCEID0_EL0 */
 458         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
 459           trap_raz_wi },
 460         /* PMCEID1_EL0 */
 461         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
 462           trap_raz_wi },
 463         /* PMCCNTR_EL0 */
 464         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
 465           trap_raz_wi },
 466         /* PMXEVTYPER_EL0 */
 467         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
 468           trap_raz_wi },
 469         /* PMXEVCNTR_EL0 */
 470         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 471           trap_raz_wi },
 472         /* PMUSERENR_EL0 */
 473         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 474           trap_raz_wi },
 475         /* PMOVSSET_EL0 */
 476         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
 477           trap_raz_wi },
 478
 479         /* TPIDR_EL0 */
 480         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
 481           NULL, reset_unknown, TPIDR_EL0 },
 482         /* TPIDRRO_EL0 */
 483         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 484           NULL, reset_unknown, TPIDRRO_EL0 },
 485
 486         /* DACR32_EL2 */
 487         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 488           NULL, reset_unknown, DACR32_EL2 },
 489         /* IFSR32_EL2 */
 490         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
 491           NULL, reset_unknown, IFSR32_EL2 },
 492         /* FPEXC32_EL2 */
 493         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
 494           NULL, reset_val, FPEXC32_EL2, 0x70 },
 495 };
 496
 497 /* Trapped cp14 registers */
 498 static const struct sys_reg_desc cp14_regs[] = {
 499 };
 500
 501 /*
 502  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 503  * depending on the way they are accessed (as a 32bit or a 64bit
 504  * register).
 505  */
 506 static const struct sys_reg_desc cp15_regs[] = {
 507         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 508         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
 509         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
 510         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
 511         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
 512         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
 513         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
 514         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
 515         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
 516         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
 517         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
 518         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
 519
 520         /*
 521          * DC{C,I,CI}SW operations:
 522          */
 523         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
 524         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
 525         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 526
 527         /* PMU */
 528         { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
 529         { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
 530         { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
 531         { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
 532         { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
 533         { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
 534         { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
 535         { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
 536         { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
 537         { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
 538         { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 539         { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
 540         { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
 541
 542         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
 543         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
 544         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
 545         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 546         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 547
 548         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
 549 };
 550
 551 /* Target specific emulation tables */
 552 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
 553
 554 void kvm_register_target_sys_reg_table(unsigned int target,
 555                                        struct kvm_sys_reg_target_table *table)
 556 {
 557         target_tables[target] = table;
 558 }
 559
 560 /* Get specific register table for this target. */
 561 static const struct sys_reg_desc *get_target_table(unsigned target,
 562                                                    bool mode_is_64,
 563                                                    size_t *num)
 564 {
 565         struct kvm_sys_reg_target_table *table;
 566
 567         table = target_tables[target];
 568         if (mode_is_64) {
 569                 *num = table->table64.num;
 570                 return table->table64.table;
 571         } else {
 572                 *num = table->table32.num;
 573                 return table->table32.table;
 574         }
 575 }
 576
 577 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
 578                                          const struct sys_reg_desc table[],
 579                                          unsigned int num)
 580 {
 581         unsigned int i;
 582
 583         for (i = 0; i < num; i++) {
 584                 const struct sys_reg_desc *r = &table[i];
 585
 586                 if (params->Op0 != r->Op0)
 587                         continue;
 588                 if (params->Op1 != r->Op1)
 589                         continue;
 590                 if (params->CRn != r->CRn)
 591                         continue;
 592                 if (params->CRm != r->CRm)
 593                         continue;
 594                 if (params->Op2 != r->Op2)
 595                         continue;
 596
 597                 return r;
 598         }
 599         return NULL;
 600 }
 601
 602 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 603 {
 604         kvm_inject_undefined(vcpu);
 605         return 1;
 606 }
 607
 608 /*
 609  * emulate_cp --  tries to match a sys_reg access in a handling table, and
 610  *                call the corresponding trap handler.
 611  *
 612  * @params: pointer to the descriptor of the access
 613  * @table: array of trap descriptors
 614  * @num: size of the trap descriptor array
 615  *
 616  * Return 0 if the access has been handled, and -1 if not.
 617  */
 618 static int emulate_cp(struct kvm_vcpu *vcpu,
 619                       const struct sys_reg_params *params,
 620                       const struct sys_reg_desc *table,
 621                       size_t num)
 622 {
 623         const struct sys_reg_desc *r;
 624
 625         if (!table)
 626                 return -1;      /* Not handled */
 627
 628         r = find_reg(params, table, num);
 629
 630         if (r) {
 631                 /*
 632                  * Not having an accessor means that we have
 633                  * configured a trap that we don't know how to
 634                  * handle. This certainly qualifies as a gross bug
 635                  * that should be fixed right away.
 636                  */
 637                 BUG_ON(!r->access);
 638
 639                 if (likely(r->access(vcpu, params, r))) {
 640                         /* Skip instruction, since it was emulated */
 641                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 642                 }
 643
 644                 /* Handled */
 645                 return 0;
 646         }
 647
 648         /* Not handled */
 649         return -1;
 650 }
 651
 652 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
 653                                 struct sys_reg_params *params)
 654 {
 655         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
 656         int cp;
 657
 658         switch(hsr_ec) {
 659         case ESR_EL2_EC_CP15_32:
 660         case ESR_EL2_EC_CP15_64:
 661                 cp = 15;
 662                 break;
 663         case ESR_EL2_EC_CP14_MR:
 664         case ESR_EL2_EC_CP14_64:
 665                 cp = 14;
 666                 break;
 667         default:
 668                 WARN_ON((cp = -1));
 669         }
 670
 671         kvm_err("Unsupported guest CP%d access at: %08lx\n",
 672                 cp, *vcpu_pc(vcpu));
 673         print_sys_reg_instr(params);
 674         kvm_inject_undefined(vcpu);
 675 }
 676
 677 /**
 678  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 679  * @vcpu: The VCPU pointer
 680  * @run:  The kvm_run struct
 681  */
 682 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
 683                             const struct sys_reg_desc *global,
 684                             size_t nr_global,
 685                             const struct sys_reg_desc *target_specific,
 686                             size_t nr_specific)
 687 {
 688         struct sys_reg_params params;
 689         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 690         int Rt2 = (hsr >> 10) & 0xf;
 691
 692         params.is_aarch32 = true;
 693         params.is_32bit = false;
 694         params.CRm = (hsr >> 1) & 0xf;
 695         params.Rt = (hsr >> 5) & 0xf;
 696         params.is_write = ((hsr & 1) == 0);
 697
 698         params.Op0 = 0;
 699         params.Op1 = (hsr >> 16) & 0xf;
 700         params.Op2 = 0;
 701         params.CRn = 0;
 702
 703         /*
 704          * Massive hack here. Store Rt2 in the top 32bits so we only
 705          * have one register to deal with. As we use the same trap
 706          * backends between AArch32 and AArch64, we get away with it.
 707          */
 708         if (params.is_write) {
 709                 u64 val = *vcpu_reg(vcpu, params.Rt);
 710                 val &= 0xffffffff;
 711                 val |= *vcpu_reg(vcpu, Rt2) << 32;
 712                 *vcpu_reg(vcpu, params.Rt) = val;
 713         }
 714
 715         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 716                 goto out;
 717         if (!emulate_cp(vcpu, &params, global, nr_global))
 718                 goto out;
 719
 720         unhandled_cp_access(vcpu, &params);
 721
 722 out:
 723         /* Do the opposite hack for the read side */
 724         if (!params.is_write) {
 725                 u64 val = *vcpu_reg(vcpu, params.Rt);
 726                 val >>= 32;
 727                 *vcpu_reg(vcpu, Rt2) = val;
 728         }
 729
 730         return 1;
 731 }
 732
 733 /**
 734  * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 735  * @vcpu: The VCPU pointer
 736  * @run:  The kvm_run struct
 737  */
 738 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
 739                             const struct sys_reg_desc *global,
 740                             size_t nr_global,
 741                             const struct sys_reg_desc *target_specific,
 742                             size_t nr_specific)
 743 {
 744         struct sys_reg_params params;
 745         u32 hsr = kvm_vcpu_get_hsr(vcpu);
 746
 747         params.is_aarch32 = true;
 748         params.is_32bit = true;
 749         params.CRm = (hsr >> 1) & 0xf;
 750         params.Rt  = (hsr >> 5) & 0xf;
 751         params.is_write = ((hsr & 1) == 0);
 752         params.CRn = (hsr >> 10) & 0xf;
 753         params.Op0 = 0;
 754         params.Op1 = (hsr >> 14) & 0x7;
 755         params.Op2 = (hsr >> 17) & 0x7;
 756
 757         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
 758                 return 1;
 759         if (!emulate_cp(vcpu, &params, global, nr_global))
 760                 return 1;
 761
 762         unhandled_cp_access(vcpu, &params);
 763         return 1;
 764 }
 765
 766 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 767 {
 768         const struct sys_reg_desc *target_specific;
 769         size_t num;
 770
 771         target_specific = get_target_table(vcpu->arch.target, false, &num);
 772         return kvm_handle_cp_64(vcpu,
 773                                 cp15_regs, ARRAY_SIZE(cp15_regs),
 774                                 target_specific, num);
 775 }
 776
 777 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 778 {
 779         const struct sys_reg_desc *target_specific;
 780         size_t num;
 781
 782         target_specific = get_target_table(vcpu->arch.target, false, &num);
 783         return kvm_handle_cp_32(vcpu,
 784                                 cp15_regs, ARRAY_SIZE(cp15_regs),
 785                                 target_specific, num);
 786 }
 787
 788 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 789 {
 790         return kvm_handle_cp_64(vcpu,
 791                                 cp14_regs, ARRAY_SIZE(cp14_regs),
 792                                 NULL, 0);
 793 }
 794
 795 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 796 {
 797         return kvm_handle_cp_32(vcpu,
 798                                 cp14_regs, ARRAY_SIZE(cp14_regs),
 799                                 NULL, 0);
 800 }
 801
 802 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
 803                            const struct sys_reg_params *params)
 804 {
 805         size_t num;
 806         const struct sys_reg_desc *table, *r;
 807
 808         table = get_target_table(vcpu->arch.target, true, &num);
 809
 810         /* Search target-specific then generic table. */
 811         r = find_reg(params, table, num);
 812         if (!r)
 813                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 814
 815         if (likely(r)) {
 816                 /*
 817                  * Not having an accessor means that we have
 818                  * configured a trap that we don't know how to
 819                  * handle. This certainly qualifies as a gross bug
 820                  * that should be fixed right away.
 821                  */
 822                 BUG_ON(!r->access);
 823
 824                 if (likely(r->access(vcpu, params, r))) {
 825                         /* Skip instruction, since it was emulated */
 826                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 827                         return 1;
 828                 }
 829                 /* If access function fails, it should complain. */
 830         } else {
 831                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
 832                         *vcpu_pc(vcpu));
 833                 print_sys_reg_instr(params);
 834         }
 835         kvm_inject_undefined(vcpu);
 836         return 1;
 837 }
 838
 839 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
 840                               const struct sys_reg_desc *table, size_t num)
 841 {
 842         unsigned long i;
 843
 844         for (i = 0; i < num; i++)
 845                 if (table[i].reset)
 846                         table[i].reset(vcpu, &table[i]);
 847 }
 848
 849 /**
 850  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
 851  * @vcpu: The VCPU pointer
 852  * @run:  The kvm_run struct
 853  */
 854 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
 855 {
 856         struct sys_reg_params params;
 857         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
 858
 859         params.is_aarch32 = false;
 860         params.is_32bit = false;
 861         params.Op0 = (esr >> 20) & 3;
 862         params.Op1 = (esr >> 14) & 0x7;
 863         params.CRn = (esr >> 10) & 0xf;
 864         params.CRm = (esr >> 1) & 0xf;
 865         params.Op2 = (esr >> 17) & 0x7;
 866         params.Rt = (esr >> 5) & 0x1f;
 867         params.is_write = !(esr & 1);
 868
 869         return emulate_sys_reg(vcpu, &params);
 870 }
 871
 872 /******************************************************************************
 873  * Userspace API
 874  *****************************************************************************/
 875
 876 static bool index_to_params(u64 id, struct sys_reg_params *params)
 877 {
 878         switch (id & KVM_REG_SIZE_MASK) {
 879         case KVM_REG_SIZE_U64:
 880                 /* Any unused index bits means it's not valid. */
 881                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
 882                               | KVM_REG_ARM_COPROC_MASK
 883                               | KVM_REG_ARM64_SYSREG_OP0_MASK
 884                               | KVM_REG_ARM64_SYSREG_OP1_MASK
 885                               | KVM_REG_ARM64_SYSREG_CRN_MASK
 886                               | KVM_REG_ARM64_SYSREG_CRM_MASK
 887                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
 888                         return false;
 889                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
 890                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
 891                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
 892                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
 893                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
 894                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
 895                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
 896                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
 897                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
 898                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
 899                 return true;
 900         default:
 901                 return false;
 902         }
 903 }
 904
 905 /* Decode an index value, and find the sys_reg_desc entry. */
 906 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
 907                                                     u64 id)
 908 {
 909         size_t num;
 910         const struct sys_reg_desc *table, *r;
 911         struct sys_reg_params params;
 912
 913         /* We only do sys_reg for now. */
 914         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
 915                 return NULL;
 916
 917         if (!index_to_params(id, &params))
 918                 return NULL;
 919
 920         table = get_target_table(vcpu->arch.target, true, &num);
 921         r = find_reg(&params, table, num);
 922         if (!r)
 923                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 924
 925         /* Not saved in the sys_reg array? */
 926         if (r && !r->reg)
 927                 r = NULL;
 928
 929         return r;
 930 }
 931
 932 /*
 933  * These are the invariant sys_reg registers: we let the guest see the
 934  * host versions of these, so they're part of the guest state.
 935  *
 936  * A future CPU may provide a mechanism to present different values to
 937  * the guest, or a future kvm may trap them.
 938  */
 939
 940 #define FUNCTION_INVARIANT(reg)                                         \
 941         static void get_##reg(struct kvm_vcpu *v,                       \
 942                               const struct sys_reg_desc *r)             \
 943         {                                                               \
 944                 u64 val;                                                \
 945                                                                         \
 946                 asm volatile("mrs %0, " __stringify(reg) "\n"           \
 947                              : "=r" (val));                             \
 948                 ((struct sys_reg_desc *)r)->val = val;                  \
 949         }
 950
 951 FUNCTION_INVARIANT(midr_el1)
 952 FUNCTION_INVARIANT(ctr_el0)
 953 FUNCTION_INVARIANT(revidr_el1)
 954 FUNCTION_INVARIANT(id_pfr0_el1)
 955 FUNCTION_INVARIANT(id_pfr1_el1)
 956 FUNCTION_INVARIANT(id_dfr0_el1)
 957 FUNCTION_INVARIANT(id_afr0_el1)
 958 FUNCTION_INVARIANT(id_mmfr0_el1)
 959 FUNCTION_INVARIANT(id_mmfr1_el1)
 960 FUNCTION_INVARIANT(id_mmfr2_el1)
 961 FUNCTION_INVARIANT(id_mmfr3_el1)
 962 FUNCTION_INVARIANT(id_isar0_el1)
 963 FUNCTION_INVARIANT(id_isar1_el1)
 964 FUNCTION_INVARIANT(id_isar2_el1)
 965 FUNCTION_INVARIANT(id_isar3_el1)
 966 FUNCTION_INVARIANT(id_isar4_el1)
 967 FUNCTION_INVARIANT(id_isar5_el1)
 968 FUNCTION_INVARIANT(clidr_el1)
 969 FUNCTION_INVARIANT(aidr_el1)
 970
 971 /* ->val is filled in by kvm_sys_reg_table_init() */
 972 static struct sys_reg_desc invariant_sys_regs[] = {
 973         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
 974           NULL, get_midr_el1 },
 975         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
 976           NULL, get_revidr_el1 },
 977         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
 978           NULL, get_id_pfr0_el1 },
 979         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
 980           NULL, get_id_pfr1_el1 },
 981         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
 982           NULL, get_id_dfr0_el1 },
 983         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
 984           NULL, get_id_afr0_el1 },
 985         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
 986           NULL, get_id_mmfr0_el1 },
 987         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
 988           NULL, get_id_mmfr1_el1 },
 989         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
 990           NULL, get_id_mmfr2_el1 },
 991         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
 992           NULL, get_id_mmfr3_el1 },
 993         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 994           NULL, get_id_isar0_el1 },
 995         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
 996           NULL, get_id_isar1_el1 },
 997         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 998           NULL, get_id_isar2_el1 },
 999         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1000           NULL, get_id_isar3_el1 },
1001         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1002           NULL, get_id_isar4_el1 },
1003         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1004           NULL, get_id_isar5_el1 },
1005         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1006           NULL, get_clidr_el1 },
1007         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1008           NULL, get_aidr_el1 },
1009         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1010           NULL, get_ctr_el0 },
1011 };
1012
1013 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1014 {
1015         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1016                 return -EFAULT;
1017         return 0;
1018 }
1019
1020 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1021 {
1022         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1023                 return -EFAULT;
1024         return 0;
1025 }
1026
1027 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1028 {
1029         struct sys_reg_params params;
1030         const struct sys_reg_desc *r;
1031
1032         if (!index_to_params(id, &params))
1033                 return -ENOENT;
1034
1035         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1036         if (!r)
1037                 return -ENOENT;
1038
1039         return reg_to_user(uaddr, &r->val, id);
1040 }
1041
1042 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1043 {
1044         struct sys_reg_params params;
1045         const struct sys_reg_desc *r;
1046         int err;
1047         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1048
1049         if (!index_to_params(id, &params))
1050                 return -ENOENT;
1051         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1052         if (!r)
1053                 return -ENOENT;
1054
1055         err = reg_from_user(&val, uaddr, id);
1056         if (err)
1057                 return err;
1058
1059         /* This is what we mean by invariant: you can't change it. */
1060         if (r->val != val)
1061                 return -EINVAL;
1062
1063         return 0;
1064 }
1065
1066 static bool is_valid_cache(u32 val)
1067 {
1068         u32 level, ctype;
1069
1070         if (val >= CSSELR_MAX)
1071                 return -ENOENT;
1072
1073         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1074         level = (val >> 1);
1075         ctype = (cache_levels >> (level * 3)) & 7;
1076
1077         switch (ctype) {
1078         case 0: /* No cache */
1079                 return false;
1080         case 1: /* Instruction cache only */
1081                 return (val & 1);
1082         case 2: /* Data cache only */
1083         case 4: /* Unified cache */
1084                 return !(val & 1);
1085         case 3: /* Separate instruction and data caches */
1086                 return true;
1087         default: /* Reserved: we can't know instruction or data. */
1088                 return false;
1089         }
1090 }
1091
1092 static int demux_c15_get(u64 id, void __user *uaddr)
1093 {
1094         u32 val;
1095         u32 __user *uval = uaddr;
1096
1097         /* Fail if we have unknown bits set. */
1098         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1099                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1100                 return -ENOENT;
1101
1102         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1103         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1104                 if (KVM_REG_SIZE(id) != 4)
1105                         return -ENOENT;
1106                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1107                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1108                 if (!is_valid_cache(val))
1109                         return -ENOENT;
1110
1111                 return put_user(get_ccsidr(val), uval);
1112         default:
1113                 return -ENOENT;
1114         }
1115 }
1116
1117 static int demux_c15_set(u64 id, void __user *uaddr)
1118 {
1119         u32 val, newval;
1120         u32 __user *uval = uaddr;
1121
1122         /* Fail if we have unknown bits set. */
1123         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1124                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1125                 return -ENOENT;
1126
1127         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1128         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1129                 if (KVM_REG_SIZE(id) != 4)
1130                         return -ENOENT;
1131                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1132                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1133                 if (!is_valid_cache(val))
1134                         return -ENOENT;
1135
1136                 if (get_user(newval, uval))
1137                         return -EFAULT;
1138
1139                 /* This is also invariant: you can't change it. */
1140                 if (newval != get_ccsidr(val))
1141                         return -EINVAL;
1142                 return 0;
1143         default:
1144                 return -ENOENT;
1145         }
1146 }
1147
1148 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1149 {
1150         const struct sys_reg_desc *r;
1151         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1152
1153         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1154                 return demux_c15_get(reg->id, uaddr);
1155
1156         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1157                 return -ENOENT;
1158
1159         r = index_to_sys_reg_desc(vcpu, reg->id);
1160         if (!r)
1161                 return get_invariant_sys_reg(reg->id, uaddr);
1162
1163         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1164 }
1165
1166 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1167 {
1168         const struct sys_reg_desc *r;
1169         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1170
1171         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1172                 return demux_c15_set(reg->id, uaddr);
1173
1174         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1175                 return -ENOENT;
1176
1177         r = index_to_sys_reg_desc(vcpu, reg->id);
1178         if (!r)
1179                 return set_invariant_sys_reg(reg->id, uaddr);
1180
1181         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1182 }
1183
1184 static unsigned int num_demux_regs(void)
1185 {
1186         unsigned int i, count = 0;
1187
1188         for (i = 0; i < CSSELR_MAX; i++)
1189                 if (is_valid_cache(i))
1190                         count++;
1191
1192         return count;
1193 }
1194
1195 static int write_demux_regids(u64 __user *uindices)
1196 {
1197         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1198         unsigned int i;
1199
1200         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1201         for (i = 0; i < CSSELR_MAX; i++) {
1202                 if (!is_valid_cache(i))
1203                         continue;
1204                 if (put_user(val | i, uindices))
1205                         return -EFAULT;
1206                 uindices++;
1207         }
1208         return 0;
1209 }
1210
1211 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1212 {
1213         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1214                 KVM_REG_ARM64_SYSREG |
1215                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1216                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1217                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1218                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1219                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1220 }
1221
1222 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1223 {
1224         if (!*uind)
1225                 return true;
1226
1227         if (put_user(sys_reg_to_index(reg), *uind))
1228                 return false;
1229
1230         (*uind)++;
1231         return true;
1232 }
1233
1234 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1235 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1236 {
1237         const struct sys_reg_desc *i1, *i2, *end1, *end2;
1238         unsigned int total = 0;
1239         size_t num;
1240
1241         /* We check for duplicates here, to allow arch-specific overrides. */
1242         i1 = get_target_table(vcpu->arch.target, true, &num);
1243         end1 = i1 + num;
1244         i2 = sys_reg_descs;
1245         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1246
1247         BUG_ON(i1 == end1 || i2 == end2);
1248
1249         /* Walk carefully, as both tables may refer to the same register. */
1250         while (i1 || i2) {
1251                 int cmp = cmp_sys_reg(i1, i2);
1252                 /* target-specific overrides generic entry. */
1253                 if (cmp <= 0) {
1254                         /* Ignore registers we trap but don't save. */
1255                         if (i1->reg) {
1256                                 if (!copy_reg_to_user(i1, &uind))
1257                                         return -EFAULT;
1258                                 total++;
1259                         }
1260                 } else {
1261                         /* Ignore registers we trap but don't save. */
1262                         if (i2->reg) {
1263                                 if (!copy_reg_to_user(i2, &uind))
1264                                         return -EFAULT;
1265                                 total++;
1266                         }
1267                 }
1268
1269                 if (cmp <= 0 && ++i1 == end1)
1270                         i1 = NULL;
1271                 if (cmp >= 0 && ++i2 == end2)
1272                         i2 = NULL;
1273         }
1274         return total;
1275 }
1276
1277 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1278 {
1279         return ARRAY_SIZE(invariant_sys_regs)
1280                 + num_demux_regs()
1281                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1282 }
1283
1284 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1285 {
1286         unsigned int i;
1287         int err;
1288
1289         /* Then give them all the invariant registers' indices. */
1290         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1291                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1292                         return -EFAULT;
1293                 uindices++;
1294         }
1295
1296         err = walk_sys_regs(vcpu, uindices);
1297         if (err < 0)
1298                 return err;
1299         uindices += err;
1300
1301         return write_demux_regids(uindices);
1302 }
1303
1304 void kvm_sys_reg_table_init(void)
1305 {
1306         unsigned int i;
1307         struct sys_reg_desc clidr;
1308
1309         /* Make sure tables are unique and in order. */
1310         for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++)
1311                 BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >= 0);
1312
1313         /* We abuse the reset function to overwrite the table itself. */
1314         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1315                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1316
1317         /*
1318          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
1319          *
1320          *   If software reads the Cache Type fields from Ctype1
1321          *   upwards, once it has seen a value of 0b000, no caches
1322          *   exist at further-out levels of the hierarchy. So, for
1323          *   example, if Ctype3 is the first Cache Type field with a
1324          *   value of 0b000, the values of Ctype4 to Ctype7 must be
1325          *   ignored.
1326          */
1327         get_clidr_el1(NULL, &clidr); /* Ugly... */
1328         cache_levels = clidr.val;
1329         for (i = 0; i < 7; i++)
1330                 if (((cache_levels >> (i*3)) & 7) == 0)
1331                         break;
1332         /* Clear all higher bits. */
1333         cache_levels &= (1 << (i*3))-1;
1334 }
1335
1336 /**
1337  * kvm_reset_sys_regs - sets system registers to reset value
1338  * @vcpu: The VCPU pointer
1339  *
1340  * This function finds the right table above and sets the registers on the
1341  * virtual CPU struct to their architecturally defined reset values.
1342  */
1343 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1344 {
1345         size_t num;
1346         const struct sys_reg_desc *table;
1347
1348         /* Catch someone adding a register without putting in reset entry. */
1349         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1350
1351         /* Generic chip reset first (so target could override). */
1352         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1353
1354         table = get_target_table(vcpu->arch.target, true, &num);
1355         reset_sys_reg_descs(vcpu, table, num);
1356
1357         for (num = 1; num < NR_SYS_REGS; num++)
1358                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1359                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
1360 }