2 * Set up the interrupt priorities
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
11 * Licensed under the GPL-2
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #include <linux/syscore_ops.h>
20 #include <asm/delay.h>
22 #include <linux/ipipe.h>
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
27 #include <asm/irq_handler.h>
31 # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
33 # define SIC_SYSIRQ(irq) ((irq) - IVG15)
38 * - we have separated the physical Hardware interrupt from the
39 * levels that the LINUX kernel sees (see the description in irq.h)
44 /* Initialize this to an actual value to force it into the .data
45 * section so that we know it is properly initialized at entry into
46 * the kernel but before bss is initialized to zero (which is where
47 * it would live otherwise). The 0x1f magic represents the IRQs we
48 * cannot actually mask out in hardware.
50 unsigned long bfin_irq_flags = 0x1f;
51 EXPORT_SYMBOL(bfin_irq_flags);
55 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
61 /* irq number for request_irq, available in mach-bf5xx/irq.h */
63 /* corresponding bit in the SIC_ISR register */
65 } ivg_table[NR_PERI_INTS];
67 static struct ivg_slice {
68 /* position of first irq in ivg_table for given ivg */
71 } ivg7_13[IVG13 - IVG7 + 1];
75 * Search SIC_IAR and fill tables with the irqvalues
76 * and their positions in the SIC_ISR register.
78 static void __init search_IAR(void)
80 unsigned ivg, irq_pos = 0;
81 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
84 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
86 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
89 bfin_read32((unsigned long *)SIC_IAR0 +
90 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
91 defined(CONFIG_BF538) || defined(CONFIG_BF539)
92 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
97 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
98 int iar_shift = (irqn & 7) * 4;
99 if (ivg == (0xf & (iar >> iar_shift))) {
100 ivg_table[irq_pos].irqno = IVG7 + irqn;
101 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
102 ivg7_13[ivg].istop++;
112 * This is for core internal IRQs
114 void bfin_ack_noop(struct irq_data *d)
116 /* Dummy function. */
119 static void bfin_core_mask_irq(struct irq_data *d)
121 bfin_irq_flags &= ~(1 << d->irq);
122 if (!hard_irqs_disabled())
123 hard_local_irq_enable();
126 static void bfin_core_unmask_irq(struct irq_data *d)
128 bfin_irq_flags |= 1 << d->irq;
130 * If interrupts are enabled, IMASK must contain the same value
131 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
132 * are currently disabled we need not do anything; one of the
133 * callers will take care of setting IMASK to the proper value
134 * when reenabling interrupts.
135 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
138 if (!hard_irqs_disabled())
139 hard_local_irq_enable();
143 void bfin_internal_mask_irq(unsigned int irq)
145 unsigned long flags = hard_local_irq_save();
148 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
149 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
152 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
153 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
158 ~(1 << SIC_SYSIRQ(irq)));
159 #endif /* end of SIC_IMASK0 */
161 hard_local_irq_restore(flags);
164 static void bfin_internal_mask_irq_chip(struct irq_data *d)
166 bfin_internal_mask_irq(d->irq);
170 void bfin_internal_unmask_irq_affinity(unsigned int irq,
171 const struct cpumask *affinity)
173 void bfin_internal_unmask_irq(unsigned int irq)
176 unsigned long flags = hard_local_irq_save();
180 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
181 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
183 if (cpumask_test_cpu(0, affinity))
185 bfin_write_SIC_IMASK(mask_bank,
186 bfin_read_SIC_IMASK(mask_bank) |
189 if (cpumask_test_cpu(1, affinity))
190 bfin_write_SICB_IMASK(mask_bank,
191 bfin_read_SICB_IMASK(mask_bank) |
195 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
196 (1 << SIC_SYSIRQ(irq)));
199 hard_local_irq_restore(flags);
203 static void bfin_sec_preflow_handler(struct irq_data *d)
205 unsigned long flags = hard_local_irq_save();
206 unsigned int sid = SIC_SYSIRQ(d->irq);
208 bfin_write_SEC_SCI(0, SEC_CSID, sid);
210 hard_local_irq_restore(flags);
213 static void bfin_sec_mask_ack_irq(struct irq_data *d)
215 unsigned long flags = hard_local_irq_save();
216 unsigned int sid = SIC_SYSIRQ(d->irq);
218 bfin_write_SEC_SCI(0, SEC_CSID, sid);
220 hard_local_irq_restore(flags);
223 static void bfin_sec_unmask_irq(struct irq_data *d)
225 unsigned long flags = hard_local_irq_save();
226 unsigned int sid = SIC_SYSIRQ(d->irq);
228 bfin_write32(SEC_END, sid);
230 hard_local_irq_restore(flags);
233 static void bfin_sec_enable_ssi(unsigned int sid)
235 unsigned long flags = hard_local_irq_save();
236 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
238 reg_sctl |= SEC_SCTL_SRC_EN;
239 bfin_write_SEC_SCTL(sid, reg_sctl);
241 hard_local_irq_restore(flags);
244 static void bfin_sec_disable_ssi(unsigned int sid)
246 unsigned long flags = hard_local_irq_save();
247 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
249 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
250 bfin_write_SEC_SCTL(sid, reg_sctl);
252 hard_local_irq_restore(flags);
255 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
257 unsigned long flags = hard_local_irq_save();
258 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
260 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
261 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
263 hard_local_irq_restore(flags);
266 static void bfin_sec_enable_sci(unsigned int sid)
268 unsigned long flags = hard_local_irq_save();
269 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
271 if (sid == SIC_SYSIRQ(IRQ_WATCH0))
272 reg_sctl |= SEC_SCTL_FAULT_EN;
274 reg_sctl |= SEC_SCTL_INT_EN;
275 bfin_write_SEC_SCTL(sid, reg_sctl);
277 hard_local_irq_restore(flags);
280 static void bfin_sec_disable_sci(unsigned int sid)
282 unsigned long flags = hard_local_irq_save();
283 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
285 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
286 bfin_write_SEC_SCTL(sid, reg_sctl);
288 hard_local_irq_restore(flags);
291 static void bfin_sec_enable(struct irq_data *d)
293 unsigned long flags = hard_local_irq_save();
294 unsigned int sid = SIC_SYSIRQ(d->irq);
296 bfin_sec_enable_sci(sid);
297 bfin_sec_enable_ssi(sid);
299 hard_local_irq_restore(flags);
302 static void bfin_sec_disable(struct irq_data *d)
304 unsigned long flags = hard_local_irq_save();
305 unsigned int sid = SIC_SYSIRQ(d->irq);
307 bfin_sec_disable_sci(sid);
308 bfin_sec_disable_ssi(sid);
310 hard_local_irq_restore(flags);
313 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
315 unsigned long flags = hard_local_irq_save();
319 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
321 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
322 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
323 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
324 bfin_write_SEC_SCTL(i, reg_sctl);
327 hard_local_irq_restore(flags);
330 static void bfin_sec_raise_irq(unsigned int sid)
332 unsigned long flags = hard_local_irq_save();
334 bfin_write32(SEC_RAISE, sid);
336 hard_local_irq_restore(flags);
339 static void init_software_driven_irq(void)
341 bfin_sec_set_ssi_coreid(34, 0);
342 bfin_sec_set_ssi_coreid(35, 1);
343 bfin_sec_set_ssi_coreid(36, 0);
344 bfin_sec_set_ssi_coreid(37, 1);
347 void bfin_sec_resume(void)
349 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
351 bfin_write_SEC_GCTL(SEC_GCTL_EN);
352 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
355 void handle_sec_sfi_fault(uint32_t gstat)
360 void handle_sec_sci_fault(uint32_t gstat)
365 core_id = gstat & SEC_GSTAT_SCI;
366 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
367 if (cstat & SEC_CSTAT_ERR) {
368 switch (cstat & SEC_CSTAT_ERRC) {
369 case SEC_CSTAT_ACKERR:
370 printk(KERN_DEBUG "sec ack err\n");
373 printk(KERN_DEBUG "sec sci unknow err\n");
379 void handle_sec_ssi_fault(uint32_t gstat)
384 sid = gstat & SEC_GSTAT_SID;
385 sstat = bfin_read_SEC_SSTAT(sid);
389 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
393 raw_spin_lock(&desc->lock);
395 sec_gstat = bfin_read32(SEC_GSTAT);
396 if (sec_gstat & SEC_GSTAT_ERR) {
398 switch (sec_gstat & SEC_GSTAT_ERRC) {
400 handle_sec_sfi_fault(sec_gstat);
402 case SEC_GSTAT_SCIERR:
403 handle_sec_sci_fault(sec_gstat);
405 case SEC_GSTAT_SSIERR:
406 handle_sec_ssi_fault(sec_gstat);
413 raw_spin_unlock(&desc->lock);
419 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
421 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
424 static int bfin_internal_set_affinity(struct irq_data *d,
425 const struct cpumask *mask, bool force)
427 bfin_internal_mask_irq(d->irq);
428 bfin_internal_unmask_irq_affinity(d->irq, mask);
433 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
435 bfin_internal_unmask_irq(d->irq);
439 #if defined(CONFIG_PM) && !defined(SEC_GCTL)
440 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
442 u32 bank, bit, wakeup = 0;
444 bank = SIC_SYSIRQ(irq) / 32;
445 bit = SIC_SYSIRQ(irq) % 32;
477 flags = hard_local_irq_save();
480 bfin_sic_iwr[bank] |= (1 << bit);
484 bfin_sic_iwr[bank] &= ~(1 << bit);
485 vr_wakeup &= ~wakeup;
488 hard_local_irq_restore(flags);
493 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
495 return bfin_internal_set_wake(d->irq, state);
498 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
502 # define bfin_internal_set_wake_chip NULL
505 static struct irq_chip bfin_core_irqchip = {
507 .irq_mask = bfin_core_mask_irq,
508 .irq_unmask = bfin_core_unmask_irq,
511 static struct irq_chip bfin_internal_irqchip = {
513 .irq_mask = bfin_internal_mask_irq_chip,
514 .irq_unmask = bfin_internal_unmask_irq_chip,
515 .irq_disable = bfin_internal_mask_irq_chip,
516 .irq_enable = bfin_internal_unmask_irq_chip,
518 .irq_set_affinity = bfin_internal_set_affinity,
520 .irq_set_wake = bfin_internal_set_wake_chip,
524 static struct irq_chip bfin_sec_irqchip = {
526 .irq_mask_ack = bfin_sec_mask_ack_irq,
527 .irq_mask = bfin_sec_mask_ack_irq,
528 .irq_unmask = bfin_sec_unmask_irq,
529 .irq_eoi = bfin_sec_unmask_irq,
530 .irq_disable = bfin_sec_disable,
531 .irq_enable = bfin_sec_enable,
535 void bfin_handle_irq(unsigned irq)
538 struct pt_regs regs; /* Contents not used. */
539 ipipe_trace_irq_entry(irq);
540 __ipipe_handle_irq(irq, ®s);
541 ipipe_trace_irq_exit(irq);
542 #else /* !CONFIG_IPIPE */
543 generic_handle_irq(irq);
544 #endif /* !CONFIG_IPIPE */
547 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
548 static int mac_stat_int_mask;
550 static void bfin_mac_status_ack_irq(unsigned int irq)
554 bfin_write_EMAC_MMC_TIRQS(
555 bfin_read_EMAC_MMC_TIRQE() &
556 bfin_read_EMAC_MMC_TIRQS());
557 bfin_write_EMAC_MMC_RIRQS(
558 bfin_read_EMAC_MMC_RIRQE() &
559 bfin_read_EMAC_MMC_RIRQS());
561 case IRQ_MAC_RXFSINT:
562 bfin_write_EMAC_RX_STKY(
563 bfin_read_EMAC_RX_IRQE() &
564 bfin_read_EMAC_RX_STKY());
566 case IRQ_MAC_TXFSINT:
567 bfin_write_EMAC_TX_STKY(
568 bfin_read_EMAC_TX_IRQE() &
569 bfin_read_EMAC_TX_STKY());
571 case IRQ_MAC_WAKEDET:
572 bfin_write_EMAC_WKUP_CTL(
573 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
576 /* These bits are W1C */
577 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
582 static void bfin_mac_status_mask_irq(struct irq_data *d)
584 unsigned int irq = d->irq;
586 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
590 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
596 if (!mac_stat_int_mask)
597 bfin_internal_mask_irq(IRQ_MAC_ERROR);
599 bfin_mac_status_ack_irq(irq);
602 static void bfin_mac_status_unmask_irq(struct irq_data *d)
604 unsigned int irq = d->irq;
609 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
615 if (!mac_stat_int_mask)
616 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
618 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
622 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
625 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
627 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
631 # define bfin_mac_status_set_wake NULL
634 static struct irq_chip bfin_mac_status_irqchip = {
636 .irq_mask = bfin_mac_status_mask_irq,
637 .irq_unmask = bfin_mac_status_unmask_irq,
638 .irq_set_wake = bfin_mac_status_set_wake,
641 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
642 struct irq_desc *inta_desc)
645 u32 status = bfin_read_EMAC_SYSTAT();
647 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
648 if (status & (1L << i)) {
649 irq = IRQ_MAC_PHYINT + i;
654 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
655 bfin_handle_irq(irq);
657 bfin_mac_status_ack_irq(irq);
659 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
664 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
665 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
666 "(EMAC_SYSTAT=0x%X)\n",
667 __func__, __FILE__, __LINE__, status);
671 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
674 handle = handle_level_irq;
676 __irq_set_handler_locked(irq, handle);
679 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
680 extern void bfin_gpio_irq_prepare(unsigned gpio);
684 static void bfin_gpio_ack_irq(struct irq_data *d)
686 /* AFAIK ack_irq in case mask_ack is provided
687 * get's only called for edge sense irqs
689 set_gpio_data(irq_to_gpio(d->irq), 0);
692 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
694 unsigned int irq = d->irq;
695 u32 gpionr = irq_to_gpio(irq);
697 if (!irqd_is_level_type(d))
698 set_gpio_data(gpionr, 0);
700 set_gpio_maska(gpionr, 0);
703 static void bfin_gpio_mask_irq(struct irq_data *d)
705 set_gpio_maska(irq_to_gpio(d->irq), 0);
708 static void bfin_gpio_unmask_irq(struct irq_data *d)
710 set_gpio_maska(irq_to_gpio(d->irq), 1);
713 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
715 u32 gpionr = irq_to_gpio(d->irq);
717 if (__test_and_set_bit(gpionr, gpio_enabled))
718 bfin_gpio_irq_prepare(gpionr);
720 bfin_gpio_unmask_irq(d);
725 static void bfin_gpio_irq_shutdown(struct irq_data *d)
727 u32 gpionr = irq_to_gpio(d->irq);
729 bfin_gpio_mask_irq(d);
730 __clear_bit(gpionr, gpio_enabled);
731 bfin_gpio_irq_free(gpionr);
734 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
736 unsigned int irq = d->irq;
739 u32 gpionr = irq_to_gpio(irq);
741 if (type == IRQ_TYPE_PROBE) {
742 /* only probe unenabled GPIO interrupt lines */
743 if (test_bit(gpionr, gpio_enabled))
745 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
748 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
749 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
751 snprintf(buf, 16, "gpio-irq%d", irq);
752 ret = bfin_gpio_irq_request(gpionr, buf);
756 if (__test_and_set_bit(gpionr, gpio_enabled))
757 bfin_gpio_irq_prepare(gpionr);
760 __clear_bit(gpionr, gpio_enabled);
764 set_gpio_inen(gpionr, 0);
765 set_gpio_dir(gpionr, 0);
767 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
768 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
769 set_gpio_both(gpionr, 1);
771 set_gpio_both(gpionr, 0);
773 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
774 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
776 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
778 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
779 set_gpio_edge(gpionr, 1);
780 set_gpio_inen(gpionr, 1);
781 set_gpio_data(gpionr, 0);
784 set_gpio_edge(gpionr, 0);
785 set_gpio_inen(gpionr, 1);
788 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
789 bfin_set_irq_handler(irq, handle_edge_irq);
791 bfin_set_irq_handler(irq, handle_level_irq);
797 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
799 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
802 # define bfin_gpio_set_wake NULL
805 static void bfin_demux_gpio_block(unsigned int irq)
807 unsigned int gpio, mask;
809 gpio = irq_to_gpio(irq);
810 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
814 bfin_handle_irq(irq);
820 void bfin_demux_gpio_irq(unsigned int inta_irq,
821 struct irq_desc *desc)
826 #if defined(BF537_FAMILY)
827 case IRQ_PF_INTA_PG_INTA:
828 bfin_demux_gpio_block(IRQ_PF0);
831 case IRQ_PH_INTA_MAC_RX:
834 #elif defined(BF533_FAMILY)
838 #elif defined(BF538_FAMILY)
842 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
852 #elif defined(CONFIG_BF561)
868 bfin_demux_gpio_block(irq);
873 #define NR_PINT_BITS 32
874 #define IRQ_NOT_AVAIL 0xFF
876 #define PINT_2_BANK(x) ((x) >> 5)
877 #define PINT_2_BIT(x) ((x) & 0x1F)
878 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
880 static unsigned char irq2pint_lut[NR_PINTS];
881 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
883 static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
884 (struct bfin_pint_regs *)PINT0_MASK_SET,
885 (struct bfin_pint_regs *)PINT1_MASK_SET,
886 (struct bfin_pint_regs *)PINT2_MASK_SET,
887 (struct bfin_pint_regs *)PINT3_MASK_SET,
889 (struct bfin_pint_regs *)PINT4_MASK_SET,
890 (struct bfin_pint_regs *)PINT5_MASK_SET,
894 inline unsigned int get_irq_base(u32 bank, u8 bmap)
896 unsigned int irq_base;
899 if (bank < 2) { /*PA-PB */
900 irq_base = IRQ_PA0 + bmap * 16;
902 irq_base = IRQ_PC0 + bmap * 16;
905 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
910 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
911 void init_pint_lut(void)
913 u16 bank, bit, irq_base, bit_pos;
917 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
919 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
921 pint_assign = pint[bank]->assign;
923 for (bit = 0; bit < NR_PINT_BITS; bit++) {
925 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
927 irq_base = get_irq_base(bank, bmap);
929 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
930 bit_pos = bit + bank * NR_PINT_BITS;
932 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
933 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
938 static void bfin_gpio_ack_irq(struct irq_data *d)
940 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
941 u32 pintbit = PINT_BIT(pint_val);
942 u32 bank = PINT_2_BANK(pint_val);
944 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
945 if (pint[bank]->invert_set & pintbit)
946 pint[bank]->invert_clear = pintbit;
948 pint[bank]->invert_set = pintbit;
950 pint[bank]->request = pintbit;
954 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
956 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
957 u32 pintbit = PINT_BIT(pint_val);
958 u32 bank = PINT_2_BANK(pint_val);
960 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
961 if (pint[bank]->invert_set & pintbit)
962 pint[bank]->invert_clear = pintbit;
964 pint[bank]->invert_set = pintbit;
967 pint[bank]->request = pintbit;
968 pint[bank]->mask_clear = pintbit;
971 static void bfin_gpio_mask_irq(struct irq_data *d)
973 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
975 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
978 static void bfin_gpio_unmask_irq(struct irq_data *d)
980 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
981 u32 pintbit = PINT_BIT(pint_val);
982 u32 bank = PINT_2_BANK(pint_val);
984 pint[bank]->mask_set = pintbit;
987 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
989 unsigned int irq = d->irq;
990 u32 gpionr = irq_to_gpio(irq);
991 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
993 if (pint_val == IRQ_NOT_AVAIL) {
995 "GPIO IRQ %d :Not in PINT Assign table "
996 "Reconfigure Interrupt to Port Assignemt\n", irq);
1000 if (__test_and_set_bit(gpionr, gpio_enabled))
1001 bfin_gpio_irq_prepare(gpionr);
1003 bfin_gpio_unmask_irq(d);
1008 static void bfin_gpio_irq_shutdown(struct irq_data *d)
1010 u32 gpionr = irq_to_gpio(d->irq);
1012 bfin_gpio_mask_irq(d);
1013 __clear_bit(gpionr, gpio_enabled);
1014 bfin_gpio_irq_free(gpionr);
1017 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1019 unsigned int irq = d->irq;
1022 u32 gpionr = irq_to_gpio(irq);
1023 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1024 u32 pintbit = PINT_BIT(pint_val);
1025 u32 bank = PINT_2_BANK(pint_val);
1027 if (pint_val == IRQ_NOT_AVAIL)
1030 if (type == IRQ_TYPE_PROBE) {
1031 /* only probe unenabled GPIO interrupt lines */
1032 if (test_bit(gpionr, gpio_enabled))
1034 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1037 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1038 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1040 snprintf(buf, 16, "gpio-irq%d", irq);
1041 ret = bfin_gpio_irq_request(gpionr, buf);
1045 if (__test_and_set_bit(gpionr, gpio_enabled))
1046 bfin_gpio_irq_prepare(gpionr);
1049 __clear_bit(gpionr, gpio_enabled);
1053 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1054 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
1056 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
1058 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1059 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1060 if (gpio_get_value(gpionr))
1061 pint[bank]->invert_set = pintbit;
1063 pint[bank]->invert_clear = pintbit;
1066 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1067 pint[bank]->edge_set = pintbit;
1068 bfin_set_irq_handler(irq, handle_edge_irq);
1070 pint[bank]->edge_clear = pintbit;
1071 bfin_set_irq_handler(irq, handle_level_irq);
1078 static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1079 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1081 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1084 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1085 u32 bank = PINT_2_BANK(pint_val);
1089 pint_irq = IRQ_PINT0;
1092 pint_irq = IRQ_PINT2;
1095 pint_irq = IRQ_PINT3;
1098 pint_irq = IRQ_PINT1;
1102 pint_irq = IRQ_PINT4;
1105 pint_irq = IRQ_PINT5;
1112 bfin_internal_set_wake(pint_irq, state);
1117 void bfin_pint_suspend(void)
1121 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1122 save_pint_reg[bank].mask_set = pint[bank]->mask_set;
1123 save_pint_reg[bank].assign = pint[bank]->assign;
1124 save_pint_reg[bank].edge_set = pint[bank]->edge_set;
1125 save_pint_reg[bank].invert_set = pint[bank]->invert_set;
1129 void bfin_pint_resume(void)
1133 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
1134 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1135 pint[bank]->assign = save_pint_reg[bank].assign;
1136 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1137 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1142 static int sec_suspend(void)
1146 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1147 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
1151 static void sec_resume(void)
1155 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1157 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1158 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1160 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
1161 bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
1164 static struct syscore_ops sec_pm_syscore_ops = {
1165 .suspend = sec_suspend,
1166 .resume = sec_resume,
1170 # define bfin_gpio_set_wake NULL
1173 void bfin_demux_gpio_irq(unsigned int inta_irq,
1174 struct irq_desc *desc)
1180 struct irq_chip *chip = irq_desc_get_chip(desc);
1182 if (chip->irq_mask_ack) {
1183 chip->irq_mask_ack(&desc->irq_data);
1185 chip->irq_mask(&desc->irq_data);
1187 chip->irq_ack(&desc->irq_data);
1215 pint_val = bank * NR_PINT_BITS;
1217 request = pint[bank]->request;
1219 level_mask = pint[bank]->edge_set & request;
1223 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1224 if (level_mask & PINT_BIT(pint_val)) {
1226 chip->irq_unmask(&desc->irq_data);
1228 bfin_handle_irq(irq);
1235 chip->irq_unmask(&desc->irq_data);
1239 static struct irq_chip bfin_gpio_irqchip = {
1241 .irq_ack = bfin_gpio_ack_irq,
1242 .irq_mask = bfin_gpio_mask_irq,
1243 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1244 .irq_unmask = bfin_gpio_unmask_irq,
1245 .irq_disable = bfin_gpio_mask_irq,
1246 .irq_enable = bfin_gpio_unmask_irq,
1247 .irq_set_type = bfin_gpio_irq_type,
1248 .irq_startup = bfin_gpio_irq_startup,
1249 .irq_shutdown = bfin_gpio_irq_shutdown,
1250 .irq_set_wake = bfin_gpio_set_wake,
1253 void __cpuinit init_exception_vectors(void)
1255 /* cannot program in software:
1256 * evt0 - emulation (jtag)
1259 bfin_write_EVT2(evt_nmi);
1260 bfin_write_EVT3(trap);
1261 bfin_write_EVT5(evt_ivhw);
1262 bfin_write_EVT6(evt_timer);
1263 bfin_write_EVT7(evt_evt7);
1264 bfin_write_EVT8(evt_evt8);
1265 bfin_write_EVT9(evt_evt9);
1266 bfin_write_EVT10(evt_evt10);
1267 bfin_write_EVT11(evt_evt11);
1268 bfin_write_EVT12(evt_evt12);
1269 bfin_write_EVT13(evt_evt13);
1270 bfin_write_EVT14(evt_evt14);
1271 bfin_write_EVT15(evt_system_call);
1277 * This function should be called during kernel startup to initialize
1278 * the BFin IRQ handling routines.
1281 int __init init_arch_irq(void)
1284 unsigned long ilat = 0;
1286 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1288 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1289 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1291 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1293 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1294 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1295 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1298 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1301 local_irq_disable();
1304 # ifdef CONFIG_PINTx_REASSIGN
1305 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1306 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1307 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1308 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1310 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1314 for (irq = 0; irq <= SYS_IRQS; irq++) {
1315 if (irq <= IRQ_CORETMR)
1316 irq_set_chip(irq, &bfin_core_irqchip);
1318 irq_set_chip(irq, &bfin_internal_irqchip);
1326 #elif defined(BF537_FAMILY)
1327 case IRQ_PH_INTA_MAC_RX:
1328 case IRQ_PF_INTA_PG_INTA:
1329 #elif defined(BF533_FAMILY)
1331 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1332 case IRQ_PORTF_INTA:
1333 case IRQ_PORTG_INTA:
1334 case IRQ_PORTH_INTA:
1335 #elif defined(CONFIG_BF561)
1336 case IRQ_PROG0_INTA:
1337 case IRQ_PROG1_INTA:
1338 case IRQ_PROG2_INTA:
1339 #elif defined(BF538_FAMILY)
1340 case IRQ_PORTF_INTA:
1342 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1344 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1346 irq_set_chained_handler(irq,
1347 bfin_demux_mac_status_irq);
1350 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1353 irq_set_handler(irq, handle_percpu_irq);
1357 #ifdef CONFIG_TICKSOURCE_CORETMR
1360 irq_set_handler(irq, handle_percpu_irq);
1362 irq_set_handler(irq, handle_simple_irq);
1367 #ifdef CONFIG_TICKSOURCE_GPTMR0
1369 irq_set_handler(irq, handle_simple_irq);
1375 irq_set_handler(irq, handle_level_irq);
1377 irq_set_handler(irq, handle_simple_irq);
1385 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1386 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1387 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1390 /* if configured as edge, then will be changed to do_edge_IRQ */
1391 for (irq = GPIO_IRQ_BASE;
1392 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1393 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1395 bfin_write_IMASK(0);
1397 ilat = bfin_read_ILAT();
1399 bfin_write_ILAT(ilat);
1402 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1403 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1404 * local_irq_enable()
1407 /* Therefore it's better to setup IARs before interrupts enabled */
1410 /* Enable interrupts IVG7-15 */
1411 bfin_irq_flags |= IMASK_IVG15 |
1412 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1413 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1415 bfin_sti(bfin_irq_flags);
1417 /* This implicitly covers ANOMALY_05000171
1418 * Boot-ROM code modifies SICA_IWRx wakeup registers
1421 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1423 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1424 * will screw up the bootrom as it relies on MDMA0/1 waking it
1425 * up from IDLE instructions. See this report for more info:
1426 * http://blackfin.uclinux.org/gf/tracker/4323
1428 if (ANOMALY_05000435)
1429 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1431 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1434 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1437 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1442 #ifdef CONFIG_DO_IRQ_L1
1443 __attribute__((l1_text))
1445 static int vec_to_irq(int vec)
1447 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1448 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1449 unsigned long sic_status[3];
1450 if (likely(vec == EVT_IVTMR_P))
1453 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1455 if (smp_processor_id()) {
1457 /* This will be optimized out in UP mode. */
1458 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1459 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1462 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1463 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1467 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1471 if (ivg >= ivg_stop)
1474 if (sic_status[0] & ivg->isrflag)
1476 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1482 #else /* SEC_GCTL */
1485 * This function should be called during kernel startup to initialize
1486 * the BFin IRQ handling routines.
1489 int __init init_arch_irq(void)
1492 unsigned long ilat = 0;
1494 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1496 local_irq_disable();
1499 # ifdef CONFIG_PINTx_REASSIGN
1500 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1501 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1502 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1503 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1504 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1505 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1507 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1511 for (irq = 0; irq <= SYS_IRQS; irq++) {
1512 if (irq <= IRQ_CORETMR) {
1513 irq_set_chip(irq, &bfin_core_irqchip);
1514 #ifdef CONFIG_TICKSOURCE_CORETMR
1515 if (irq == IRQ_CORETMR)
1517 irq_set_handler(irq, handle_percpu_irq);
1519 irq_set_handler(irq, handle_simple_irq);
1522 } else if (irq < BFIN_IRQ(0)) {
1523 irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
1525 } else if (irq < CORE_IRQS && irq != IRQ_CGU_EVT) {
1526 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1528 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1529 irq_set_chip(irq, &bfin_sec_irqchip);
1530 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1531 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1532 irq_set_chip(irq, &bfin_sec_irqchip);
1533 irq_set_handler(irq, handle_percpu_irq);
1535 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1536 handle_fasteoi_irq);
1537 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1540 for (irq = GPIO_IRQ_BASE;
1541 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1542 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1545 bfin_write_IMASK(0);
1547 ilat = bfin_read_ILAT();
1549 bfin_write_ILAT(ilat);
1552 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1554 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1556 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1558 /* Enable interrupts IVG7-15 */
1559 bfin_irq_flags |= IMASK_IVG15 |
1560 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1561 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1564 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1565 bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1566 bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1567 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1569 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1570 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1571 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1573 init_software_driven_irq();
1574 register_syscore_ops(&sec_pm_syscore_ops);
1579 #ifdef CONFIG_DO_IRQ_L1
1580 __attribute__((l1_text))
1582 static int vec_to_irq(int vec)
1584 if (likely(vec == EVT_IVTMR_P))
1587 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1589 #endif /* SEC_GCTL */
1591 #ifdef CONFIG_DO_IRQ_L1
1592 __attribute__((l1_text))
1594 void do_irq(int vec, struct pt_regs *fp)
1596 int irq = vec_to_irq(vec);
1599 asm_do_IRQ(irq, fp);
1604 int __ipipe_get_irq_priority(unsigned irq)
1608 if (irq <= IRQ_CORETMR)
1612 if (irq >= BFIN_IRQ(0))
1615 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1616 struct ivgx *ivg = ivg_table + ient;
1617 if (ivg->irqno == irq) {
1618 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1619 if (ivg7_13[prio].ifirst <= ivg &&
1620 ivg7_13[prio].istop > ivg)
1630 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1631 #ifdef CONFIG_DO_IRQ_L1
1632 __attribute__((l1_text))
1634 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1636 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1637 struct ipipe_domain *this_domain = __ipipe_current_domain;
1640 irq = vec_to_irq(vec);
1644 if (irq == IRQ_SYSTMR) {
1645 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1646 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1648 /* This is basically what we need from the register frame. */
1649 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1650 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1651 if (this_domain != ipipe_root_domain)
1652 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1654 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1658 * We don't want Linux interrupt handlers to run at the
1659 * current core priority level (i.e. < EVT15), since this
1660 * might delay other interrupts handled by a high priority
1661 * domain. Here is what we do instead:
1663 * - we raise the SYNCDEFER bit to prevent
1664 * __ipipe_handle_irq() to sync the pipeline for the root
1665 * stage for the incoming interrupt. Upon return, that IRQ is
1666 * pending in the interrupt log.
1668 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1669 * that _schedule_and_signal_from_int will eventually sync the
1670 * pipeline from EVT15.
1672 if (this_domain == ipipe_root_domain) {
1673 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1677 ipipe_trace_irq_entry(irq);
1678 __ipipe_handle_irq(irq, regs);
1679 ipipe_trace_irq_exit(irq);
1681 if (user_mode(regs) &&
1682 !ipipe_test_foreign_stack() &&
1683 (current->ipipe_flags & PF_EVTRET) != 0) {
1685 * Testing for user_regs() does NOT fully eliminate
1686 * foreign stack contexts, because of the forged
1687 * interrupt returns we do through
1688 * __ipipe_call_irqtail. In that case, we might have
1689 * preempted a foreign stack context in a high
1690 * priority domain, with a single interrupt level now
1691 * pending after the irqtail unwinding is done. In
1692 * which case user_mode() is now true, and the event
1693 * gets dispatched spuriously.
1695 current->ipipe_flags &= ~PF_EVTRET;
1696 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1699 if (this_domain == ipipe_root_domain) {
1700 set_thread_flag(TIF_IRQ_SYNC);
1702 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1703 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1710 #endif /* CONFIG_IPIPE */