2 * Switch a MMU context.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/slab.h>
18 #include <asm/cacheflush.h>
19 #include <asm/hazards.h>
20 #include <asm/tlbflush.h>
21 #ifdef CONFIG_MIPS_MT_SMTC
22 #include <asm/mipsmtregs.h>
25 #include <asm-generic/mm_hooks.h>
27 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
29 extern void tlbmiss_handler_setup_pgd(unsigned long); \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
33 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
35 #define TLBMISS_HANDLER_RESTORE() \
36 write_c0_xcontext((unsigned long) smp_processor_id() << \
39 #define TLBMISS_HANDLER_SETUP() \
41 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
42 TLBMISS_HANDLER_RESTORE(); \
45 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
48 * For the fast tlb miss handlers, we keep a per cpu array of pointers
49 * to the current pgd for each processor. Also, the proc. id is stuffed
50 * into the context register.
52 extern unsigned long pgd_current[];
54 #define TLBMISS_HANDLER_RESTORE() \
55 write_c0_context((unsigned long) smp_processor_id() << \
58 #define TLBMISS_HANDLER_SETUP() \
59 TLBMISS_HANDLER_RESTORE(); \
60 back_to_back_c0_hazard(); \
61 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
62 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
63 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
66 #define ASID_MASK 0xfc0
68 #elif defined(CONFIG_CPU_R8000)
71 #define ASID_MASK 0xff0
73 #elif defined(CONFIG_MIPS_MT_SMTC)
76 extern unsigned long smtc_asid_mask;
77 #define ASID_MASK (smtc_asid_mask)
78 #define HW_ASID_MASK 0xff
79 /* End SMTC/34K debug hack */
80 #else /* FIXME: not correct for R6000 */
83 #define ASID_MASK 0xff
87 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
88 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
89 #define asid_cache(cpu) (cpu_data[cpu].asid_cache)
91 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
96 * All unused by hardware upper bits will be considered
97 * as a software asid extension.
99 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
100 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
102 #ifndef CONFIG_MIPS_MT_SMTC
103 /* Normal, classic MIPS get_new_mmu_context */
105 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
107 extern void kvm_local_flush_tlb_all(void);
108 unsigned long asid = asid_cache(cpu);
110 if (! ((asid += ASID_INC) & ASID_MASK) ) {
111 if (cpu_has_vtag_icache)
114 kvm_local_flush_tlb_all(); /* start new asid cycle */
116 local_flush_tlb_all(); /* start new asid cycle */
118 if (!asid) /* fix version if needed */
119 asid = ASID_FIRST_VERSION;
122 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
125 #else /* CONFIG_MIPS_MT_SMTC */
127 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
129 #endif /* CONFIG_MIPS_MT_SMTC */
132 * Initialize the context related info for a new mm_struct
136 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
140 for_each_possible_cpu(i)
141 cpu_context(i, mm) = 0;
146 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
147 struct task_struct *tsk)
149 unsigned int cpu = smp_processor_id();
151 #ifdef CONFIG_MIPS_MT_SMTC
152 unsigned long oldasid;
153 unsigned long mtflags;
154 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
155 local_irq_save(flags);
158 local_irq_save(flags);
159 #endif /* CONFIG_MIPS_MT_SMTC */
161 /* Check if our ASID is of an older version and thus invalid */
162 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
163 get_new_mmu_context(next, cpu);
164 #ifdef CONFIG_MIPS_MT_SMTC
166 * If the EntryHi ASID being replaced happens to be
167 * the value flagged at ASID recycling time as having
168 * an extended life, clear the bit showing it being
169 * in use by this "CPU", and if that's the last bit,
170 * free up the ASID value for use and flush any old
171 * instances of it from the TLB.
173 oldasid = (read_c0_entryhi() & ASID_MASK);
174 if(smtc_live_asid[mytlb][oldasid]) {
175 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
176 if(smtc_live_asid[mytlb][oldasid] == 0)
177 smtc_flush_tlb_asid(oldasid);
180 * Tread softly on EntryHi, and so long as we support
181 * having ASID_MASK smaller than the hardware maximum,
182 * make sure no "soft" bits become "hard"...
184 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
185 cpu_asid(cpu, next));
186 ehb(); /* Make sure it propagates to TCStatus */
189 write_c0_entryhi(cpu_asid(cpu, next));
190 #endif /* CONFIG_MIPS_MT_SMTC */
191 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
194 * Mark current->active_mm as not "active" anymore.
195 * We don't want to mislead possible IPI tlb flush routines.
197 cpumask_clear_cpu(cpu, mm_cpumask(prev));
198 cpumask_set_cpu(cpu, mm_cpumask(next));
200 local_irq_restore(flags);
204 * Destroy context related info for an mm_struct that is about
207 static inline void destroy_context(struct mm_struct *mm)
211 #define deactivate_mm(tsk, mm) do { } while (0)
214 * After we have set current->mm to a new value, this activates
215 * the context for the new mm so we see the new mappings.
218 activate_mm(struct mm_struct *prev, struct mm_struct *next)
221 unsigned int cpu = smp_processor_id();
223 #ifdef CONFIG_MIPS_MT_SMTC
224 unsigned long oldasid;
225 unsigned long mtflags;
226 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
227 #endif /* CONFIG_MIPS_MT_SMTC */
229 local_irq_save(flags);
231 /* Unconditionally get a new ASID. */
232 get_new_mmu_context(next, cpu);
234 #ifdef CONFIG_MIPS_MT_SMTC
235 /* See comments for similar code above */
237 oldasid = read_c0_entryhi() & ASID_MASK;
238 if(smtc_live_asid[mytlb][oldasid]) {
239 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
240 if(smtc_live_asid[mytlb][oldasid] == 0)
241 smtc_flush_tlb_asid(oldasid);
243 /* See comments for similar code above */
244 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
245 cpu_asid(cpu, next));
246 ehb(); /* Make sure it propagates to TCStatus */
249 write_c0_entryhi(cpu_asid(cpu, next));
250 #endif /* CONFIG_MIPS_MT_SMTC */
251 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
253 /* mark mmu ownership change */
254 cpumask_clear_cpu(cpu, mm_cpumask(prev));
255 cpumask_set_cpu(cpu, mm_cpumask(next));
257 local_irq_restore(flags);
261 * If mm is currently active_mm, we can't really drop it. Instead,
262 * we will get a new one for it.
265 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
268 #ifdef CONFIG_MIPS_MT_SMTC
269 unsigned long oldasid;
270 /* Can't use spinlock because called from TLB flush within DVPE */
271 unsigned int prevvpe;
272 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
273 #endif /* CONFIG_MIPS_MT_SMTC */
275 local_irq_save(flags);
277 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
278 get_new_mmu_context(mm, cpu);
279 #ifdef CONFIG_MIPS_MT_SMTC
280 /* See comments for similar code above */
282 oldasid = (read_c0_entryhi() & ASID_MASK);
283 if (smtc_live_asid[mytlb][oldasid]) {
284 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
285 if(smtc_live_asid[mytlb][oldasid] == 0)
286 smtc_flush_tlb_asid(oldasid);
288 /* See comments for similar code above */
289 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
290 | cpu_asid(cpu, mm));
291 ehb(); /* Make sure it propagates to TCStatus */
293 #else /* not CONFIG_MIPS_MT_SMTC */
294 write_c0_entryhi(cpu_asid(cpu, mm));
295 #endif /* CONFIG_MIPS_MT_SMTC */
297 /* will get a new context next time */
298 #ifndef CONFIG_MIPS_MT_SMTC
299 cpu_context(cpu, mm) = 0;
303 /* SMTC shares the TLB (and ASIDs) across VPEs */
304 for_each_online_cpu(i) {
305 if((smtc_status & SMTC_TLB_SHARED)
306 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
307 cpu_context(i, mm) = 0;
309 #endif /* CONFIG_MIPS_MT_SMTC */
311 local_irq_restore(flags);
314 #endif /* _ASM_MMU_CONTEXT_H */