arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | TX39_CONF_HALT);
  44 }
  45
  46 static void r4k_wait(void)
  47 {
  48         __asm__(".set\tmips3\n\t"
  49                 "wait\n\t"
  50                 ".set\tmips0");
  51 }
  52
  53 /* The Au1xxx wait is available only if using 32khz counter or
  54  * external timer source, but specifically not CP0 Counter. */
  55 int allow_au1k_wait;
  56
  57 static void au1k_wait(void)
  58 {
  59         /* using the wait instruction makes CP0 counter unusable */
  60         __asm__(".set mips3\n\t"
  61                 "cache 0x14, 0(%0)\n\t"
  62                 "cache 0x14, 32(%0)\n\t"
  63                 "sync\n\t"
  64                 "nop\n\t"
  65                 "wait\n\t"
  66                 "nop\n\t"
  67                 "nop\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 ".set mips0\n\t"
  71                 : : "r" (au1k_wait));
  72 }
  73
  74 static int __initdata nowait = 0;
  75
  76 int __init wait_disable(char *s)
  77 {
  78         nowait = 1;
  79
  80         return 1;
  81 }
  82
  83 __setup("nowait", wait_disable);
  84
  85 static inline void check_wait(void)
  86 {
  87         struct cpuinfo_mips *c = &current_cpu_data;
  88
  89         printk("Checking for 'wait' instruction... ");
  90         if (nowait) {
  91                 printk (" disabled.\n");
  92                 return;
  93         }
  94
  95         switch (c->cputype) {
  96         case CPU_R3081:
  97         case CPU_R3081E:
  98                 cpu_wait = r3081_wait;
  99                 printk(" available.\n");
 100                 break;
 101         case CPU_TX3927:
 102                 cpu_wait = r39xx_wait;
 103                 printk(" available.\n");
 104                 break;
 105         case CPU_R4200:
 106 /*      case CPU_R4300: */
 107         case CPU_R4600:
 108         case CPU_R4640:
 109         case CPU_R4650:
 110         case CPU_R4700:
 111         case CPU_R5000:
 112         case CPU_NEVADA:
 113         case CPU_RM7000:
 114         case CPU_RM9000:
 115         case CPU_TX49XX:
 116         case CPU_4KC:
 117         case CPU_4KEC:
 118         case CPU_4KSC:
 119         case CPU_5KC:
 120 /*      case CPU_20KC:*/
 121         case CPU_24K:
 122         case CPU_25KF:
 123         case CPU_34K:
 124         case CPU_74K:
 125         case CPU_PR4450:
 126                 cpu_wait = r4k_wait;
 127                 printk(" available.\n");
 128                 break;
 129         case CPU_AU1000:
 130         case CPU_AU1100:
 131         case CPU_AU1500:
 132         case CPU_AU1550:
 133         case CPU_AU1200:
 134                 if (allow_au1k_wait) {
 135                         cpu_wait = au1k_wait;
 136                         printk(" available.\n");
 137                 } else
 138                         printk(" unavailable.\n");
 139                 break;
 140         default:
 141                 printk(" unavailable.\n");
 142                 break;
 143         }
 144 }
 145
 146 void __init check_bugs32(void)
 147 {
 148         check_wait();
 149 }
 150
 151 /*
 152  * Probe whether cpu has config register by trying to play with
 153  * alternate cache bit and see whether it matters.
 154  * It's used by cpu_probe to distinguish between R3000A and R3081.
 155  */
 156 static inline int cpu_has_confreg(void)
 157 {
 158 #ifdef CONFIG_CPU_R3000
 159         extern unsigned long r3k_cache_size(unsigned long);
 160         unsigned long size1, size2;
 161         unsigned long cfg = read_c0_conf();
 162
 163         size1 = r3k_cache_size(ST0_ISC);
 164         write_c0_conf(cfg ^ R30XX_CONF_AC);
 165         size2 = r3k_cache_size(ST0_ISC);
 166         write_c0_conf(cfg);
 167         return size1 != size2;
 168 #else
 169         return 0;
 170 #endif
 171 }
 172
 173 /*
 174  * Get the FPU Implementation/Revision.
 175  */
 176 static inline unsigned long cpu_get_fpu_id(void)
 177 {
 178         unsigned long tmp, fpu_id;
 179
 180         tmp = read_c0_status();
 181         __enable_fpu();
 182         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 183         write_c0_status(tmp);
 184         return fpu_id;
 185 }
 186
 187 /*
 188  * Check the CPU has an FPU the official way.
 189  */
 190 static inline int __cpu_has_fpu(void)
 191 {
 192         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 193 }
 194
 195 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 196                 | MIPS_CPU_COUNTER)
 197
 198 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 199 {
 200         switch (c->processor_id & 0xff00) {
 201         case PRID_IMP_R2000:
 202                 c->cputype = CPU_R2000;
 203                 c->isa_level = MIPS_CPU_ISA_I;
 204                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 205                              MIPS_CPU_NOFPUEX;
 206                 if (__cpu_has_fpu())
 207                         c->options |= MIPS_CPU_FPU;
 208                 c->tlbsize = 64;
 209                 break;
 210         case PRID_IMP_R3000:
 211                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 212                         if (cpu_has_confreg())
 213                                 c->cputype = CPU_R3081E;
 214                         else
 215                                 c->cputype = CPU_R3000A;
 216                 else
 217                         c->cputype = CPU_R3000;
 218                 c->isa_level = MIPS_CPU_ISA_I;
 219                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 220                              MIPS_CPU_NOFPUEX;
 221                 if (__cpu_has_fpu())
 222                         c->options |= MIPS_CPU_FPU;
 223                 c->tlbsize = 64;
 224                 break;
 225         case PRID_IMP_R4000:
 226                 if (read_c0_config() & CONF_SC) {
 227                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 228                                 c->cputype = CPU_R4400PC;
 229                         else
 230                                 c->cputype = CPU_R4000PC;
 231                 } else {
 232                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 233                                 c->cputype = CPU_R4400SC;
 234                         else
 235                                 c->cputype = CPU_R4000SC;
 236                 }
 237
 238                 c->isa_level = MIPS_CPU_ISA_III;
 239                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 240                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 241                              MIPS_CPU_LLSC;
 242                 c->tlbsize = 48;
 243                 break;
 244         case PRID_IMP_VR41XX:
 245                 switch (c->processor_id & 0xf0) {
 246                 case PRID_REV_VR4111:
 247                         c->cputype = CPU_VR4111;
 248                         break;
 249                 case PRID_REV_VR4121:
 250                         c->cputype = CPU_VR4121;
 251                         break;
 252                 case PRID_REV_VR4122:
 253                         if ((c->processor_id & 0xf) < 0x3)
 254                                 c->cputype = CPU_VR4122;
 255                         else
 256                                 c->cputype = CPU_VR4181A;
 257                         break;
 258                 case PRID_REV_VR4130:
 259                         if ((c->processor_id & 0xf) < 0x4)
 260                                 c->cputype = CPU_VR4131;
 261                         else
 262                                 c->cputype = CPU_VR4133;
 263                         break;
 264                 default:
 265                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 266                         c->cputype = CPU_VR41XX;
 267                         break;
 268                 }
 269                 c->isa_level = MIPS_CPU_ISA_III;
 270                 c->options = R4K_OPTS;
 271                 c->tlbsize = 32;
 272                 break;
 273         case PRID_IMP_R4300:
 274                 c->cputype = CPU_R4300;
 275                 c->isa_level = MIPS_CPU_ISA_III;
 276                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 277                              MIPS_CPU_LLSC;
 278                 c->tlbsize = 32;
 279                 break;
 280         case PRID_IMP_R4600:
 281                 c->cputype = CPU_R4600;
 282                 c->isa_level = MIPS_CPU_ISA_III;
 283                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 284                              MIPS_CPU_LLSC;
 285                 c->tlbsize = 48;
 286                 break;
 287         #if 0
 288         case PRID_IMP_R4650:
 289                 /*
 290                  * This processor doesn't have an MMU, so it's not
 291                  * "real easy" to run Linux on it. It is left purely
 292                  * for documentation.  Commented out because it shares
 293                  * it's c0_prid id number with the TX3900.
 294                  */
 295                 c->cputype = CPU_R4650;
 296                 c->isa_level = MIPS_CPU_ISA_III;
 297                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 298                 c->tlbsize = 48;
 299                 break;
 300         #endif
 301         case PRID_IMP_TX39:
 302                 c->isa_level = MIPS_CPU_ISA_I;
 303                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 304
 305                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 306                         c->cputype = CPU_TX3927;
 307                         c->tlbsize = 64;
 308                 } else {
 309                         switch (c->processor_id & 0xff) {
 310                         case PRID_REV_TX3912:
 311                                 c->cputype = CPU_TX3912;
 312                                 c->tlbsize = 32;
 313                                 break;
 314                         case PRID_REV_TX3922:
 315                                 c->cputype = CPU_TX3922;
 316                                 c->tlbsize = 64;
 317                                 break;
 318                         default:
 319                                 c->cputype = CPU_UNKNOWN;
 320                                 break;
 321                         }
 322                 }
 323                 break;
 324         case PRID_IMP_R4700:
 325                 c->cputype = CPU_R4700;
 326                 c->isa_level = MIPS_CPU_ISA_III;
 327                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 328                              MIPS_CPU_LLSC;
 329                 c->tlbsize = 48;
 330                 break;
 331         case PRID_IMP_TX49:
 332                 c->cputype = CPU_TX49XX;
 333                 c->isa_level = MIPS_CPU_ISA_III;
 334                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 335                 if (!(c->processor_id & 0x08))
 336                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 337                 c->tlbsize = 48;
 338                 break;
 339         case PRID_IMP_R5000:
 340                 c->cputype = CPU_R5000;
 341                 c->isa_level = MIPS_CPU_ISA_IV;
 342                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 343                              MIPS_CPU_LLSC;
 344                 c->tlbsize = 48;
 345                 break;
 346         case PRID_IMP_R5432:
 347                 c->cputype = CPU_R5432;
 348                 c->isa_level = MIPS_CPU_ISA_IV;
 349                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 350                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 351                 c->tlbsize = 48;
 352                 break;
 353         case PRID_IMP_R5500:
 354                 c->cputype = CPU_R5500;
 355                 c->isa_level = MIPS_CPU_ISA_IV;
 356                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 357                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 358                 c->tlbsize = 48;
 359                 break;
 360         case PRID_IMP_NEVADA:
 361                 c->cputype = CPU_NEVADA;
 362                 c->isa_level = MIPS_CPU_ISA_IV;
 363                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 364                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 365                 c->tlbsize = 48;
 366                 break;
 367         case PRID_IMP_R6000:
 368                 c->cputype = CPU_R6000;
 369                 c->isa_level = MIPS_CPU_ISA_II;
 370                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 371                              MIPS_CPU_LLSC;
 372                 c->tlbsize = 32;
 373                 break;
 374         case PRID_IMP_R6000A:
 375                 c->cputype = CPU_R6000A;
 376                 c->isa_level = MIPS_CPU_ISA_II;
 377                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 378                              MIPS_CPU_LLSC;
 379                 c->tlbsize = 32;
 380                 break;
 381         case PRID_IMP_RM7000:
 382                 c->cputype = CPU_RM7000;
 383                 c->isa_level = MIPS_CPU_ISA_IV;
 384                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 385                              MIPS_CPU_LLSC;
 386                 /*
 387                  * Undocumented RM7000:  Bit 29 in the info register of
 388                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 389                  * entries.
 390                  *
 391                  * 29      1 =>    64 entry JTLB
 392                  *         0 =>    48 entry JTLB
 393                  */
 394                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 395                 break;
 396         case PRID_IMP_RM9000:
 397                 c->cputype = CPU_RM9000;
 398                 c->isa_level = MIPS_CPU_ISA_IV;
 399                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 400                              MIPS_CPU_LLSC;
 401                 /*
 402                  * Bit 29 in the info register of the RM9000
 403                  * indicates if the TLB has 48 or 64 entries.
 404                  *
 405                  * 29      1 =>    64 entry JTLB
 406                  *         0 =>    48 entry JTLB
 407                  */
 408                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 409                 break;
 410         case PRID_IMP_R8000:
 411                 c->cputype = CPU_R8000;
 412                 c->isa_level = MIPS_CPU_ISA_IV;
 413                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 414                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 415                              MIPS_CPU_LLSC;
 416                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 417                 break;
 418         case PRID_IMP_R10000:
 419                 c->cputype = CPU_R10000;
 420                 c->isa_level = MIPS_CPU_ISA_IV;
 421                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 422                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 423                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 424                              MIPS_CPU_LLSC;
 425                 c->tlbsize = 64;
 426                 break;
 427         case PRID_IMP_R12000:
 428                 c->cputype = CPU_R12000;
 429                 c->isa_level = MIPS_CPU_ISA_IV;
 430                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 431                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 432                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 433                              MIPS_CPU_LLSC;
 434                 c->tlbsize = 64;
 435                 break;
 436         }
 437 }
 438
 439 static char unknown_isa[] __initdata = KERN_ERR \
 440         "Unsupported ISA type, c0.config0: %d.";
 441
 442 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 443 {
 444         unsigned int config0;
 445         int isa;
 446
 447         config0 = read_c0_config();
 448
 449         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 450                 c->options |= MIPS_CPU_TLB;
 451         isa = (config0 & MIPS_CONF_AT) >> 13;
 452         switch (isa) {
 453         case 0:
 454                 switch ((config0 >> 10) & 7) {
 455                 case 0:
 456                         c->isa_level = MIPS_CPU_ISA_M32R1;
 457                         break;
 458                 case 1:
 459                         c->isa_level = MIPS_CPU_ISA_M32R2;
 460                         break;
 461                 default:
 462                         goto unknown;
 463                 }
 464                 break;
 465         case 2:
 466                 switch ((config0 >> 10) & 7) {
 467                 case 0:
 468                         c->isa_level = MIPS_CPU_ISA_M64R1;
 469                         break;
 470                 case 1:
 471                         c->isa_level = MIPS_CPU_ISA_M64R2;
 472                         break;
 473                 default:
 474                         goto unknown;
 475                 }
 476                 break;
 477         default:
 478                 goto unknown;
 479         }
 480
 481         return config0 & MIPS_CONF_M;
 482
 483 unknown:
 484         panic(unknown_isa, config0);
 485 }
 486
 487 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 488 {
 489         unsigned int config1;
 490
 491         config1 = read_c0_config1();
 492
 493         if (config1 & MIPS_CONF1_MD)
 494                 c->ases |= MIPS_ASE_MDMX;
 495         if (config1 & MIPS_CONF1_WR)
 496                 c->options |= MIPS_CPU_WATCH;
 497         if (config1 & MIPS_CONF1_CA)
 498                 c->ases |= MIPS_ASE_MIPS16;
 499         if (config1 & MIPS_CONF1_EP)
 500                 c->options |= MIPS_CPU_EJTAG;
 501         if (config1 & MIPS_CONF1_FP) {
 502                 c->options |= MIPS_CPU_FPU;
 503                 c->options |= MIPS_CPU_32FPR;
 504         }
 505         if (cpu_has_tlb)
 506                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 507
 508         return config1 & MIPS_CONF_M;
 509 }
 510
 511 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 512 {
 513         unsigned int config2;
 514
 515         config2 = read_c0_config2();
 516
 517         if (config2 & MIPS_CONF2_SL)
 518                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 519
 520         return config2 & MIPS_CONF_M;
 521 }
 522
 523 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 524 {
 525         unsigned int config3;
 526
 527         config3 = read_c0_config3();
 528
 529         if (config3 & MIPS_CONF3_SM)
 530                 c->ases |= MIPS_ASE_SMARTMIPS;
 531         if (config3 & MIPS_CONF3_DSP)
 532                 c->ases |= MIPS_ASE_DSP;
 533         if (config3 & MIPS_CONF3_VINT)
 534                 c->options |= MIPS_CPU_VINT;
 535         if (config3 & MIPS_CONF3_VEIC)
 536                 c->options |= MIPS_CPU_VEIC;
 537         if (config3 & MIPS_CONF3_MT)
 538                 c->ases |= MIPS_ASE_MIPSMT;
 539
 540         return config3 & MIPS_CONF_M;
 541 }
 542
 543 static inline void decode_configs(struct cpuinfo_mips *c)
 544 {
 545         /* MIPS32 or MIPS64 compliant CPU.  */
 546         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 547                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 548
 549         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 550
 551         /* Read Config registers.  */
 552         if (!decode_config0(c))
 553                 return;                 /* actually worth a panic() */
 554         if (!decode_config1(c))
 555                 return;
 556         if (!decode_config2(c))
 557                 return;
 558         if (!decode_config3(c))
 559                 return;
 560 }
 561
 562 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 563 {
 564         decode_configs(c);
 565         switch (c->processor_id & 0xff00) {
 566         case PRID_IMP_4KC:
 567                 c->cputype = CPU_4KC;
 568                 break;
 569         case PRID_IMP_4KEC:
 570                 c->cputype = CPU_4KEC;
 571                 break;
 572         case PRID_IMP_4KECR2:
 573                 c->cputype = CPU_4KEC;
 574                 break;
 575         case PRID_IMP_4KSC:
 576         case PRID_IMP_4KSD:
 577                 c->cputype = CPU_4KSC;
 578                 break;
 579         case PRID_IMP_5KC:
 580                 c->cputype = CPU_5KC;
 581                 break;
 582         case PRID_IMP_20KC:
 583                 c->cputype = CPU_20KC;
 584                 break;
 585         case PRID_IMP_24K:
 586         case PRID_IMP_24KE:
 587                 c->cputype = CPU_24K;
 588                 break;
 589         case PRID_IMP_25KF:
 590                 c->cputype = CPU_25KF;
 591                 /* Probe for L2 cache */
 592                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 593                 break;
 594         case PRID_IMP_34K:
 595                 c->cputype = CPU_34K;
 596                 break;
 597         case PRID_IMP_74K:
 598                 c->cputype = CPU_74K;
 599                 break;
 600         }
 601 }
 602
 603 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 604 {
 605         decode_configs(c);
 606         switch (c->processor_id & 0xff00) {
 607         case PRID_IMP_AU1_REV1:
 608         case PRID_IMP_AU1_REV2:
 609                 switch ((c->processor_id >> 24) & 0xff) {
 610                 case 0:
 611                         c->cputype = CPU_AU1000;
 612                         break;
 613                 case 1:
 614                         c->cputype = CPU_AU1500;
 615                         break;
 616                 case 2:
 617                         c->cputype = CPU_AU1100;
 618                         break;
 619                 case 3:
 620                         c->cputype = CPU_AU1550;
 621                         break;
 622                 case 4:
 623                         c->cputype = CPU_AU1200;
 624                         break;
 625                 default:
 626                         panic("Unknown Au Core!");
 627                         break;
 628                 }
 629                 break;
 630         }
 631 }
 632
 633 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 634 {
 635         decode_configs(c);
 636
 637         /*
 638          * For historical reasons the SB1 comes with it's own variant of
 639          * cache code which eventually will be folded into c-r4k.c.  Until
 640          * then we pretend it's got it's own cache architecture.
 641          */
 642         c->options &= ~MIPS_CPU_4K_CACHE;
 643         c->options |= MIPS_CPU_SB1_CACHE;
 644
 645         switch (c->processor_id & 0xff00) {
 646         case PRID_IMP_SB1:
 647                 c->cputype = CPU_SB1;
 648                 /* FPU in pass1 is known to have issues. */
 649                 if ((c->processor_id & 0xff) < 0x20)
 650                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 651                 break;
 652         case PRID_IMP_SB1A:
 653                 c->cputype = CPU_SB1A;
 654                 break;
 655         }
 656 }
 657
 658 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 659 {
 660         decode_configs(c);
 661         switch (c->processor_id & 0xff00) {
 662         case PRID_IMP_SR71000:
 663                 c->cputype = CPU_SR71000;
 664                 c->scache.ways = 8;
 665                 c->tlbsize = 64;
 666                 break;
 667         }
 668 }
 669
 670 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 671 {
 672         decode_configs(c);
 673         switch (c->processor_id & 0xff00) {
 674         case PRID_IMP_PR4450:
 675                 c->cputype = CPU_PR4450;
 676                 c->isa_level = MIPS_CPU_ISA_M32R1;
 677                 break;
 678         default:
 679                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 680                 break;
 681         }
 682 }
 683
 684
 685 __init void cpu_probe(void)
 686 {
 687         struct cpuinfo_mips *c = &current_cpu_data;
 688
 689         c->processor_id = PRID_IMP_UNKNOWN;
 690         c->fpu_id       = FPIR_IMP_NONE;
 691         c->cputype      = CPU_UNKNOWN;
 692
 693         c->processor_id = read_c0_prid();
 694         switch (c->processor_id & 0xff0000) {
 695         case PRID_COMP_LEGACY:
 696                 cpu_probe_legacy(c);
 697                 break;
 698         case PRID_COMP_MIPS:
 699                 cpu_probe_mips(c);
 700                 break;
 701         case PRID_COMP_ALCHEMY:
 702                 cpu_probe_alchemy(c);
 703                 break;
 704         case PRID_COMP_SIBYTE:
 705                 cpu_probe_sibyte(c);
 706                 break;
 707         case PRID_COMP_SANDCRAFT:
 708                 cpu_probe_sandcraft(c);
 709                 break;
 710         case PRID_COMP_PHILIPS:
 711                 cpu_probe_philips(c);
 712                 break;
 713         default:
 714                 c->cputype = CPU_UNKNOWN;
 715         }
 716         if (c->options & MIPS_CPU_FPU) {
 717                 c->fpu_id = cpu_get_fpu_id();
 718
 719                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 720                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 721                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 722                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 723                         if (c->fpu_id & MIPS_FPIR_3D)
 724                                 c->ases |= MIPS_ASE_MIPS3D;
 725                 }
 726         }
 727 }
 728
 729 __init void cpu_report(void)
 730 {
 731         struct cpuinfo_mips *c = &current_cpu_data;
 732
 733         printk("CPU revision is: %08x\n", c->processor_id);
 734         if (c->options & MIPS_CPU_FPU)
 735                 printk("FPU revision is: %08x\n", c->fpu_id);
 736 }