arch/mips/kernel/mips-cpc.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/errno.h>
  12
  13 #include <asm/mips-cm.h>
  14 #include <asm/mips-cpc.h>
  15
  16 void __iomem *mips_cpc_base;
  17
  18 static DEFINE_PER_CPU_ALIGNED(spinlock_t, cpc_core_lock);
  19
  20 static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
  21
  22 phys_t __weak mips_cpc_phys_base(void)
  23 {
  24         u32 cpc_base;
  25
  26         if (!mips_cm_present())
  27                 return 0;
  28
  29         if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
  30                 return 0;
  31
  32         /* If the CPC is already enabled, leave it so */
  33         cpc_base = read_gcr_cpc_base();
  34         if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
  35                 return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
  36
  37         /* Otherwise, give it the default address & enable it */
  38         cpc_base = mips_cpc_default_phys_base();
  39         write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
  40         return cpc_base;
  41 }
  42
  43 int mips_cpc_probe(void)
  44 {
  45         phys_t addr;
  46         unsigned cpu;
  47
  48         for_each_possible_cpu(cpu)
  49                 spin_lock_init(&per_cpu(cpc_core_lock, cpu));
  50
  51         addr = mips_cpc_phys_base();
  52         if (!addr)
  53                 return -ENODEV;
  54
  55         mips_cpc_base = ioremap_nocache(addr, 0x8000);
  56         if (!mips_cpc_base)
  57                 return -ENXIO;
  58
  59         return 0;
  60 }
  61
  62 void mips_cpc_lock_other(unsigned int core)
  63 {
  64         unsigned curr_core;
  65         preempt_disable();
  66         curr_core = current_cpu_data.core;
  67         spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
  68                           per_cpu(cpc_core_lock_flags, curr_core));
  69         write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
  70 }
  71
  72 void mips_cpc_unlock_other(void)
  73 {
  74         unsigned curr_core = current_cpu_data.core;
  75         spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
  76                                per_cpu(cpc_core_lock_flags, curr_core));
  77         preempt_enable();
  78 }