arch/mips/kernel/smp-cps.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/sched.h>
  13 #include <linux/slab.h>
  14 #include <linux/smp.h>
  15 #include <linux/types.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/gic.h>
  19 #include <asm/mips-cm.h>
  20 #include <asm/mips-cpc.h>
  21 #include <asm/mips_mt.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/smp-cps.h>
  24 #include <asm/time.h>
  25 #include <asm/uasm.h>
  26
  27 static DECLARE_BITMAP(core_power, NR_CPUS);
  28
  29 struct core_boot_config *mips_cps_core_bootcfg;
  30
  31 static unsigned core_vpe_count(unsigned core)
  32 {
  33         unsigned cfg;
  34
  35         if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  36                 return 1;
  37
  38         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  39         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  40         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  41 }
  42
  43 static void __init cps_smp_setup(void)
  44 {
  45         unsigned int ncores, nvpes, core_vpes;
  46         int c, v;
  47
  48         /* Detect & record VPE topology */
  49         ncores = mips_cm_numcores();
  50         pr_info("VPE topology ");
  51         for (c = nvpes = 0; c < ncores; c++) {
  52                 core_vpes = core_vpe_count(c);
  53                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  54
  55                 /* Use the number of VPEs in core 0 for smp_num_siblings */
  56                 if (!c)
  57                         smp_num_siblings = core_vpes;
  58
  59                 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  60                         cpu_data[nvpes + v].core = c;
  61 #ifdef CONFIG_MIPS_MT_SMP
  62                         cpu_data[nvpes + v].vpe_id = v;
  63 #endif
  64                 }
  65
  66                 nvpes += core_vpes;
  67         }
  68         pr_cont("} total %u\n", nvpes);
  69
  70         /* Indicate present CPUs (CPU being synonymous with VPE) */
  71         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  72                 set_cpu_possible(v, true);
  73                 set_cpu_present(v, true);
  74                 __cpu_number_map[v] = v;
  75                 __cpu_logical_map[v] = v;
  76         }
  77
  78         /* Core 0 is powered up (we're running on it) */
  79         bitmap_set(core_power, 0, 1);
  80
  81         /* Initialise core 0 */
  82         mips_cps_core_init();
  83
  84         /* Make core 0 coherent with everything */
  85         write_gcr_cl_coherence(0xff);
  86 }
  87
  88 static void __init cps_prepare_cpus(unsigned int max_cpus)
  89 {
  90         unsigned ncores, core_vpes, c;
  91         u32 *entry_code;
  92
  93         mips_mt_set_cpuoptions();
  94
  95         /* Patch the start of mips_cps_core_entry to provide the CM base */
  96         entry_code = (u32 *)&mips_cps_core_entry;
  97         UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
  98         dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
  99                             (void *)entry_code - (void *)&mips_cps_core_entry);
 100
 101         /* Allocate core boot configuration structs */
 102         ncores = mips_cm_numcores();
 103         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 104                                         GFP_KERNEL);
 105         if (!mips_cps_core_bootcfg) {
 106                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 107                 goto err_out;
 108         }
 109
 110         /* Allocate VPE boot configuration structs */
 111         for (c = 0; c < ncores; c++) {
 112                 core_vpes = core_vpe_count(c);
 113                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 114                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 115                                 GFP_KERNEL);
 116                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 117                         pr_err("Failed to allocate %u VPE boot configs\n",
 118                                core_vpes);
 119                         goto err_out;
 120                 }
 121         }
 122
 123         /* Mark this CPU as booted */
 124         atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
 125                    1 << cpu_vpe_id(&current_cpu_data));
 126
 127         return;
 128 err_out:
 129         /* Clean up allocations */
 130         if (mips_cps_core_bootcfg) {
 131                 for (c = 0; c < ncores; c++)
 132                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 133                 kfree(mips_cps_core_bootcfg);
 134                 mips_cps_core_bootcfg = NULL;
 135         }
 136
 137         /* Effectively disable SMP by declaring CPUs not present */
 138         for_each_possible_cpu(c) {
 139                 if (c == 0)
 140                         continue;
 141                 set_cpu_present(c, false);
 142         }
 143 }
 144
 145 static void boot_core(unsigned core)
 146 {
 147         u32 access;
 148
 149         /* Select the appropriate core */
 150         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
 151
 152         /* Set its reset vector */
 153         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 154
 155         /* Ensure its coherency is disabled */
 156         write_gcr_co_coherence(0);
 157
 158         /* Ensure the core can access the GCRs */
 159         access = read_gcr_access();
 160         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
 161         write_gcr_access(access);
 162
 163         if (mips_cpc_present()) {
 164                 /* Reset the core */
 165                 mips_cpc_lock_other(core);
 166                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 167                 mips_cpc_unlock_other();
 168         } else {
 169                 /* Take the core out of reset */
 170                 write_gcr_co_reset_release(0);
 171         }
 172
 173         /* The core is now powered up */
 174         bitmap_set(core_power, core, 1);
 175 }
 176
 177 static void remote_vpe_boot(void *dummy)
 178 {
 179         mips_cps_boot_vpes();
 180 }
 181
 182 static void cps_boot_secondary(int cpu, struct task_struct *idle)
 183 {
 184         unsigned core = cpu_data[cpu].core;
 185         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 186         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 187         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 188         unsigned int remote;
 189         int err;
 190
 191         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 192         vpe_cfg->sp = __KSTK_TOS(idle);
 193         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 194
 195         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 196
 197         if (!test_bit(core, core_power)) {
 198                 /* Boot a VPE on a powered down core */
 199                 boot_core(core);
 200                 return;
 201         }
 202
 203         if (core != current_cpu_data.core) {
 204                 /* Boot a VPE on another powered up core */
 205                 for (remote = 0; remote < NR_CPUS; remote++) {
 206                         if (cpu_data[remote].core != core)
 207                                 continue;
 208                         if (cpu_online(remote))
 209                                 break;
 210                 }
 211                 BUG_ON(remote >= NR_CPUS);
 212
 213                 err = smp_call_function_single(remote, remote_vpe_boot,
 214                                                NULL, 1);
 215                 if (err)
 216                         panic("Failed to call remote CPU\n");
 217                 return;
 218         }
 219
 220         BUG_ON(!cpu_has_mipsmt);
 221
 222         /* Boot a VPE on this core */
 223         mips_cps_boot_vpes();
 224 }
 225
 226 static void cps_init_secondary(void)
 227 {
 228         /* Disable MT - we only want to run 1 TC per VPE */
 229         if (cpu_has_mipsmt)
 230                 dmt();
 231
 232         change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
 233                                  STATUSF_IP6 | STATUSF_IP7);
 234 }
 235
 236 static void cps_smp_finish(void)
 237 {
 238         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 239
 240 #ifdef CONFIG_MIPS_MT_FPAFF
 241         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 242         if (cpu_has_fpu)
 243                 cpu_set(smp_processor_id(), mt_fpu_cpumask);
 244 #endif /* CONFIG_MIPS_MT_FPAFF */
 245
 246         local_irq_enable();
 247 }
 248
 249 static void cps_cpus_done(void)
 250 {
 251 }
 252
 253 static struct plat_smp_ops cps_smp_ops = {
 254         .smp_setup              = cps_smp_setup,
 255         .prepare_cpus           = cps_prepare_cpus,
 256         .boot_secondary         = cps_boot_secondary,
 257         .init_secondary         = cps_init_secondary,
 258         .smp_finish             = cps_smp_finish,
 259         .send_ipi_single        = gic_send_ipi_single,
 260         .send_ipi_mask          = gic_send_ipi_mask,
 261         .cpus_done              = cps_cpus_done,
 262 };
 263
 264 bool mips_cps_smp_in_use(void)
 265 {
 266         extern struct plat_smp_ops *mp_ops;
 267         return mp_ops == &cps_smp_ops;
 268 }
 269
 270 int register_cps_smp_ops(void)
 271 {
 272         if (!mips_cm_present()) {
 273                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 274                 return -ENODEV;
 275         }
 276
 277         /* check we have a GIC - we need one for IPIs */
 278         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
 279                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 280                 return -ENODEV;
 281         }
 282
 283         register_smp_ops(&cps_smp_ops);
 284         return 0;
 285 }