arch/mips/lantiq/xway/sysctrl.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  *  Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
   5  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   6  */
   7
   8 #include <linux/ioport.h>
   9 #include <linux/export.h>
  10 #include <linux/clkdev.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14
  15 #include <lantiq_soc.h>
  16
  17 #include "../clk.h"
  18 #include "../prom.h"
  19
  20 /* clock control register for legacy */
  21 #define CGU_IFCCR       0x0018
  22 #define CGU_IFCCR_VR9   0x0024
  23 /* system clock register for legacy */
  24 #define CGU_SYS         0x0010
  25 /* pci control register */
  26 #define CGU_PCICR       0x0034
  27 #define CGU_PCICR_VR9   0x0038
  28 /* ephy configuration register */
  29 #define CGU_EPHY        0x10
  30
  31 /* Legacy PMU register for ar9, ase, danube */
  32 /* power control register */
  33 #define PMU_PWDCR       0x1C
  34 /* power status register */
  35 #define PMU_PWDSR       0x20
  36 /* power control register */
  37 #define PMU_PWDCR1      0x24
  38 /* power status register */
  39 #define PMU_PWDSR1      0x28
  40 /* power control register */
  41 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  42 /* power status register */
  43 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  44
  45
  46 /* PMU register for ar10 and grx390 */
  47
  48 /* First register set */
  49 #define PMU_CLK_SR      0x20 /* status */
  50 #define PMU_CLK_CR_A    0x24 /* Enable */
  51 #define PMU_CLK_CR_B    0x28 /* Disable */
  52 /* Second register set */
  53 #define PMU_CLK_SR1     0x30 /* status */
  54 #define PMU_CLK_CR1_A   0x34 /* Enable */
  55 #define PMU_CLK_CR1_B   0x38 /* Disable */
  56 /* Third register set */
  57 #define PMU_ANA_SR      0x40 /* status */
  58 #define PMU_ANA_CR_A    0x44 /* Enable */
  59 #define PMU_ANA_CR_B    0x48 /* Disable */
  60
  61 /* Status */
  62 static u32 pmu_clk_sr[] = {
  63         PMU_CLK_SR,
  64         PMU_CLK_SR1,
  65         PMU_ANA_SR,
  66 };
  67
  68 /* Enable */
  69 static u32 pmu_clk_cr_a[] = {
  70         PMU_CLK_CR_A,
  71         PMU_CLK_CR1_A,
  72         PMU_ANA_CR_A,
  73 };
  74
  75 /* Disable */
  76 static u32 pmu_clk_cr_b[] = {
  77         PMU_CLK_CR_B,
  78         PMU_CLK_CR1_B,
  79         PMU_ANA_CR_B,
  80 };
  81
  82 #define PWDCR_EN_XRX(x)         (pmu_clk_cr_a[(x)])
  83 #define PWDCR_DIS_XRX(x)        (pmu_clk_cr_b[(x)])
  84 #define PWDSR_XRX(x)            (pmu_clk_sr[(x)])
  85
  86 /* clock gates that we can en/disable */
  87 #define PMU_USB0_P      BIT(0)
  88 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
  89 #define PMU_PCI         BIT(4)
  90 #define PMU_DMA         BIT(5)
  91 #define PMU_USB0        BIT(6)
  92 #define PMU_ASC0        BIT(7)
  93 #define PMU_EPHY        BIT(7)  /* ase */
  94 #define PMU_USIF        BIT(7) /* from vr9 until grx390 */
  95 #define PMU_SPI         BIT(8)
  96 #define PMU_DFE         BIT(9)
  97 #define PMU_EBU         BIT(10)
  98 #define PMU_STP         BIT(11)
  99 #define PMU_GPT         BIT(12)
 100 #define PMU_AHBS        BIT(13) /* vr9 */
 101 #define PMU_FPI         BIT(14)
 102 #define PMU_AHBM        BIT(15)
 103 #define PMU_SDIO        BIT(16) /* danube, ar9, vr9 */
 104 #define PMU_ASC1        BIT(17)
 105 #define PMU_PPE_QSB     BIT(18)
 106 #define PMU_PPE_SLL01   BIT(19)
 107 #define PMU_DEU         BIT(20)
 108 #define PMU_PPE_TC      BIT(21)
 109 #define PMU_PPE_EMA     BIT(22)
 110 #define PMU_PPE_DPLUM   BIT(23)
 111 #define PMU_PPE_DP      BIT(23)
 112 #define PMU_PPE_DPLUS   BIT(24)
 113 #define PMU_USB1_P      BIT(26)
 114 #define PMU_GPHY3       BIT(26) /* grx390 */
 115 #define PMU_USB1        BIT(27)
 116 #define PMU_SWITCH      BIT(28)
 117 #define PMU_PPE_TOP     BIT(29)
 118 #define PMU_GPHY0       BIT(29) /* ar10, xrx390 */
 119 #define PMU_GPHY        BIT(30)
 120 #define PMU_GPHY1       BIT(30) /* ar10, xrx390 */
 121 #define PMU_PCIE_CLK    BIT(31)
 122 #define PMU_GPHY2       BIT(31) /* ar10, xrx390 */
 123
 124 #define PMU1_PCIE_PHY   BIT(0)  /* vr9-specific,moved in ar10/grx390 */
 125 #define PMU1_PCIE_CTL   BIT(1)
 126 #define PMU1_PCIE_PDI   BIT(4)
 127 #define PMU1_PCIE_MSI   BIT(5)
 128 #define PMU1_CKE        BIT(6)
 129 #define PMU1_PCIE1_CTL  BIT(17)
 130 #define PMU1_PCIE1_PDI  BIT(20)
 131 #define PMU1_PCIE1_MSI  BIT(21)
 132 #define PMU1_PCIE2_CTL  BIT(25)
 133 #define PMU1_PCIE2_PDI  BIT(26)
 134 #define PMU1_PCIE2_MSI  BIT(27)
 135
 136 #define PMU_ANALOG_USB0_P       BIT(0)
 137 #define PMU_ANALOG_USB1_P       BIT(1)
 138 #define PMU_ANALOG_PCIE0_P      BIT(8)
 139 #define PMU_ANALOG_PCIE1_P      BIT(9)
 140 #define PMU_ANALOG_PCIE2_P      BIT(10)
 141 #define PMU_ANALOG_DSL_AFE      BIT(16)
 142 #define PMU_ANALOG_DCDC_2V5     BIT(17)
 143 #define PMU_ANALOG_DCDC_1VX     BIT(18)
 144 #define PMU_ANALOG_DCDC_1V0     BIT(19)
 145
 146 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 147 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 148
 149 static void __iomem *pmu_membase;
 150 void __iomem *ltq_cgu_membase;
 151 void __iomem *ltq_ebu_membase;
 152
 153 static u32 ifccr = CGU_IFCCR;
 154 static u32 pcicr = CGU_PCICR;
 155
 156 static DEFINE_SPINLOCK(g_pmu_lock);
 157
 158 /* legacy function kept alive to ease clkdev transition */
 159 void ltq_pmu_enable(unsigned int module)
 160 {
 161         int retry = 1000000;
 162
 163         spin_lock(&g_pmu_lock);
 164         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
 165         do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
 166         spin_unlock(&g_pmu_lock);
 167
 168         if (!retry)
 169                 panic("activating PMU module failed!");
 170 }
 171 EXPORT_SYMBOL(ltq_pmu_enable);
 172
 173 /* legacy function kept alive to ease clkdev transition */
 174 void ltq_pmu_disable(unsigned int module)
 175 {
 176         int retry = 1000000;
 177
 178         spin_lock(&g_pmu_lock);
 179         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 180         do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
 181         spin_unlock(&g_pmu_lock);
 182
 183         if (!retry)
 184                 pr_warn("deactivating PMU module failed!");
 185 }
 186 EXPORT_SYMBOL(ltq_pmu_disable);
 187
 188 /* enable a hw clock */
 189 static int cgu_enable(struct clk *clk)
 190 {
 191         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 192         return 0;
 193 }
 194
 195 /* disable a hw clock */
 196 static void cgu_disable(struct clk *clk)
 197 {
 198         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 199 }
 200
 201 /* enable a clock gate */
 202 static int pmu_enable(struct clk *clk)
 203 {
 204         int retry = 1000000;
 205
 206         if (of_machine_is_compatible("lantiq,ar10")
 207             || of_machine_is_compatible("lantiq,grx390")) {
 208                 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
 209                 do {} while (--retry &&
 210                              (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
 211
 212         } else {
 213                 spin_lock(&g_pmu_lock);
 214                 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 215                                 PWDCR(clk->module));
 216                 do {} while (--retry &&
 217                              (pmu_r32(PWDSR(clk->module)) & clk->bits));
 218                 spin_unlock(&g_pmu_lock);
 219         }
 220
 221         if (!retry)
 222                 panic("activating PMU module failed!");
 223
 224         return 0;
 225 }
 226
 227 /* disable a clock gate */
 228 static void pmu_disable(struct clk *clk)
 229 {
 230         int retry = 1000000;
 231
 232         if (of_machine_is_compatible("lantiq,ar10")
 233             || of_machine_is_compatible("lantiq,grx390")) {
 234                 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
 235                 do {} while (--retry &&
 236                              (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
 237         } else {
 238                 spin_lock(&g_pmu_lock);
 239                 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 240                                 PWDCR(clk->module));
 241                 do {} while (--retry &&
 242                              (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
 243                 spin_unlock(&g_pmu_lock);
 244         }
 245
 246         if (!retry)
 247                 pr_warn("deactivating PMU module failed!");
 248 }
 249
 250 /* the pci enable helper */
 251 static int pci_enable(struct clk *clk)
 252 {
 253         unsigned int val = ltq_cgu_r32(ifccr);
 254         /* set bus clock speed */
 255         if (of_machine_is_compatible("lantiq,ar9") ||
 256                         of_machine_is_compatible("lantiq,vr9")) {
 257                 val &= ~0x1f00000;
 258                 if (clk->rate == CLOCK_33M)
 259                         val |= 0xe00000;
 260                 else
 261                         val |= 0x700000; /* 62.5M */
 262         } else {
 263                 val &= ~0xf00000;
 264                 if (clk->rate == CLOCK_33M)
 265                         val |= 0x800000;
 266                 else
 267                         val |= 0x400000; /* 62.5M */
 268         }
 269         ltq_cgu_w32(val, ifccr);
 270         pmu_enable(clk);
 271         return 0;
 272 }
 273
 274 /* enable the external clock as a source */
 275 static int pci_ext_enable(struct clk *clk)
 276 {
 277         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 278         ltq_cgu_w32((1 << 30), pcicr);
 279         return 0;
 280 }
 281
 282 /* disable the external clock as a source */
 283 static void pci_ext_disable(struct clk *clk)
 284 {
 285         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 286         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 287 }
 288
 289 /* enable a clockout source */
 290 static int clkout_enable(struct clk *clk)
 291 {
 292         int i;
 293
 294         /* get the correct rate */
 295         for (i = 0; i < 4; i++) {
 296                 if (clk->rates[i] == clk->rate) {
 297                         int shift = 14 - (2 * clk->module);
 298                         int enable = 7 - clk->module;
 299                         unsigned int val = ltq_cgu_r32(ifccr);
 300
 301                         val &= ~(3 << shift);
 302                         val |= i << shift;
 303                         val |= enable;
 304                         ltq_cgu_w32(val, ifccr);
 305                         return 0;
 306                 }
 307         }
 308         return -1;
 309 }
 310
 311 /* manage the clock gates via PMU */
 312 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
 313                            unsigned int module, unsigned int bits)
 314 {
 315         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 316
 317         if (!clk)
 318                 return;
 319         clk->cl.dev_id = dev;
 320         clk->cl.con_id = con;
 321         clk->cl.clk = clk;
 322         clk->enable = pmu_enable;
 323         clk->disable = pmu_disable;
 324         clk->module = module;
 325         clk->bits = bits;
 326         if (deactivate) {
 327                 /*
 328                  * Disable it during the initialization. Module should enable
 329                  * when used
 330                  */
 331                 pmu_disable(clk);
 332         }
 333         clkdev_add(&clk->cl);
 334 }
 335
 336 /* manage the clock generator */
 337 static void clkdev_add_cgu(const char *dev, const char *con,
 338                                         unsigned int bits)
 339 {
 340         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 341
 342         if (!clk)
 343                 return;
 344         clk->cl.dev_id = dev;
 345         clk->cl.con_id = con;
 346         clk->cl.clk = clk;
 347         clk->enable = cgu_enable;
 348         clk->disable = cgu_disable;
 349         clk->bits = bits;
 350         clkdev_add(&clk->cl);
 351 }
 352
 353 /* pci needs its own enable function as the setup is a bit more complex */
 354 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 355
 356 static void clkdev_add_pci(void)
 357 {
 358         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 359         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 360
 361         /* main pci clock */
 362         if (clk) {
 363                 clk->cl.dev_id = "17000000.pci";
 364                 clk->cl.con_id = NULL;
 365                 clk->cl.clk = clk;
 366                 clk->rate = CLOCK_33M;
 367                 clk->rates = valid_pci_rates;
 368                 clk->enable = pci_enable;
 369                 clk->disable = pmu_disable;
 370                 clk->module = 0;
 371                 clk->bits = PMU_PCI;
 372                 clkdev_add(&clk->cl);
 373         }
 374
 375         /* use internal/external bus clock */
 376         if (clk_ext) {
 377                 clk_ext->cl.dev_id = "17000000.pci";
 378                 clk_ext->cl.con_id = "external";
 379                 clk_ext->cl.clk = clk_ext;
 380                 clk_ext->enable = pci_ext_enable;
 381                 clk_ext->disable = pci_ext_disable;
 382                 clkdev_add(&clk_ext->cl);
 383         }
 384 }
 385
 386 /* xway socs can generate clocks on gpio pins */
 387 static unsigned long valid_clkout_rates[4][5] = {
 388         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 389         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 390         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 391         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 392 };
 393
 394 static void clkdev_add_clkout(void)
 395 {
 396         int i;
 397
 398         for (i = 0; i < 4; i++) {
 399                 struct clk *clk;
 400                 char *name;
 401
 402                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 403                 if (!name)
 404                         continue;
 405                 sprintf(name, "clkout%d", i);
 406
 407                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 408                 if (!clk) {
 409                         kfree(name);
 410                         continue;
 411                 }
 412                 clk->cl.dev_id = "1f103000.cgu";
 413                 clk->cl.con_id = name;
 414                 clk->cl.clk = clk;
 415                 clk->rate = 0;
 416                 clk->rates = valid_clkout_rates[i];
 417                 clk->enable = clkout_enable;
 418                 clk->module = i;
 419                 clkdev_add(&clk->cl);
 420         }
 421 }
 422
 423 /* bring up all register ranges that we need for basic system control */
 424 void __init ltq_soc_init(void)
 425 {
 426         struct resource res_pmu, res_cgu, res_ebu;
 427         struct device_node *np_pmu =
 428                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 429         struct device_node *np_cgu =
 430                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 431         struct device_node *np_ebu =
 432                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 433
 434         /* check if all the core register ranges are available */
 435         if (!np_pmu || !np_cgu || !np_ebu)
 436                 panic("Failed to load core nodes from devicetree");
 437
 438         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 439                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 440                         of_address_to_resource(np_ebu, 0, &res_ebu))
 441                 panic("Failed to get core resources");
 442
 443         of_node_put(np_pmu);
 444         of_node_put(np_cgu);
 445         of_node_put(np_ebu);
 446
 447         if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
 448                                 res_pmu.name) ||
 449                 !request_mem_region(res_cgu.start, resource_size(&res_cgu),
 450                                 res_cgu.name) ||
 451                 !request_mem_region(res_ebu.start, resource_size(&res_ebu),
 452                                 res_ebu.name))
 453                 pr_err("Failed to request core resources");
 454
 455         pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
 456         ltq_cgu_membase = ioremap(res_cgu.start,
 457                                                 resource_size(&res_cgu));
 458         ltq_ebu_membase = ioremap(res_ebu.start,
 459                                                 resource_size(&res_ebu));
 460         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 461                 panic("Failed to remap core resources");
 462
 463         /* make sure to unprotect the memory region where flash is located */
 464         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 465
 466         /* add our generic xway clocks */
 467         clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
 468         clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
 469         clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
 470         clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
 471         clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
 472         clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
 473         clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
 474         clkdev_add_clkout();
 475
 476         /* add the soc dependent clocks */
 477         if (of_machine_is_compatible("lantiq,vr9")) {
 478                 ifccr = CGU_IFCCR_VR9;
 479                 pcicr = CGU_PCICR_VR9;
 480         } else {
 481                 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
 482         }
 483
 484         if (!of_machine_is_compatible("lantiq,ase"))
 485                 clkdev_add_pci();
 486
 487         if (of_machine_is_compatible("lantiq,grx390") ||
 488             of_machine_is_compatible("lantiq,ar10")) {
 489                 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
 490                 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
 491                 clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
 492                 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
 493                 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
 494                 /* rc 0 */
 495                 clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 496                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 497                 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
 498                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 499                 /* rc 1 */
 500                 clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
 501                 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
 502                 clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
 503                 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
 504         }
 505
 506         if (of_machine_is_compatible("lantiq,ase")) {
 507                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 508                         clkdev_add_static(CLOCK_266M, CLOCK_133M,
 509                                                 CLOCK_133M, CLOCK_266M);
 510                 else
 511                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
 512                                                 CLOCK_133M, CLOCK_133M);
 513                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
 514                 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
 515                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 516                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 517                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
 518                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
 519                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 520         } else if (of_machine_is_compatible("lantiq,grx390")) {
 521                 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
 522                                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
 523                 clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
 524                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
 525                 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
 526                 /* rc 2 */
 527                 clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
 528                 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
 529                 clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
 530                 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
 531                 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
 532                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 533                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 534         } else if (of_machine_is_compatible("lantiq,ar10")) {
 535                 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
 536                                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
 537                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
 538                 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
 539                 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
 540                                PMU_PPE_DP | PMU_PPE_TC);
 541                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 542                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 543                 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
 544                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 545         } else if (of_machine_is_compatible("lantiq,vr9")) {
 546                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 547                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 548                 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
 549                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
 550                 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
 551                 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
 552                 clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
 553                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 554                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 555                 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
 556                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 557                 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
 558
 559                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 560                 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
 561                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 562                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 563                                 PMU_PPE_QSB | PMU_PPE_TOP);
 564                 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
 565                 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
 566                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 567                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 568                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 569         } else if (of_machine_is_compatible("lantiq,ar9")) {
 570                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 571                                 ltq_ar9_fpi_hz(), CLOCK_250M);
 572                 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
 573                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
 574                 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
 575                 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
 576                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
 577                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 578                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 579                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 580                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 581         } else {
 582                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 583                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 584                 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
 585                 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
 586                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 587                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 588                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 589                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 590         }
 591 }