1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/mmzone.h>
4 #include <linux/nodemask.h>
5 #include <linux/spinlock.h>
7 #include <linux/atomic.h>
8 #include <asm/sn/types.h>
9 #include <asm/sn/addrs.h>
10 #include <asm/sn/nmi.h>
11 #include <asm/sn/arch.h>
12 #include <asm/sn/sn0/hub.h>
15 #define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
17 #define NODE_NUM_CPUS(n) CPUS_PER_NODE
20 typedef unsigned long machreg_t;
22 static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
25 * Let's see what else we need to do here. Set up sp, gp?
29 void cont_nmi_dump(void);
34 void install_cpu_nmi_handler(int slice)
38 nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
39 if (nmi_addr->call_addr)
41 nmi_addr->magic = NMI_MAGIC;
42 nmi_addr->call_addr = (void *)nmi_dump;
43 nmi_addr->call_addr_c =
44 (void *)(~((unsigned long)(nmi_addr->call_addr)));
45 nmi_addr->call_parm = 0;
49 * Copy the cpu registers which have been saved in the IP27prom format
50 * into the eframe format for the node under consideration.
53 void nmi_cpu_eframe_save(nasid_t nasid, int slice)
55 struct reg_struct *nr;
58 /* Get the pointer to the current cpu's register set. */
59 nr = (struct reg_struct *)
60 (TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
61 slice * IP27_NMI_KREGS_CPU_SIZE);
63 pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);
66 * Saved main processor registers
68 for (i = 0; i < 32; ) {
70 pr_emerg("$%2d :", i);
71 pr_cont(" %016lx", nr->gpr[i]);
78 pr_emerg("Hi : (value lost)\n");
79 pr_emerg("Lo : (value lost)\n");
84 pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc);
85 pr_emerg("%s\n", print_tainted());
86 pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
87 pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
88 pr_emerg("Status: %08lx ", nr->sr);
97 switch (nr->sr & ST0_KSU) {
102 pr_cont("SUPERVISOR ");
108 pr_cont("BAD_MODE ");
112 if (nr->sr & ST0_ERL)
114 if (nr->sr & ST0_EXL)
120 pr_emerg("Cause : %08lx\n", nr->cause);
121 pr_emerg("PrId : %08x\n", read_c0_prid());
122 pr_emerg("BadVA : %016lx\n", nr->badva);
123 pr_emerg("CErr : %016lx\n", nr->cache_err);
124 pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);
129 void nmi_dump_hub_irq(nasid_t nasid, int slice)
131 u64 mask0, mask1, pend0, pend1;
133 if (slice == 0) { /* Slice A */
134 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
135 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
136 } else { /* Slice B */
137 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
138 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
141 pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
142 pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
144 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
145 pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
150 * Copy the cpu registers which have been saved in the IP27prom format
151 * into the eframe format for the node under consideration.
153 void nmi_node_eframe_save(nasid_t nasid)
157 if (nasid == INVALID_NASID)
160 /* Save the registers into eframe for each cpu */
161 for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
162 nmi_cpu_eframe_save(nasid, slice);
163 nmi_dump_hub_irq(nasid, slice);
168 * Save the nmi cpu registers for all cpus in the system.
171 nmi_eframes_save(void)
175 for_each_online_node(nasid)
176 nmi_node_eframe_save(nasid);
182 #ifndef REAL_NMI_SIGNAL
183 static atomic_t nmied_cpus = ATOMIC_INIT(0);
185 atomic_inc(&nmied_cpus);
188 * Only allow 1 cpu to proceed
190 arch_spin_lock(&nmi_lock);
192 #ifdef REAL_NMI_SIGNAL
194 * Wait up to 15 seconds for the other cpus to respond to the NMI.
195 * If a cpu has not responded after 10 sec, send it 1 additional NMI.
196 * This is for 2 reasons:
197 * - sometimes a MMSC fail to NMI all cpus.
198 * - on 512p SN0 system, the MMSC will only send NMIs to
199 * half the cpus. Unfortunately, we don't know which cpus may be
200 * NMIed - it depends on how the site chooses to configure.
202 * Note: it has been measure that it takes the MMSC up to 2.3 secs to
203 * send NMIs to all cpus on a 256p system.
205 for (i=0; i < 1500; i++) {
206 for_each_online_node(node)
207 if (NODEPDA(node)->dump_count == 0)
209 if (node == MAX_NUMNODES)
212 for_each_online_node(node)
213 if (NODEPDA(node)->dump_count == 0) {
214 cpu = cpumask_first(cpumask_of_node(node));
215 for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
216 CPUMASK_SETB(nmied_cpus, cpu);
218 * cputonasid, cputoslice
221 SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
229 while (atomic_read(&nmied_cpus) != num_online_cpus());
233 * Save the nmi cpu registers for all cpu in the eframe format.
236 LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);