arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * MPC8610 HPCD Device Tree Source
   4  *
   5  * Copyright 2007-2008 Freescale Semiconductor Inc.
   6  */
   7
   8 /dts-v1/;
   9
  10 / {
  11         model = "MPC8610HPCD";
  12         compatible = "fsl,MPC8610HPCD";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         aliases {
  17                 serial0 = &serial0;
  18                 serial1 = &serial1;
  19                 pci0 = &pci0;
  20                 pci1 = &pci1;
  21                 pci2 = &pci2;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 PowerPC,8610@0 {
  29                         device_type = "cpu";
  30                         reg = <0>;
  31                         d-cache-line-size = <32>;
  32                         i-cache-line-size = <32>;
  33                         d-cache-size = <32768>;         // L1
  34                         i-cache-size = <32768>;         // L1
  35                         sleep = <&pmc 0x00008000 0      // core
  36                                  &pmc 0x00004000 0>;    // timebase
  37                         timebase-frequency = <0>;       // From uboot
  38                         bus-frequency = <0>;            // From uboot
  39                         clock-frequency = <0>;          // From uboot
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  46         };
  47
  48         localbus@e0005000 {
  49                 #address-cells = <2>;
  50                 #size-cells = <1>;
  51                 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
  52                 reg = <0xe0005000 0x1000>;
  53                 interrupts = <19 2>;
  54                 interrupt-parent = <&mpic>;
  55                 ranges = <0 0 0xf8000000 0x08000000
  56                           1 0 0xf0000000 0x08000000
  57                           2 0 0xe8400000 0x00008000
  58                           4 0 0xe8440000 0x00008000
  59                           5 0 0xe8480000 0x00008000
  60                           6 0 0xe84c0000 0x00008000
  61                           3 0 0xe8000000 0x00000020>;
  62                 sleep = <&pmc 0x08000000 0>;
  63
  64                 flash@0,0 {
  65                         compatible = "cfi-flash";
  66                         reg = <0 0 0x8000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69                 };
  70
  71                 flash@1,0 {
  72                         compatible = "cfi-flash";
  73                         reg = <1 0 0x8000000>;
  74                         bank-width = <2>;
  75                         device-width = <1>;
  76                 };
  77
  78                 flash@2,0 {
  79                         compatible = "fsl,mpc8610-fcm-nand",
  80                                      "fsl,elbc-fcm-nand";
  81                         reg = <2 0 0x8000>;
  82                 };
  83
  84                 flash@4,0 {
  85                         compatible = "fsl,mpc8610-fcm-nand",
  86                                      "fsl,elbc-fcm-nand";
  87                         reg = <4 0 0x8000>;
  88                 };
  89
  90                 flash@5,0 {
  91                         compatible = "fsl,mpc8610-fcm-nand",
  92                                      "fsl,elbc-fcm-nand";
  93                         reg = <5 0 0x8000>;
  94                 };
  95
  96                 flash@6,0 {
  97                         compatible = "fsl,mpc8610-fcm-nand",
  98                                      "fsl,elbc-fcm-nand";
  99                         reg = <6 0 0x8000>;
 100                 };
 101
 102                 board-control@3,0 {
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         compatible = "fsl,fpga-pixis";
 106                         reg = <3 0 0x20>;
 107                         ranges = <0 3 0 0x20>;
 108                         interrupt-parent = <&mpic>;
 109                         interrupts = <8 8>;
 110
 111                         sdcsr_pio: gpio-controller@a {
 112                                 #gpio-cells = <2>;
 113                                 compatible = "fsl,fpga-pixis-gpio-bank";
 114                                 reg = <0xa 1>;
 115                                 gpio-controller;
 116                         };
 117                 };
 118         };
 119
 120         soc@e0000000 {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 #interrupt-cells = <2>;
 124                 device_type = "soc";
 125                 compatible = "fsl,mpc8610-immr", "simple-bus";
 126                 ranges = <0x0 0xe0000000 0x00100000>;
 127                 bus-frequency = <0>;
 128
 129                 mcm-law@0 {
 130                         compatible = "fsl,mcm-law";
 131                         reg = <0x0 0x1000>;
 132                         fsl,num-laws = <10>;
 133                 };
 134
 135                 mcm@1000 {
 136                         compatible = "fsl,mpc8610-mcm", "fsl,mcm";
 137                         reg = <0x1000 0x1000>;
 138                         interrupts = <17 2>;
 139                         interrupt-parent = <&mpic>;
 140                 };
 141
 142                 i2c@3000 {
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         cell-index = <0>;
 146                         compatible = "fsl-i2c";
 147                         reg = <0x3000 0x100>;
 148                         interrupts = <43 2>;
 149                         interrupt-parent = <&mpic>;
 150                         dfsrr;
 151
 152                         cs4270:codec@4f {
 153                                 compatible = "cirrus,cs4270";
 154                                 reg = <0x4f>;
 155                                 /* MCLK source is a stand-alone oscillator */
 156                                 clock-frequency = <12288000>;
 157                         };
 158                 };
 159
 160                 i2c@3100 {
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         cell-index = <1>;
 164                         compatible = "fsl-i2c";
 165                         reg = <0x3100 0x100>;
 166                         interrupts = <43 2>;
 167                         interrupt-parent = <&mpic>;
 168                         sleep = <&pmc 0x00000004 0>;
 169                         dfsrr;
 170                 };
 171
 172                 serial0: serial@4500 {
 173                         cell-index = <0>;
 174                         device_type = "serial";
 175                         compatible = "fsl,ns16550", "ns16550";
 176                         reg = <0x4500 0x100>;
 177                         clock-frequency = <0>;
 178                         interrupts = <42 2>;
 179                         interrupt-parent = <&mpic>;
 180                         sleep = <&pmc 0x00000002 0>;
 181                 };
 182
 183                 serial1: serial@4600 {
 184                         cell-index = <1>;
 185                         device_type = "serial";
 186                         compatible = "fsl,ns16550", "ns16550";
 187                         reg = <0x4600 0x100>;
 188                         clock-frequency = <0>;
 189                         interrupts = <42 2>;
 190                         interrupt-parent = <&mpic>;
 191                         sleep = <&pmc 0x00000008 0>;
 192                 };
 193
 194                 spi@7000 {
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         compatible = "fsl,mpc8610-spi", "fsl,spi";
 198                         reg = <0x7000 0x40>;
 199                         cell-index = <0>;
 200                         interrupts = <59 2>;
 201                         interrupt-parent = <&mpic>;
 202                         mode = "cpu";
 203                         gpios = <&sdcsr_pio 7 0>;
 204                         sleep = <&pmc 0x00000800 0>;
 205
 206                         mmc-slot@0 {
 207                                 compatible = "fsl,mpc8610hpcd-mmc-slot",
 208                                              "mmc-spi-slot";
 209                                 reg = <0>;
 210                                 gpios = <&sdcsr_pio 0 1   /* nCD */
 211                                          &sdcsr_pio 1 0>; /*  WP */
 212                                 voltage-ranges = <3300 3300>;
 213                                 spi-max-frequency = <50000000>;
 214                         };
 215                 };
 216
 217                 display@2c000 {
 218                         compatible = "fsl,diu";
 219                         reg = <0x2c000 100>;
 220                         interrupts = <72 2>;
 221                         interrupt-parent = <&mpic>;
 222                         sleep = <&pmc 0x04000000 0>;
 223                 };
 224
 225                 mpic: interrupt-controller@40000 {
 226                         interrupt-controller;
 227                         #address-cells = <0>;
 228                         #interrupt-cells = <2>;
 229                         reg = <0x40000 0x40000>;
 230                         compatible = "chrp,open-pic";
 231                         device_type = "open-pic";
 232                 };
 233
 234                 msi@41600 {
 235                         compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
 236                         reg = <0x41600 0x80>;
 237                         msi-available-ranges = <0 0x100>;
 238                         interrupts = <
 239                                 0xe0 0
 240                                 0xe1 0
 241                                 0xe2 0
 242                                 0xe3 0
 243                                 0xe4 0
 244                                 0xe5 0
 245                                 0xe6 0
 246                                 0xe7 0>;
 247                         interrupt-parent = <&mpic>;
 248                 };
 249
 250                 global-utilities@e0000 {
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         compatible = "fsl,mpc8610-guts";
 254                         reg = <0xe0000 0x1000>;
 255                         ranges = <0 0xe0000 0x1000>;
 256                         fsl,has-rstcr;
 257
 258                         pmc: power@70 {
 259                                 compatible = "fsl,mpc8610-pmc",
 260                                              "fsl,mpc8641d-pmc";
 261                                 reg = <0x70 0x20>;
 262                         };
 263                 };
 264
 265                 wdt@e4000 {
 266                         compatible = "fsl,mpc8610-wdt";
 267                         reg = <0xe4000 0x100>;
 268                 };
 269
 270                 ssi@16000 {
 271                         compatible = "fsl,mpc8610-ssi";
 272                         cell-index = <0>;
 273                         reg = <0x16000 0x100>;
 274                         interrupt-parent = <&mpic>;
 275                         interrupts = <62 2>;
 276                         fsl,mode = "i2s-slave";
 277                         codec-handle = <&cs4270>;
 278                         fsl,playback-dma = <&dma00>;
 279                         fsl,capture-dma = <&dma01>;
 280                         fsl,fifo-depth = <8>;
 281                         sleep = <&pmc 0 0x08000000>;
 282                 };
 283
 284                 ssi@16100 {
 285                         compatible = "fsl,mpc8610-ssi";
 286                         status = "disabled";
 287                         cell-index = <1>;
 288                         reg = <0x16100 0x100>;
 289                         interrupt-parent = <&mpic>;
 290                         interrupts = <63 2>;
 291                         fsl,fifo-depth = <8>;
 292                         sleep = <&pmc 0 0x04000000>;
 293                 };
 294
 295                 dma@21300 {
 296                         #address-cells = <1>;
 297                         #size-cells = <1>;
 298                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 299                         cell-index = <0>;
 300                         reg = <0x21300 0x4>; /* DMA general status register */
 301                         ranges = <0x0 0x21100 0x200>;
 302                         sleep = <&pmc 0x00000400 0>;
 303
 304                         dma00: dma-channel@0 {
 305                                 compatible = "fsl,mpc8610-dma-channel",
 306                                         "fsl,ssi-dma-channel";
 307                                 cell-index = <0>;
 308                                 reg = <0x0 0x80>;
 309                                 interrupt-parent = <&mpic>;
 310                                 interrupts = <20 2>;
 311                         };
 312                         dma01: dma-channel@1 {
 313                                 compatible = "fsl,mpc8610-dma-channel",
 314                                         "fsl,ssi-dma-channel";
 315                                 cell-index = <1>;
 316                                 reg = <0x80 0x80>;
 317                                 interrupt-parent = <&mpic>;
 318                                 interrupts = <21 2>;
 319                         };
 320                         dma-channel@2 {
 321                                 compatible = "fsl,mpc8610-dma-channel",
 322                                         "fsl,eloplus-dma-channel";
 323                                 cell-index = <2>;
 324                                 reg = <0x100 0x80>;
 325                                 interrupt-parent = <&mpic>;
 326                                 interrupts = <22 2>;
 327                         };
 328                         dma-channel@3 {
 329                                 compatible = "fsl,mpc8610-dma-channel",
 330                                         "fsl,eloplus-dma-channel";
 331                                 cell-index = <3>;
 332                                 reg = <0x180 0x80>;
 333                                 interrupt-parent = <&mpic>;
 334                                 interrupts = <23 2>;
 335                         };
 336                 };
 337
 338                 dma@c300 {
 339                         #address-cells = <1>;
 340                         #size-cells = <1>;
 341                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 342                         cell-index = <1>;
 343                         reg = <0xc300 0x4>; /* DMA general status register */
 344                         ranges = <0x0 0xc100 0x200>;
 345                         sleep = <&pmc 0x00000200 0>;
 346
 347                         dma-channel@0 {
 348                                 compatible = "fsl,mpc8610-dma-channel",
 349                                         "fsl,eloplus-dma-channel";
 350                                 cell-index = <0>;
 351                                 reg = <0x0 0x80>;
 352                                 interrupt-parent = <&mpic>;
 353                                 interrupts = <76 2>;
 354                         };
 355                         dma-channel@1 {
 356                                 compatible = "fsl,mpc8610-dma-channel",
 357                                         "fsl,eloplus-dma-channel";
 358                                 cell-index = <1>;
 359                                 reg = <0x80 0x80>;
 360                                 interrupt-parent = <&mpic>;
 361                                 interrupts = <77 2>;
 362                         };
 363                         dma-channel@2 {
 364                                 compatible = "fsl,mpc8610-dma-channel",
 365                                         "fsl,eloplus-dma-channel";
 366                                 cell-index = <2>;
 367                                 reg = <0x100 0x80>;
 368                                 interrupt-parent = <&mpic>;
 369                                 interrupts = <78 2>;
 370                         };
 371                         dma-channel@3 {
 372                                 compatible = "fsl,mpc8610-dma-channel",
 373                                         "fsl,eloplus-dma-channel";
 374                                 cell-index = <3>;
 375                                 reg = <0x180 0x80>;
 376                                 interrupt-parent = <&mpic>;
 377                                 interrupts = <79 2>;
 378                         };
 379                 };
 380
 381         };
 382
 383         pci0: pci@e0008000 {
 384                 compatible = "fsl,mpc8610-pci";
 385                 device_type = "pci";
 386                 #interrupt-cells = <1>;
 387                 #size-cells = <2>;
 388                 #address-cells = <3>;
 389                 reg = <0xe0008000 0x1000>;
 390                 bus-range = <0 0>;
 391                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 392                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 393                 sleep = <&pmc 0x80000000 0>;
 394                 clock-frequency = <33333333>;
 395                 interrupt-parent = <&mpic>;
 396                 interrupts = <24 2>;
 397                 interrupt-map-mask = <0xf800 0 0 7>;
 398                 interrupt-map = <
 399                         /* IDSEL 0x11 */
 400                         0x8800 0 0 1 &mpic 4 1
 401                         0x8800 0 0 2 &mpic 5 1
 402                         0x8800 0 0 3 &mpic 6 1
 403                         0x8800 0 0 4 &mpic 7 1
 404
 405                         /* IDSEL 0x12 */
 406                         0x9000 0 0 1 &mpic 5 1
 407                         0x9000 0 0 2 &mpic 6 1
 408                         0x9000 0 0 3 &mpic 7 1
 409                         0x9000 0 0 4 &mpic 4 1
 410                         >;
 411         };
 412
 413         pci1: pcie@e000a000 {
 414                 compatible = "fsl,mpc8641-pcie";
 415                 device_type = "pci";
 416                 #interrupt-cells = <1>;
 417                 #size-cells = <2>;
 418                 #address-cells = <3>;
 419                 reg = <0xe000a000 0x1000>;
 420                 bus-range = <1 3>;
 421                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 422                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 423                 sleep = <&pmc 0x40000000 0>;
 424                 clock-frequency = <33333333>;
 425                 interrupt-parent = <&mpic>;
 426                 interrupts = <26 2>;
 427                 interrupt-map-mask = <0xf800 0 0 7>;
 428
 429                 interrupt-map = <
 430                         /* IDSEL 0x1b */
 431                         0xd800 0 0 1 &mpic 2 1
 432
 433                         /* IDSEL 0x1c*/
 434                         0xe000 0 0 1 &mpic 1 1
 435                         0xe000 0 0 2 &mpic 1 1
 436                         0xe000 0 0 3 &mpic 1 1
 437                         0xe000 0 0 4 &mpic 1 1
 438
 439                         /* IDSEL 0x1f */
 440                         0xf800 0 0 1 &mpic 3 2
 441                         0xf800 0 0 2 &mpic 0 1
 442                 >;
 443
 444                 pcie@0 {
 445                         reg = <0 0 0 0 0>;
 446                         #size-cells = <2>;
 447                         #address-cells = <3>;
 448                         device_type = "pci";
 449                         ranges = <0x02000000 0x0 0xa0000000
 450                                   0x02000000 0x0 0xa0000000
 451                                   0x0 0x10000000
 452                                   0x01000000 0x0 0x00000000
 453                                   0x01000000 0x0 0x00000000
 454                                   0x0 0x00100000>;
 455                         uli1575@0 {
 456                                 reg = <0 0 0 0 0>;
 457                                 #size-cells = <2>;
 458                                 #address-cells = <3>;
 459                                 ranges = <0x02000000 0x0 0xa0000000
 460                                           0x02000000 0x0 0xa0000000
 461                                           0x0 0x10000000
 462                                           0x01000000 0x0 0x00000000
 463                                           0x01000000 0x0 0x00000000
 464                                           0x0 0x00100000>;
 465
 466                                 isa@1e {
 467                                         device_type = "isa";
 468                                         #size-cells = <1>;
 469                                         #address-cells = <2>;
 470                                         reg = <0xf000 0 0 0 0>;
 471                                         ranges = <1 0 0x01000000 0 0
 472                                                   0x00001000>;
 473
 474                                         rtc@70 {
 475                                                 compatible = "pnpPNP,b00";
 476                                                 reg = <1 0x70 2>;
 477                                         };
 478                                 };
 479                         };
 480                 };
 481         };
 482
 483         pci2: pcie@e0009000 {
 484                 #address-cells = <3>;
 485                 #size-cells = <2>;
 486                 #interrupt-cells = <1>;
 487                 device_type = "pci";
 488                 compatible = "fsl,mpc8641-pcie";
 489                 reg = <0xe0009000 0x00001000>;
 490                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
 491                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
 492                 bus-range = <0 255>;
 493                 interrupt-map-mask = <0xf800 0 0 7>;
 494                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
 495                                  0x0000 0 0 2 &mpic 5 1
 496                                  0x0000 0 0 3 &mpic 6 1
 497                                  0x0000 0 0 4 &mpic 7 1>;
 498                 interrupt-parent = <&mpic>;
 499                 interrupts = <25 2>;
 500                 sleep = <&pmc 0x20000000 0>;
 501                 clock-frequency = <33333333>;
 502         };
 503 };