1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
4 #include <asm-generic/5level-fixup.h>
7 #include <linux/mmdebug.h>
12 * Common bits between hash and Radix page table
14 #define _PAGE_BIT_SWAP_TYPE 0
17 #define _PAGE_SHARED 0
19 #define _PAGE_EXEC 0x00001 /* execute permission */
20 #define _PAGE_WRITE 0x00002 /* write access allowed */
21 #define _PAGE_READ 0x00004 /* read access allowed */
22 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
23 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
24 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
25 #define _PAGE_SAO 0x00010 /* Strong access order */
26 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
27 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
28 #define _PAGE_DIRTY 0x00080 /* C: page changed */
29 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
33 #define _RPAGE_SW0 0x2000000000000000UL
34 #define _RPAGE_SW1 0x00800
35 #define _RPAGE_SW2 0x00400
36 #define _RPAGE_SW3 0x00200
37 #define _RPAGE_RSV1 0x1000000000000000UL
38 #define _RPAGE_RSV2 0x0800000000000000UL
39 #define _RPAGE_RSV3 0x0400000000000000UL
40 #define _RPAGE_RSV4 0x0200000000000000UL
42 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
43 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
46 * Top and bottom bits of RPN which can be used by hash
47 * translation mode, because we expect them to be zero
50 #define _RPAGE_RPN0 0x01000
51 #define _RPAGE_RPN1 0x02000
52 #define _RPAGE_RPN44 0x0100000000000000UL
53 #define _RPAGE_RPN43 0x0080000000000000UL
54 #define _RPAGE_RPN42 0x0040000000000000UL
55 #define _RPAGE_RPN41 0x0020000000000000UL
57 /* Max physical address bit as per radix table */
58 #define _RPAGE_PA_MAX 57
61 * Max physical address bit we will use for now.
63 * This is mostly a hardware limitation and for now Power9 has
66 * This is different from the number of physical bit required to address
67 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
68 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
69 * number of sections we can support (SECTIONS_SHIFT).
71 * This is different from Radix page table limitation above and
72 * should always be less than that. The limit is done such that
73 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
74 * for hash linux page table specific bits.
76 * In order to be compatible with future hardware generations we keep
77 * some offsets and limit this for now to 53
79 #define _PAGE_PA_MAX 53
81 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
82 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
83 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
84 #define __HAVE_ARCH_PTE_DEVMAP
87 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
88 * Instead of fixing all of them, add an alternate define which
89 * maps CI pte mapping.
91 #define _PAGE_NO_CACHE _PAGE_TOLERANT
93 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
94 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
95 * and every thing below PAGE_SHIFT;
97 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
99 * set of bits not changed in pmd_modify. Even though we have hash specific bits
100 * in here, on radix we expect them to be zero.
102 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
103 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
106 * user access blocked by key
108 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
109 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
110 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
111 _PAGE_RW | _PAGE_EXEC)
113 * No page size encoding in the linux PTE
115 #define _PAGE_PSIZE 0
117 * _PAGE_CHG_MASK masks of bits that are to be preserved across
120 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
121 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
124 * Mask of bits returned by pte_pgprot()
126 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
127 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
128 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
131 * We define 2 sets of base prot bits, one for basic pages (ie,
132 * cacheable kernel and user pages) and one for non cacheable
133 * pages. We always set _PAGE_COHERENT when SMP is enabled or
134 * the processor might need it for DMA coherency.
136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
137 #define _PAGE_BASE (_PAGE_BASE_NC)
139 /* Permission masks used to generate the __P and __S table,
141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
143 * Write permissions imply read permissions for now (we could make write-only
144 * pages on BookE but we don't bother for now). Execute permission control is
145 * possible on platforms that define _PAGE_EXEC
147 * Note due to the way vm flags are laid out, the bits are XWR
149 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
150 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
151 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
152 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
153 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
154 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
155 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
157 #define __P000 PAGE_NONE
158 #define __P001 PAGE_READONLY
159 #define __P010 PAGE_COPY
160 #define __P011 PAGE_COPY
161 #define __P100 PAGE_READONLY_X
162 #define __P101 PAGE_READONLY_X
163 #define __P110 PAGE_COPY_X
164 #define __P111 PAGE_COPY_X
166 #define __S000 PAGE_NONE
167 #define __S001 PAGE_READONLY
168 #define __S010 PAGE_SHARED
169 #define __S011 PAGE_SHARED
170 #define __S100 PAGE_READONLY_X
171 #define __S101 PAGE_READONLY_X
172 #define __S110 PAGE_SHARED_X
173 #define __S111 PAGE_SHARED_X
175 /* Permission masks used for kernel mappings */
176 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
177 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
179 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
180 _PAGE_NON_IDEMPOTENT)
181 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
182 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
183 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
186 * Protection used for kernel text. We want the debuggers to be able to
187 * set breakpoints anywhere, so don't write protect the kernel text
188 * on platforms where such control is possible.
190 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
191 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
192 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
194 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
197 /* Make modules code happy. We don't set RO yet */
198 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
199 #define PAGE_AGP (PAGE_KERNEL_NC)
205 extern unsigned long __pte_index_size;
206 extern unsigned long __pmd_index_size;
207 extern unsigned long __pud_index_size;
208 extern unsigned long __pgd_index_size;
209 extern unsigned long __pmd_cache_index;
210 #define PTE_INDEX_SIZE __pte_index_size
211 #define PMD_INDEX_SIZE __pmd_index_size
212 #define PUD_INDEX_SIZE __pud_index_size
213 #define PGD_INDEX_SIZE __pgd_index_size
214 #define PMD_CACHE_INDEX __pmd_cache_index
216 * Because of use of pte fragments and THP, size of page table
217 * are not always derived out of index size above.
219 extern unsigned long __pte_table_size;
220 extern unsigned long __pmd_table_size;
221 extern unsigned long __pud_table_size;
222 extern unsigned long __pgd_table_size;
223 #define PTE_TABLE_SIZE __pte_table_size
224 #define PMD_TABLE_SIZE __pmd_table_size
225 #define PUD_TABLE_SIZE __pud_table_size
226 #define PGD_TABLE_SIZE __pgd_table_size
228 extern unsigned long __pmd_val_bits;
229 extern unsigned long __pud_val_bits;
230 extern unsigned long __pgd_val_bits;
231 #define PMD_VAL_BITS __pmd_val_bits
232 #define PUD_VAL_BITS __pud_val_bits
233 #define PGD_VAL_BITS __pgd_val_bits
235 extern unsigned long __pte_frag_nr;
236 #define PTE_FRAG_NR __pte_frag_nr
237 extern unsigned long __pte_frag_size_shift;
238 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
239 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
241 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
242 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
243 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
244 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
246 /* PMD_SHIFT determines what a second-level page table entry can map */
247 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
248 #define PMD_SIZE (1UL << PMD_SHIFT)
249 #define PMD_MASK (~(PMD_SIZE-1))
251 /* PUD_SHIFT determines what a third-level page table entry can map */
252 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
253 #define PUD_SIZE (1UL << PUD_SHIFT)
254 #define PUD_MASK (~(PUD_SIZE-1))
256 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
257 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
258 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
259 #define PGDIR_MASK (~(PGDIR_SIZE-1))
261 /* Bits to mask out from a PMD to get to the PTE page */
262 #define PMD_MASKED_BITS 0xc0000000000000ffUL
263 /* Bits to mask out from a PUD to get to the PMD page */
264 #define PUD_MASKED_BITS 0xc0000000000000ffUL
265 /* Bits to mask out from a PGD to get to the PUD page */
266 #define PGD_MASKED_BITS 0xc0000000000000ffUL
268 extern unsigned long __vmalloc_start;
269 extern unsigned long __vmalloc_end;
270 #define VMALLOC_START __vmalloc_start
271 #define VMALLOC_END __vmalloc_end
273 extern unsigned long __kernel_virt_start;
274 extern unsigned long __kernel_virt_size;
275 extern unsigned long __kernel_io_start;
276 #define KERN_VIRT_START __kernel_virt_start
277 #define KERN_VIRT_SIZE __kernel_virt_size
278 #define KERN_IO_START __kernel_io_start
279 extern struct page *vmemmap;
280 extern unsigned long ioremap_bot;
281 extern unsigned long pci_io_base;
282 #endif /* __ASSEMBLY__ */
284 #include <asm/book3s/64/hash.h>
285 #include <asm/book3s/64/radix.h>
287 #ifdef CONFIG_PPC_64K_PAGES
288 #include <asm/book3s/64/pgtable-64k.h>
290 #include <asm/book3s/64/pgtable-4k.h>
293 #include <asm/barrier.h>
295 * The second half of the kernel virtual space is used for IO mappings,
296 * it's itself carved into the PIO region (ISA and PHB IO space) and
299 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
300 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
301 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
303 #define FULL_IO_SIZE 0x80000000ul
304 #define ISA_IO_BASE (KERN_IO_START)
305 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
306 #define PHB_IO_BASE (ISA_IO_END)
307 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
308 #define IOREMAP_BASE (PHB_IO_END)
309 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
311 /* Advertise special mapping type for AGP */
312 #define HAVE_PAGE_AGP
314 /* Advertise support for _PAGE_SPECIAL */
315 #define __HAVE_ARCH_PTE_SPECIAL
320 * This is the default implementation of various PTE accessors, it's
321 * used in all cases except Book3S with 64K pages where we have a
322 * concept of sub-pages
326 #define __real_pte(e,p) ((real_pte_t){(e)})
327 #define __rpte_to_pte(r) ((r).pte)
328 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
330 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
333 shift = mmu_psize_defs[psize].shift; \
335 #define pte_iterate_hashed_end() } while(0)
338 * We expect this to be called only for user addresses or kernel virtual
339 * addresses other than the linear mapping.
341 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
343 #endif /* __real_pte */
345 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
346 pte_t *ptep, unsigned long clr,
347 unsigned long set, int huge)
350 return radix__pte_update(mm, addr, ptep, clr, set, huge);
351 return hash__pte_update(mm, addr, ptep, clr, set, huge);
354 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
355 * We currently remove entries from the hashtable regardless of whether
356 * the entry was young or dirty.
358 * We should be more intelligent about this but for the moment we override
359 * these functions and force a tlb flush unconditionally
360 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
361 * function for both hash and radix.
363 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
364 unsigned long addr, pte_t *ptep)
368 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
370 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
371 return (old & _PAGE_ACCESSED) != 0;
374 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
375 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
378 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
382 static inline int __pte_write(pte_t pte)
384 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
387 #ifdef CONFIG_NUMA_BALANCING
388 #define pte_savedwrite pte_savedwrite
389 static inline bool pte_savedwrite(pte_t pte)
392 * Saved write ptes are prot none ptes that doesn't have
393 * privileged bit sit. We mark prot none as one which has
394 * present and pviliged bit set and RWX cleared. To mark
395 * protnone which used to have _PAGE_WRITE set we clear
396 * the privileged bit.
398 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
401 #define pte_savedwrite pte_savedwrite
402 static inline bool pte_savedwrite(pte_t pte)
408 static inline int pte_write(pte_t pte)
410 return __pte_write(pte) || pte_savedwrite(pte);
413 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
414 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
417 if (__pte_write(*ptep))
418 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
419 else if (unlikely(pte_savedwrite(*ptep)))
420 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
423 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
424 unsigned long addr, pte_t *ptep)
427 * We should not find protnone for hugetlb, but this complete the
430 if (__pte_write(*ptep))
431 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
432 else if (unlikely(pte_savedwrite(*ptep)))
433 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
436 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
437 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
438 unsigned long addr, pte_t *ptep)
440 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
444 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
445 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
447 pte_t *ptep, int full)
449 if (full && radix_enabled()) {
451 * Let's skip the DD1 style pte update here. We know that
452 * this is a full mm pte clear and hence can be sure there is
453 * no parallel set_pte.
455 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
457 return ptep_get_and_clear(mm, addr, ptep);
461 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
464 pte_update(mm, addr, ptep, ~0UL, 0, 0);
467 static inline int pte_dirty(pte_t pte)
469 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
472 static inline int pte_young(pte_t pte)
474 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
477 static inline int pte_special(pte_t pte)
479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
482 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
484 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
485 static inline bool pte_soft_dirty(pte_t pte)
487 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
490 static inline pte_t pte_mksoft_dirty(pte_t pte)
492 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
495 static inline pte_t pte_clear_soft_dirty(pte_t pte)
497 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
499 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
501 #ifdef CONFIG_NUMA_BALANCING
502 static inline int pte_protnone(pte_t pte)
504 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
505 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
508 #define pte_mk_savedwrite pte_mk_savedwrite
509 static inline pte_t pte_mk_savedwrite(pte_t pte)
512 * Used by Autonuma subsystem to preserve the write bit
513 * while marking the pte PROT_NONE. Only allow this
516 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
517 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
518 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
521 #define pte_clear_savedwrite pte_clear_savedwrite
522 static inline pte_t pte_clear_savedwrite(pte_t pte)
525 * Used by KSM subsystem to make a protnone pte readonly.
527 VM_BUG_ON(!pte_protnone(pte));
528 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
531 #define pte_clear_savedwrite pte_clear_savedwrite
532 static inline pte_t pte_clear_savedwrite(pte_t pte)
535 return __pte(pte_val(pte) & ~_PAGE_WRITE);
537 #endif /* CONFIG_NUMA_BALANCING */
539 static inline int pte_present(pte_t pte)
541 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
544 * Conversion functions: convert a page and protection to a page entry,
545 * and a page entry and page directory to the page they refer to.
547 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
550 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
552 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
556 static inline unsigned long pte_pfn(pte_t pte)
558 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
561 /* Generic modifiers for PTE bits */
562 static inline pte_t pte_wrprotect(pte_t pte)
564 if (unlikely(pte_savedwrite(pte)))
565 return pte_clear_savedwrite(pte);
566 return __pte(pte_val(pte) & ~_PAGE_WRITE);
569 static inline pte_t pte_mkclean(pte_t pte)
571 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
574 static inline pte_t pte_mkold(pte_t pte)
576 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
579 static inline pte_t pte_mkwrite(pte_t pte)
582 * write implies read, hence set both
584 return __pte(pte_val(pte) | _PAGE_RW);
587 static inline pte_t pte_mkdirty(pte_t pte)
589 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
592 static inline pte_t pte_mkyoung(pte_t pte)
594 return __pte(pte_val(pte) | _PAGE_ACCESSED);
597 static inline pte_t pte_mkspecial(pte_t pte)
599 return __pte(pte_val(pte) | _PAGE_SPECIAL);
602 static inline pte_t pte_mkhuge(pte_t pte)
607 static inline pte_t pte_mkdevmap(pte_t pte)
609 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
612 static inline int pte_devmap(pte_t pte)
614 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DEVMAP));
617 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
619 /* FIXME!! check whether this need to be a conditional */
620 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
623 static inline bool pte_user(pte_t pte)
625 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
628 /* Encode and de-code a swap entry */
629 #define MAX_SWAPFILES_CHECK() do { \
630 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
632 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
633 * We filter HPTEFLAGS on set_pte. \
635 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
636 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
639 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
641 #define SWP_TYPE_BITS 5
642 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
643 & ((1UL << SWP_TYPE_BITS) - 1))
644 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
645 #define __swp_entry(type, offset) ((swp_entry_t) { \
646 ((type) << _PAGE_BIT_SWAP_TYPE) \
647 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
649 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
650 * swap type and offset we get from swap and convert that to pte to find a
651 * matching pte in linux page table.
652 * Clear bits not found in swap entries here.
654 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
655 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
657 #ifdef CONFIG_MEM_SOFT_DIRTY
658 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
660 #define _PAGE_SWP_SOFT_DIRTY 0UL
661 #endif /* CONFIG_MEM_SOFT_DIRTY */
663 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
664 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
666 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
669 static inline bool pte_swp_soft_dirty(pte_t pte)
671 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
674 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
676 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
678 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
680 static inline bool check_pte_access(unsigned long access, unsigned long ptev)
683 * This check for _PAGE_RWX and _PAGE_PRESENT bits
688 * This check for access to privilege space
690 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
696 * Generic functions with hash/radix callbacks
699 static inline void __ptep_set_access_flags(struct mm_struct *mm,
700 pte_t *ptep, pte_t entry,
701 unsigned long address)
704 return radix__ptep_set_access_flags(mm, ptep, entry, address);
705 return hash__ptep_set_access_flags(ptep, entry);
708 #define __HAVE_ARCH_PTE_SAME
709 static inline int pte_same(pte_t pte_a, pte_t pte_b)
712 return radix__pte_same(pte_a, pte_b);
713 return hash__pte_same(pte_a, pte_b);
716 static inline int pte_none(pte_t pte)
719 return radix__pte_none(pte);
720 return hash__pte_none(pte);
723 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
724 pte_t *ptep, pte_t pte, int percpu)
727 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
728 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
731 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
733 #define pgprot_noncached pgprot_noncached
734 static inline pgprot_t pgprot_noncached(pgprot_t prot)
736 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
737 _PAGE_NON_IDEMPOTENT);
740 #define pgprot_noncached_wc pgprot_noncached_wc
741 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
743 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
747 #define pgprot_cached pgprot_cached
748 static inline pgprot_t pgprot_cached(pgprot_t prot)
750 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
753 #define pgprot_writecombine pgprot_writecombine
754 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
756 return pgprot_noncached_wc(prot);
759 * check a pte mapping have cache inhibited property
761 static inline bool pte_ci(pte_t pte)
763 unsigned long pte_v = pte_val(pte);
765 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
766 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
771 static inline void pmd_set(pmd_t *pmdp, unsigned long val)
776 static inline void pmd_clear(pmd_t *pmdp)
781 static inline int pmd_none(pmd_t pmd)
783 return !pmd_raw(pmd);
786 static inline int pmd_present(pmd_t pmd)
789 return !pmd_none(pmd);
792 static inline int pmd_bad(pmd_t pmd)
795 return radix__pmd_bad(pmd);
796 return hash__pmd_bad(pmd);
799 static inline void pud_set(pud_t *pudp, unsigned long val)
804 static inline void pud_clear(pud_t *pudp)
809 static inline int pud_none(pud_t pud)
811 return !pud_raw(pud);
814 static inline int pud_present(pud_t pud)
816 return !pud_none(pud);
819 extern struct page *pud_page(pud_t pud);
820 extern struct page *pmd_page(pmd_t pmd);
821 static inline pte_t pud_pte(pud_t pud)
823 return __pte_raw(pud_raw(pud));
826 static inline pud_t pte_pud(pte_t pte)
828 return __pud_raw(pte_raw(pte));
830 #define pud_write(pud) pte_write(pud_pte(pud))
832 static inline int pud_bad(pud_t pud)
835 return radix__pud_bad(pud);
836 return hash__pud_bad(pud);
840 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
841 static inline void pgd_set(pgd_t *pgdp, unsigned long val)
846 static inline void pgd_clear(pgd_t *pgdp)
851 static inline int pgd_none(pgd_t pgd)
853 return !pgd_raw(pgd);
856 static inline int pgd_present(pgd_t pgd)
858 return !pgd_none(pgd);
861 static inline pte_t pgd_pte(pgd_t pgd)
863 return __pte_raw(pgd_raw(pgd));
866 static inline pgd_t pte_pgd(pte_t pte)
868 return __pgd_raw(pte_raw(pte));
871 static inline int pgd_bad(pgd_t pgd)
874 return radix__pgd_bad(pgd);
875 return hash__pgd_bad(pgd);
878 extern struct page *pgd_page(pgd_t pgd);
880 /* Pointers in the page table tree are physical addresses */
881 #define __pgtable_ptr_val(ptr) __pa(ptr)
883 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
884 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
885 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
887 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
888 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
889 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
890 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
893 * Find an entry in a page-table-directory. We combine the address region
894 * (the high order N bits) and the pgd portion of the address.
897 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
899 #define pud_offset(pgdp, addr) \
900 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
901 #define pmd_offset(pudp,addr) \
902 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
903 #define pte_offset_kernel(dir,addr) \
904 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
906 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
907 #define pte_unmap(pte) do { } while(0)
909 /* to find an entry in a kernel page-table-directory */
910 /* This now only contains the vmalloc pages */
911 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
913 #define pte_ERROR(e) \
914 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
915 #define pmd_ERROR(e) \
916 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
917 #define pud_ERROR(e) \
918 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
919 #define pgd_ERROR(e) \
920 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
922 static inline int map_kernel_page(unsigned long ea, unsigned long pa,
925 if (radix_enabled()) {
926 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
927 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
928 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
930 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
932 return hash__map_kernel_page(ea, pa, flags);
935 static inline int __meminit vmemmap_create_mapping(unsigned long start,
936 unsigned long page_size,
940 return radix__vmemmap_create_mapping(start, page_size, phys);
941 return hash__vmemmap_create_mapping(start, page_size, phys);
944 #ifdef CONFIG_MEMORY_HOTPLUG
945 static inline void vmemmap_remove_mapping(unsigned long start,
946 unsigned long page_size)
949 return radix__vmemmap_remove_mapping(start, page_size);
950 return hash__vmemmap_remove_mapping(start, page_size);
953 struct page *realmode_pfn_to_page(unsigned long pfn);
955 static inline pte_t pmd_pte(pmd_t pmd)
957 return __pte_raw(pmd_raw(pmd));
960 static inline pmd_t pte_pmd(pte_t pte)
962 return __pmd_raw(pte_raw(pte));
965 static inline pte_t *pmdp_ptep(pmd_t *pmd)
969 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
970 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
971 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
972 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
973 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
974 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
975 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
976 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
977 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
978 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
979 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
981 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
982 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
983 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
984 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
985 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
987 #ifdef CONFIG_NUMA_BALANCING
988 static inline int pmd_protnone(pmd_t pmd)
990 return pte_protnone(pmd_pte(pmd));
992 #endif /* CONFIG_NUMA_BALANCING */
994 #define __HAVE_ARCH_PMD_WRITE
995 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
996 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
997 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
999 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1000 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1001 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1002 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1003 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1004 pmd_t *pmdp, pmd_t pmd);
1005 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1007 extern int hash__has_transparent_hugepage(void);
1008 static inline int has_transparent_hugepage(void)
1010 if (radix_enabled())
1011 return radix__has_transparent_hugepage();
1012 return hash__has_transparent_hugepage();
1014 #define has_transparent_hugepage has_transparent_hugepage
1016 static inline unsigned long
1017 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1018 unsigned long clr, unsigned long set)
1020 if (radix_enabled())
1021 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1022 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1025 static inline int pmd_large(pmd_t pmd)
1027 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
1030 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1032 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1035 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1036 * the below will work for radix too
1038 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1039 unsigned long addr, pmd_t *pmdp)
1043 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1045 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1046 return ((old & _PAGE_ACCESSED) != 0);
1049 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1050 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1053 if (__pmd_write((*pmdp)))
1054 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1055 else if (unlikely(pmd_savedwrite(*pmdp)))
1056 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
1059 static inline int pmd_trans_huge(pmd_t pmd)
1061 if (radix_enabled())
1062 return radix__pmd_trans_huge(pmd);
1063 return hash__pmd_trans_huge(pmd);
1066 #define __HAVE_ARCH_PMD_SAME
1067 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1069 if (radix_enabled())
1070 return radix__pmd_same(pmd_a, pmd_b);
1071 return hash__pmd_same(pmd_a, pmd_b);
1074 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1076 if (radix_enabled())
1077 return radix__pmd_mkhuge(pmd);
1078 return hash__pmd_mkhuge(pmd);
1081 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1082 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1083 unsigned long address, pmd_t *pmdp,
1084 pmd_t entry, int dirty);
1086 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1087 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1088 unsigned long address, pmd_t *pmdp);
1090 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1091 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1092 unsigned long addr, pmd_t *pmdp)
1094 if (radix_enabled())
1095 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
1096 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1099 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1100 unsigned long address, pmd_t *pmdp)
1102 if (radix_enabled())
1103 return radix__pmdp_collapse_flush(vma, address, pmdp);
1104 return hash__pmdp_collapse_flush(vma, address, pmdp);
1106 #define pmdp_collapse_flush pmdp_collapse_flush
1108 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1109 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1110 pmd_t *pmdp, pgtable_t pgtable)
1112 if (radix_enabled())
1113 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1114 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1117 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1118 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1121 if (radix_enabled())
1122 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1123 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1126 #define __HAVE_ARCH_PMDP_INVALIDATE
1127 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1130 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
1131 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
1132 unsigned long address, pmd_t *pmdp)
1134 if (radix_enabled())
1135 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
1136 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
1139 #define pmd_move_must_withdraw pmd_move_must_withdraw
1141 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1142 struct spinlock *old_pmd_ptl,
1143 struct vm_area_struct *vma)
1145 if (radix_enabled())
1148 * Archs like ppc64 use pgtable to store per pmd
1149 * specific information. So when we switch the pmd,
1150 * we should also withdraw and deposit the pgtable
1156 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1157 static inline bool arch_needs_pgtable_deposit(void)
1159 if (radix_enabled())
1165 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1167 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1170 static inline int pmd_devmap(pmd_t pmd)
1172 return pte_devmap(pmd_pte(pmd));
1175 static inline int pud_devmap(pud_t pud)
1180 static inline int pgd_devmap(pgd_t pgd)
1184 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1186 static inline const int pud_pfn(pud_t pud)
1189 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1190 * check so this should never be used. If it grows another user we
1191 * want to know about it.
1197 #endif /* __ASSEMBLY__ */
1198 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */