3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
39 #include <linux/memory.h>
40 #include <linux/nmi.h>
43 #include <asm/kdump.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
49 #include <asm/machdep.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/mmu_context.h>
68 #include <asm/code-patching.h>
69 #include <asm/kvm_ppc.h>
70 #include <asm/hugetlb.h>
71 #include <asm/epapr_hcalls.h>
74 #define DBG(fmt...) udbg_printf(fmt)
79 int spinning_secondaries;
82 /* Pick defaults since we might want to patch instructions
83 * before we've read this from the device tree.
85 struct ppc64_caches ppc64_caches = {
91 EXPORT_SYMBOL_GPL(ppc64_caches);
94 * These are used in binfmt_elf.c to put aux entries on the stack
95 * for each elf executable being started.
101 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
102 static void setup_tlb_core_data(void)
106 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
108 for_each_possible_cpu(cpu) {
109 int first = cpu_first_thread_sibling(cpu);
112 * If we boot via kdump on a non-primary thread,
113 * make sure we point at the thread that actually
116 if (cpu_first_thread_sibling(boot_cpuid) == first)
119 paca[cpu].tcd_ptr = &paca[first].tcd;
122 * If we have threads, we need either tlbsrx.
123 * or e6500 tablewalk mode, or else TLB handlers
124 * will be racy and could produce duplicate entries.
126 if (smt_enabled_at_boot >= 2 &&
127 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
128 book3e_htw_mode != PPC_HTW_E6500) {
129 /* Should we panic instead? */
130 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
136 static void setup_tlb_core_data(void)
143 static char *smt_enabled_cmdline;
145 /* Look for ibm,smt-enabled OF option */
146 static void check_smt_enabled(void)
148 struct device_node *dn;
149 const char *smt_option;
151 /* Default to enabling all threads */
152 smt_enabled_at_boot = threads_per_core;
154 /* Allow the command line to overrule the OF option */
155 if (smt_enabled_cmdline) {
156 if (!strcmp(smt_enabled_cmdline, "on"))
157 smt_enabled_at_boot = threads_per_core;
158 else if (!strcmp(smt_enabled_cmdline, "off"))
159 smt_enabled_at_boot = 0;
164 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
166 smt_enabled_at_boot =
167 min(threads_per_core, smt);
170 dn = of_find_node_by_path("/options");
172 smt_option = of_get_property(dn, "ibm,smt-enabled",
176 if (!strcmp(smt_option, "on"))
177 smt_enabled_at_boot = threads_per_core;
178 else if (!strcmp(smt_option, "off"))
179 smt_enabled_at_boot = 0;
187 /* Look for smt-enabled= cmdline option */
188 static int __init early_smt_enabled(char *p)
190 smt_enabled_cmdline = p;
193 early_param("smt-enabled", early_smt_enabled);
196 #define check_smt_enabled()
197 #endif /* CONFIG_SMP */
199 /** Fix up paca fields required for the boot cpu */
200 static void fixup_boot_paca(void)
202 /* The boot cpu is started */
203 get_paca()->cpu_start = 1;
204 /* Allow percpu accesses to work until we setup percpu data */
205 get_paca()->data_offset = 0;
208 static void cpu_ready_for_interrupts(void)
210 /* Set IR and DR in PACA MSR */
211 get_paca()->kernel_msr = MSR_KERNEL;
214 * Enable AIL if supported, and we are in hypervisor mode. If we are
215 * not in hypervisor mode, we enable relocation-on interrupts later
216 * in pSeries_setup_arch() using the H_SET_MODE hcall.
218 if (cpu_has_feature(CPU_FTR_HVMODE) &&
219 cpu_has_feature(CPU_FTR_ARCH_207S)) {
220 unsigned long lpcr = mfspr(SPRN_LPCR);
221 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
225 * Fixup HFSCR:TM based on CPU features. The bit is set by our
226 * early asm init because at that point we haven't updated our
227 * CPU features from firmware and device-tree. Here we have,
230 if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
231 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
235 * Early initialization entry point. This is called by head.S
236 * with MMU translation disabled. We rely on the "feature" of
237 * the CPU that ignores the top 2 bits of the address in real
238 * mode so we can access kernel globals normally provided we
239 * only toy with things in the RMO region. From here, we do
240 * some early parsing of the device-tree to setup out MEMBLOCK
241 * data structures, and allocate & initialize the hash table
242 * and segment tables so we can start running with translation
245 * It is this function which will call the probe() callback of
246 * the various platform types and copy the matching one to the
247 * global ppc_md structure. Your platform can eventually do
248 * some very early initializations from the probe() routine, but
249 * this is not recommended, be very careful as, for example, the
250 * device-tree is not accessible via normal means at this point.
253 void __init early_setup(unsigned long dt_ptr)
255 static __initdata struct paca_struct boot_paca;
257 /* -------- printk is _NOT_ safe to use here ! ------- */
259 /* Identify CPU type */
260 identify_cpu(0, mfspr(SPRN_PVR));
262 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
263 initialise_paca(&boot_paca, 0);
264 setup_paca(&boot_paca);
267 /* Initialize lockdep early or else spinlocks will blow */
270 /* -------- printk is now safe to use ------- */
272 /* Enable early debugging if any specified (see udbg.h) */
275 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
278 * Do early initialization using the flattened device
279 * tree, such as retrieving the physical memory map or
280 * calculating/retrieving the hash table size.
282 early_init_devtree(__va(dt_ptr));
284 epapr_paravirt_early_init();
286 /* Now we know the logical id of our boot cpu, setup the paca. */
287 setup_paca(&paca[boot_cpuid]);
290 /* Probe the machine type */
293 setup_kdump_trampoline();
295 DBG("Found, Initializing memory management...\n");
297 /* Initialize the hash table or TLB handling */
301 * At this point, we can let interrupts switch to virtual mode
302 * (the MMU has been setup), so adjust the MSR in the PACA to
303 * have IR and DR set and enable AIL if it exists
305 cpu_ready_for_interrupts();
307 /* Reserve large chunks of memory for use by CMA for KVM */
311 * Reserve any gigantic pages requested on the command line.
312 * memblock needs to have been initialized by the time this is
313 * called since this will reserve memory.
315 reserve_hugetlb_gpages();
317 DBG(" <- early_setup()\n");
319 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
321 * This needs to be done *last* (after the above DBG() even)
323 * Right after we return from this function, we turn on the MMU
324 * which means the real-mode access trick that btext does will
325 * no longer work, it needs to switch to using a real MMU
326 * mapping. This call will ensure that it does
329 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
333 void early_setup_secondary(void)
335 /* Mark interrupts enabled in PACA */
336 get_paca()->soft_enabled = 0;
338 /* Initialize the hash table or TLB handling */
339 early_init_mmu_secondary();
342 * At this point, we can let interrupts switch to virtual mode
343 * (the MMU has been setup), so adjust the MSR in the PACA to
344 * have IR and DR set.
346 cpu_ready_for_interrupts();
349 #endif /* CONFIG_SMP */
351 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
352 static bool use_spinloop(void)
354 if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
358 * When book3e boots from kexec, the ePAPR spin table does
361 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
364 void smp_release_cpus(void)
372 DBG(" -> smp_release_cpus()\n");
374 /* All secondary cpus are spinning on a common spinloop, release them
375 * all now so they can start to spin on their individual paca
376 * spinloops. For non SMP kernels, the secondary cpus never get out
377 * of the common spinloop.
380 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
382 *ptr = ppc_function_entry(generic_secondary_smp_init);
384 /* And wait a bit for them to catch up */
385 for (i = 0; i < 100000; i++) {
388 if (spinning_secondaries == 0)
392 DBG("spinning_secondaries = %d\n", spinning_secondaries);
394 DBG(" <- smp_release_cpus()\n");
396 #endif /* CONFIG_SMP || CONFIG_KEXEC */
399 * Initialize some remaining members of the ppc64_caches and systemcfg
401 * (at least until we get rid of them completely). This is mostly some
402 * cache informations about the CPU that will be used by cache flush
403 * routines and/or provided to userland
405 static void __init initialize_cache_info(void)
407 struct device_node *np;
408 unsigned long num_cpus = 0;
410 DBG(" -> initialize_cache_info()\n");
412 for_each_node_by_type(np, "cpu") {
416 * We're assuming *all* of the CPUs have the same
417 * d-cache and i-cache sizes... -Peter
420 const __be32 *sizep, *lsizep;
424 lsize = cur_cpu_spec->dcache_bsize;
425 sizep = of_get_property(np, "d-cache-size", NULL);
427 size = be32_to_cpu(*sizep);
428 lsizep = of_get_property(np, "d-cache-block-size",
430 /* fallback if block size missing */
432 lsizep = of_get_property(np,
436 lsize = be32_to_cpu(*lsizep);
437 if (sizep == NULL || lsizep == NULL)
438 DBG("Argh, can't find dcache properties ! "
439 "sizep: %p, lsizep: %p\n", sizep, lsizep);
441 ppc64_caches.dsize = size;
442 ppc64_caches.dline_size = lsize;
443 ppc64_caches.log_dline_size = __ilog2(lsize);
444 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
447 lsize = cur_cpu_spec->icache_bsize;
448 sizep = of_get_property(np, "i-cache-size", NULL);
450 size = be32_to_cpu(*sizep);
451 lsizep = of_get_property(np, "i-cache-block-size",
454 lsizep = of_get_property(np,
458 lsize = be32_to_cpu(*lsizep);
459 if (sizep == NULL || lsizep == NULL)
460 DBG("Argh, can't find icache properties ! "
461 "sizep: %p, lsizep: %p\n", sizep, lsizep);
463 ppc64_caches.isize = size;
464 ppc64_caches.iline_size = lsize;
465 ppc64_caches.log_iline_size = __ilog2(lsize);
466 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
470 DBG(" <- initialize_cache_info()\n");
475 * Do some initial setup of the system. The parameters are those which
476 * were passed in from the bootloader.
478 void __init setup_system(void)
480 DBG(" -> setup_system()\n");
482 /* Apply the CPUs-specific and firmware specific fixups to kernel
483 * text (nop out sections not relevant to this CPU or this firmware)
485 do_feature_fixups(cur_cpu_spec->cpu_features,
486 &__start___ftr_fixup, &__stop___ftr_fixup);
487 do_feature_fixups(cur_cpu_spec->mmu_features,
488 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
489 do_feature_fixups(powerpc_firmware_features,
490 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
491 do_lwsync_fixups(cur_cpu_spec->cpu_features,
492 &__start___lwsync_fixup, &__stop___lwsync_fixup);
496 * Unflatten the device-tree passed by prom_init or kexec
498 unflatten_device_tree();
501 * Fill the ppc64_caches & systemcfg structures with informations
502 * retrieved from the device-tree.
504 initialize_cache_info();
506 #ifdef CONFIG_PPC_RTAS
508 * Initialize RTAS if available
511 #endif /* CONFIG_PPC_RTAS */
514 * Check if we have an initrd provided via the device-tree
519 * Do some platform specific early initializations, that includes
520 * setting up the hash table pointers. It also sets up some interrupt-mapping
521 * related options that will be used by finish_device_tree()
523 if (ppc_md.init_early)
527 * We can discover serial ports now since the above did setup the
528 * hash table management for us, thus ioremap works. We do that early
529 * so that further code can be debugged
531 find_legacy_serial_ports();
534 * Register early console
536 register_early_udbg_console();
543 smp_setup_cpu_maps();
545 setup_tlb_core_data();
548 * Freescale Book3e parts spin in a loop provided by firmware,
549 * so smp_release_cpus() does nothing for them
551 #if defined(CONFIG_SMP)
552 /* Release secondary cpus out of their spinloops at 0x60 now that
553 * we can map physical -> logical CPU ids
558 pr_info("Starting Linux %s %s\n", init_utsname()->machine,
559 init_utsname()->version);
561 pr_info("-----------------------------------------------------\n");
562 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
563 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
565 if (ppc64_caches.dline_size != 0x80)
566 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size);
567 if (ppc64_caches.iline_size != 0x80)
568 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size);
570 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features);
571 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE);
572 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS);
573 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
574 cur_cpu_spec->cpu_user_features2);
575 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features);
576 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
578 #ifdef CONFIG_PPC_STD_MMU_64
580 pr_info("htab_address = 0x%p\n", htab_address);
582 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
585 if (PHYSICAL_START > 0)
586 pr_info("physical_start = 0x%llx\n",
587 (unsigned long long)PHYSICAL_START);
588 pr_info("-----------------------------------------------------\n");
590 DBG(" <- setup_system()\n");
593 /* This returns the limit below which memory accesses to the linear
594 * mapping are guarnateed not to cause a TLB or SLB miss. This is
595 * used to allocate interrupt or emergency stacks for which our
596 * exception entry path doesn't deal with being interrupted.
598 static u64 safe_stack_limit(void)
600 #ifdef CONFIG_PPC_BOOK3E
601 /* Freescale BookE bolts the entire linear mapping */
602 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
603 return linear_map_top;
604 /* Other BookE, we assume the first GB is bolted */
607 /* BookS, the first segment is bolted */
608 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
609 return 1UL << SID_SHIFT_1T;
610 return 1UL << SID_SHIFT;
614 static void __init irqstack_early_init(void)
616 u64 limit = safe_stack_limit();
620 * Interrupt stacks must be in the first segment since we
621 * cannot afford to take SLB misses on them.
623 for_each_possible_cpu(i) {
624 softirq_ctx[i] = (struct thread_info *)
625 __va(memblock_alloc_base(THREAD_SIZE,
626 THREAD_SIZE, limit));
627 hardirq_ctx[i] = (struct thread_info *)
628 __va(memblock_alloc_base(THREAD_SIZE,
629 THREAD_SIZE, limit));
633 #ifdef CONFIG_PPC_BOOK3E
634 static void __init exc_lvl_early_init(void)
639 for_each_possible_cpu(i) {
640 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
641 critirq_ctx[i] = (struct thread_info *)__va(sp);
642 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
644 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
645 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
646 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
648 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
649 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
650 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
653 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
654 patch_exception(0x040, exc_debug_debug_book3e);
657 #define exc_lvl_early_init()
661 * Stack space used when we detect a bad kernel stack pointer, and
662 * early in SMP boots before relocation is enabled. Exclusive emergency
663 * stack for machine checks.
665 static void __init emergency_stack_init(void)
671 * Emergency stacks must be under 256MB, we cannot afford to take
672 * SLB misses on them. The ABI also requires them to be 128-byte
675 * Since we use these as temporary stacks during secondary CPU
676 * bringup, we need to get at them in real mode. This means they
677 * must also be within the RMO region.
679 limit = min(safe_stack_limit(), ppc64_rma_size);
681 for_each_possible_cpu(i) {
683 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
685 paca[i].emergency_sp = __va(sp);
687 #ifdef CONFIG_PPC_BOOK3S_64
688 /* emergency stack for machine check exception handling. */
689 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
691 paca[i].mc_emergency_sp = __va(sp);
697 * Called into from start_kernel this initializes memblock, which is used
698 * to manage page allocation until mem_init is called.
700 void __init setup_arch(char **cmdline_p)
702 *cmdline_p = boot_command_line;
705 * Set cache line size based on type of cpu as a default.
706 * Systems with OF can look in the properties on the cpu node(s)
707 * for a possibly more accurate value.
709 dcache_bsize = ppc64_caches.dline_size;
710 icache_bsize = ppc64_caches.iline_size;
715 init_mm.start_code = (unsigned long)_stext;
716 init_mm.end_code = (unsigned long) _etext;
717 init_mm.end_data = (unsigned long) _edata;
718 init_mm.brk = klimit;
719 #ifdef CONFIG_PPC_64K_PAGES
720 init_mm.context.pte_frag = NULL;
722 #ifdef CONFIG_SPAPR_TCE_IOMMU
723 mm_iommu_init(&init_mm.context);
725 irqstack_early_init();
726 exc_lvl_early_init();
727 emergency_stack_init();
731 #ifdef CONFIG_DUMMY_CONSOLE
732 conswitchp = &dummy_con;
735 if (ppc_md.setup_arch)
740 /* Initialize the MMU context management stuff */
743 /* Interrupt code needs to be 64K-aligned */
744 if ((unsigned long)_stext & 0xffff)
745 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
746 (unsigned long)_stext);
750 #define PCPU_DYN_SIZE ()
752 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
754 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
755 __pa(MAX_DMA_ADDRESS));
758 static void __init pcpu_fc_free(void *ptr, size_t size)
760 free_bootmem(__pa(ptr), size);
763 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
765 if (cpu_to_node(from) == cpu_to_node(to))
766 return LOCAL_DISTANCE;
768 return REMOTE_DISTANCE;
771 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
772 EXPORT_SYMBOL(__per_cpu_offset);
774 void __init setup_per_cpu_areas(void)
776 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
783 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
784 * to group units. For larger mappings, use 1M atom which
785 * should be large enough to contain a number of units.
787 if (mmu_linear_psize == MMU_PAGE_4K)
788 atom_size = PAGE_SIZE;
792 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
793 pcpu_fc_alloc, pcpu_fc_free);
795 panic("cannot initialize percpu area (err=%d)", rc);
797 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
798 for_each_possible_cpu(cpu) {
799 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
800 paca[cpu].data_offset = __per_cpu_offset[cpu];
805 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
806 unsigned long memory_block_size_bytes(void)
808 if (ppc_md.memory_block_size)
809 return ppc_md.memory_block_size();
811 return MIN_MEMORY_BLOCK_SIZE;
815 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
816 struct ppc_pci_io ppc_pci_io;
817 EXPORT_SYMBOL(ppc_pci_io);
820 #ifdef CONFIG_HARDLOCKUP_DETECTOR
821 u64 hw_nmi_get_sample_period(int watchdog_thresh)
823 return ppc_proc_freq * watchdog_thresh;
827 * The hardlockup detector breaks PMU event based branches and is likely
828 * to get false positives in KVM guests, so disable it by default.
830 static int __init disable_hardlockup_detector(void)
832 hardlockup_detector_disable();
836 early_initcall(disable_hardlockup_detector);