1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Transactional memory support routines to reclaim and recheckpoint
4 * transactional process state.
6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
9 #include <asm/asm-offsets.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/ptrace.h>
15 #include <asm/export.h>
16 #include <asm/feature-fixups.h>
19 /* See fpu.S, this is borrowed from there */
20 #define __SAVE_32FPRS_VSRS(n,c,base) \
23 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
24 SAVE_32FPRS(n,base); \
26 2: SAVE_32VSRS(n,c,base); \
28 #define __REST_32FPRS_VSRS(n,c,base) \
31 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
32 REST_32FPRS(n,base); \
34 2: REST_32VSRS(n,c,base); \
37 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
38 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
40 #define SAVE_32FPRS_VSRS(n,c,base) \
41 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 #define REST_32FPRS_VSRS(n,c,base) \
43 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
45 /* Stack frame offsets for local variables. */
46 #define TM_FRAME_L0 TM_FRAME_SIZE-16
47 #define TM_FRAME_L1 TM_FRAME_SIZE-8
50 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
60 EXPORT_SYMBOL_GPL(tm_enable);
69 EXPORT_SYMBOL_GPL(tm_disable);
73 std r0, THREAD_TM_TFHAR(r3)
75 std r0, THREAD_TM_TEXASR(r3)
77 std r0, THREAD_TM_TFIAR(r3)
80 _GLOBAL(tm_restore_sprs)
81 ld r0, THREAD_TM_TFHAR(r3)
83 ld r0, THREAD_TM_TEXASR(r3)
85 ld r0, THREAD_TM_TFIAR(r3)
89 /* Passed an 8-bit failure cause as first argument. */
93 EXPORT_SYMBOL_GPL(tm_abort);
95 /* void tm_reclaim(struct thread_struct *thread,
98 * - Performs a full reclaim. This destroys outstanding
99 * transactions and updates thread->regs.tm_ckpt_* with the
100 * original checkpointed state. Note that thread->regs is
103 * Purpose is to both abort transactions of, and preserve the state of,
104 * a transactions at a context switch. We preserve/restore both sets of process
105 * state to restore them when the thread's scheduled again. We continue in
106 * userland as though nothing happened, but when the transaction is resumed
107 * they will abort back to the checkpointed state we save out here.
109 * Call with IRQs off, stacks get all out of sync for some periods in here!
117 stdu r1, -TM_FRAME_SIZE(r1)
119 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
121 std r3, STK_PARAM(R3)(r1)
124 /* We need to setup MSR for VSX register save instructions. */
129 ori r16, r16, MSR_EE /* IRQs hard off */
131 oris r15, r15, MSR_VEC@h
134 oris r15,r15, MSR_VSX@h
135 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
138 std r14, TM_FRAME_L0(r1)
140 /* Do sanity check on MSR to make sure we are suspended */
141 li r7, (MSR_TS_S)@higher
145 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
147 /* Stash the stack pointer away for use after reclaim */
150 /* Clear MSR RI since we are about to change r1, EE is already off. */
156 * At this point we can't take an SLB miss since we have MSR_RI
157 * off. Load only to/from the stack/paca which are in SLB bolted regions
158 * until we turn MSR RI back on.
160 * The moment we treclaim, ALL of our GPRs will switch
161 * to user register state. (FPRs, CCR etc. also!)
162 * Use an sprg and a tm_scratch in the PACA to shuffle.
164 TRECLAIM(R4) /* Cause in r4 */
166 /* ******************** GPRs ******************** */
167 /* Stash the checkpointed r13 away in the scratch SPR and get the real
173 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
176 std r1, PACATMSCRATCH(r13)
179 std r11, GPR11(r1) /* Temporary stash */
182 * Store r13 away so we can free up the scratch SPR for the SLB fault
183 * handler (needed once we start accessing the thread_struct).
188 /* Reset MSR RI so we can take SLB faults again */
192 /* Store the PPR in r11 and reset to decent value */
196 /* Now get some more GPRS free */
197 std r7, GPR7(r1) /* Temporary stash */
198 std r12, GPR12(r1) /* '' '' '' */
199 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
201 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
203 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
205 /* Make r7 look like an exception frame so that we
206 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
208 subi r7, r7, STACK_FRAME_OVERHEAD
210 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
211 SAVE_GPR(0, r7) /* user r0 */
212 SAVE_GPR(2, r7) /* user r2 */
213 SAVE_4GPRS(3, r7) /* user r3-r6 */
214 SAVE_GPR(8, r7) /* user r8 */
215 SAVE_GPR(9, r7) /* user r9 */
216 SAVE_GPR(10, r7) /* user r10 */
217 ld r3, PACATMSCRATCH(r13) /* user r1 */
218 ld r4, GPR7(r1) /* user r7 */
219 ld r5, GPR11(r1) /* user r11 */
220 ld r6, GPR12(r1) /* user r12 */
221 ld r8, GPR13(r1) /* user r13 */
228 SAVE_NVGPRS(r7) /* user r14-r31 */
230 /* ******************** NIP ******************** */
232 std r3, _NIP(r7) /* Returns to failhandler */
233 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
234 * but is used in signal return to 'wind back' to the abort handler.
237 /* ******************** CR,LR,CCR,MSR ********** */
249 /* ******************** TAR, DSCR ********** */
253 std r3, THREAD_TM_TAR(r12)
254 std r4, THREAD_TM_DSCR(r12)
256 /* MSR and flags: We don't change CRs, and we don't need to alter
261 /* ******************** FPR/VR/VSRs ************
262 * After reclaiming, capture the checkpointed FPRs/VRs.
264 * We enabled VEC/FP/VSX in the msr above, so we can execute these
269 /* Altivec (VEC/VMX/VR)*/
270 addi r7, r3, THREAD_CKVRSTATE
271 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
277 mfspr r0, SPRN_VRSAVE
278 std r0, THREAD_CKVRSAVE(r3)
280 /* Floating Point (FP) */
281 addi r7, r3, THREAD_CKFPSTATE
282 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
284 stfd fr0,FPSTATE_FPSCR(r7)
287 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
288 * been updated by the treclaim, to explain to userland the failure
291 mfspr r0, SPRN_TEXASR
294 std r0, THREAD_TM_TEXASR(r12)
295 std r3, THREAD_TM_TFHAR(r12)
296 std r4, THREAD_TM_TFIAR(r12)
298 /* AMR is checkpointed too, but is unsupported by Linux. */
300 /* Restore original MSR/IRQ state & clear TM mode */
301 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
304 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
309 addi r1, r1, TM_FRAME_SIZE
316 /* Load CPU's default DSCR */
317 ld r0, PACA_DSCR_DEFAULT(r13)
324 * void __tm_recheckpoint(struct thread_struct *thread)
325 * - Restore the checkpointed register state saved by tm_reclaim
326 * when we switch_to a process.
328 * Call with IRQs off, stacks get all out of sync for
329 * some periods in here!
331 _GLOBAL(__tm_recheckpoint)
337 stdu r1, -TM_FRAME_SIZE(r1)
339 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
340 * This is used for backing up the NVGPRs:
344 /* Load complete register state from ts_ckpt* registers */
346 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
348 /* Make r7 look like an exception frame so that we
349 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
351 subi r7, r7, STACK_FRAME_OVERHEAD
353 /* We need to setup MSR for FP/VMX/VSX register save instructions. */
357 #ifdef CONFIG_ALTIVEC
358 oris r5, r5, MSR_VEC@h
362 oris r5,r5, MSR_VSX@h
363 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
367 #ifdef CONFIG_ALTIVEC
369 * FP and VEC registers: These are recheckpointed from
370 * thread.ckfp_state and thread.ckvr_state respectively. The
371 * thread.fp_state[] version holds the 'live' (transactional)
372 * and will be loaded subsequently by any FPUnavailable trap.
374 addi r8, r3, THREAD_CKVRSTATE
378 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
379 ld r5, THREAD_CKVRSAVE(r3)
380 mtspr SPRN_VRSAVE, r5
383 addi r8, r3, THREAD_CKFPSTATE
384 lfd fr0, FPSTATE_FPSCR(r8)
386 REST_32FPRS_VSRS(0, R4, R8)
388 mtmsr r6 /* FP/Vec off again! */
392 /* ******************** CR,LR,CCR,MSR ********** */
401 /* ******************** TAR ******************** */
402 ld r4, THREAD_TM_TAR(r3)
405 /* Load up the PPR and DSCR in GPRs only at this stage */
406 ld r5, THREAD_TM_DSCR(r3)
407 ld r6, THREAD_TM_PPR(r3)
409 REST_GPR(0, r7) /* GPR0 */
410 REST_2GPRS(2, r7) /* GPR2-3 */
411 REST_GPR(4, r7) /* GPR4 */
412 REST_4GPRS(8, r7) /* GPR8-11 */
413 REST_2GPRS(12, r7) /* GPR12-13 */
415 REST_NVGPRS(r7) /* GPR14-31 */
417 /* Load up PPR and DSCR here so we don't run with user values for long
422 /* Do final sanity check on TEXASR to make sure FS is set. Do this
423 * here before we load up the userspace r1 so any bugs we hit will get
425 mfspr r5, SPRN_TEXASR
430 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
432 /* Do final sanity check on MSR to make sure we are not transactional
436 li r5, (MSR_TS_MASK)@higher
440 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
449 * Store r1 and r5 on the stack so that we can access them
450 * after we clear MSR RI.
460 /* Clear MSR RI since we are about to change r1. EE is already off */
466 * At this point we can't take an SLB miss since we have MSR_RI
467 * off. Load only to/from the stack/paca which are in SLB bolted regions
468 * until we turn MSR RI back on.
475 /* Commit register state as checkpointed state: */
480 /* Our transactional state has now changed.
482 * Now just get out of here. Transactional (current) state will be
483 * updated once restore is called on the return path in the _switch-ed
490 /* R1 is restored, so we are recoverable again. EE is still off */
496 addi r1, r1, TM_FRAME_SIZE
503 /* Load CPU's default DSCR */
504 ld r0, PACA_DSCR_DEFAULT(r13)
509 /* ****************************************************************** */