2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
36 /* Values in HSTATE_NAPPING(r13) */
37 #define NAPPING_CEDE 1
38 #define NAPPING_NOVCPU 2
41 * Call kvmppc_hv_entry in real mode.
42 * Must be called with interrupts hard-disabled.
46 * LR = return address to continue at after eventually re-enabling MMU
48 _GLOBAL(kvmppc_hv_entry_trampoline)
50 std r0, PPC_LR_STKOFF(r1)
53 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
58 mtmsrd r0,1 /* clear RI in MSR */
64 ld r4, HSTATE_KVM_VCPU(r13)
67 /* Back from guest - restore host state and return to caller */
70 /* Restore host DABR and DABRX */
71 ld r5,HSTATE_DABR(r13)
75 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
81 /* Reload the host's PMU registers */
82 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
83 lbz r4, LPPACA_PMCINUSE(r3)
85 beq 23f /* skip if not */
86 lwz r3, HSTATE_PMC(r13)
87 lwz r4, HSTATE_PMC + 4(r13)
88 lwz r5, HSTATE_PMC + 8(r13)
89 lwz r6, HSTATE_PMC + 12(r13)
90 lwz r8, HSTATE_PMC + 16(r13)
91 lwz r9, HSTATE_PMC + 20(r13)
93 lwz r10, HSTATE_PMC + 24(r13)
94 lwz r11, HSTATE_PMC + 28(r13)
95 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
105 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
106 ld r3, HSTATE_MMCR(r13)
107 ld r4, HSTATE_MMCR + 8(r13)
108 ld r5, HSTATE_MMCR + 16(r13)
116 * Reload DEC. HDEC interrupts were disabled when
117 * we reloaded the host's LPCR value.
119 ld r3, HSTATE_DECEXP(r13)
125 * For external and machine check interrupts, we need
126 * to call the Linux handler to process the interrupt.
127 * We do that by jumping to absolute address 0x500 for
128 * external interrupts, or the machine_check_fwnmi label
129 * for machine checks (since firmware might have patched
130 * the vector area at 0x200). The [h]rfid at the end of the
131 * handler will return to the book3s_hv_interrupts.S code.
132 * For other interrupts we do the rfid to get back
133 * to the book3s_hv_interrupts.S code here.
135 ld r8, 112+PPC_LR_STKOFF(r1)
137 ld r7, HSTATE_HOST_MSR(r13)
139 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
140 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
143 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
145 /* RFI into the highmem handler, or branch to interrupt handler */
149 mtmsrd r6, 1 /* Clear RI in MSR */
152 beqa 0x500 /* external interrupt (PPC970) */
153 beq cr1, 13f /* machine check */
156 /* On POWER7, we have external interrupts set to use HSRR0/1 */
157 11: mtspr SPRN_HSRR0, r8
161 13: b machine_check_fwnmi
164 kvmppc_primary_no_guest:
165 /* We handle this much like a ceded vcpu */
166 /* set our bit in napping_threads */
167 ld r5, HSTATE_KVM_VCORE(r13)
168 lbz r7, HSTATE_PTID(r13)
171 addi r6, r5, VCORE_NAPPING_THREADS
176 /* order napping_threads update vs testing entry_exit_count */
179 lwz r7, VCORE_ENTRY_EXIT(r5)
181 bge kvm_novcpu_exit /* another thread already exiting */
182 li r3, NAPPING_NOVCPU
183 stb r3, HSTATE_NAPPING(r13)
185 stb r3, HSTATE_HWTHREAD_REQ(r13)
190 ld r1, HSTATE_HOST_R1(r13)
191 ld r5, HSTATE_KVM_VCORE(r13)
193 stb r0, HSTATE_NAPPING(r13)
194 stb r0, HSTATE_HWTHREAD_REQ(r13)
196 /* see if any other thread is already exiting */
198 lwz r0, VCORE_ENTRY_EXIT(r5)
202 /* clear our bit in napping_threads */
203 lbz r7, HSTATE_PTID(r13)
206 addi r6, r5, VCORE_NAPPING_THREADS
212 /* Check the wake reason in SRR1 to see why we got here */
214 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
215 cmpwi r3, 4 /* was it an external interrupt? */
216 bne kvm_novcpu_exit /* if not, exit the guest */
218 /* extern interrupt - read and handle it */
219 li r12, BOOK3S_INTERRUPT_EXTERNAL
225 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
226 ld r4, HSTATE_KVM_VCPU(r13)
234 * We come in here when wakened from nap mode.
235 * Relocation is off and most register values are lost.
236 * r13 points to the PACA.
238 .globl kvm_start_guest
242 li r0,KVM_HWTHREAD_IN_KVM
243 stb r0,HSTATE_HWTHREAD_STATE(r13)
245 /* NV GPR values from power7_idle() will no longer be valid */
247 stb r0,PACA_NAPSTATELOST(r13)
249 /* were we napping due to cede? */
250 lbz r0,HSTATE_NAPPING(r13)
251 cmpwi r0,NAPPING_CEDE
253 cmpwi r0,NAPPING_NOVCPU
254 beq kvm_novcpu_wakeup
256 ld r1,PACAEMERGSP(r13)
257 subi r1,r1,STACK_FRAME_OVERHEAD
260 * We weren't napping due to cede, so this must be a secondary
261 * thread being woken up to run a guest, or being woken up due
262 * to a stray IPI. (Or due to some machine check or hypervisor
263 * maintenance interrupt while the core is in KVM.)
266 /* Check the wake reason in SRR1 to see why we got here */
268 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
269 cmpwi r3,4 /* was it an external interrupt? */
271 ld r5,HSTATE_XICS_PHYS(r13)
272 li r7,XICS_XIRR /* if it was an external interrupt, */
273 lwzcix r8,r5,r7 /* get and ack the interrupt */
275 clrldi. r9,r8,40 /* get interrupt source ID. */
276 beq 28f /* none there? */
277 cmpwi r9,XICS_IPI /* was it an IPI? */
281 stbcix r0,r5,r6 /* clear IPI */
282 stwcix r8,r5,r7 /* EOI the interrupt */
283 sync /* order loading of vcpu after that */
285 /* get vcpu pointer, NULL if we have no vcpu to run */
286 ld r4,HSTATE_KVM_VCPU(r13)
288 /* if we have no vcpu to run, go back to sleep */
292 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
294 28: /* SRR1 said external but ICP said nope?? */
296 29: /* External non-IPI interrupt to offline secondary thread? help?? */
297 stw r8,HSTATE_SAVED_XIRR(r13)
301 /* Set HSTATE_DSCR(r13) to something sensible */
302 LOAD_REG_ADDR(r6, dscr_default)
304 std r6, HSTATE_DSCR(r13)
308 /* Back from the guest, go back to nap */
309 /* Clear our vcpu pointer so we don't come back in early */
311 std r0, HSTATE_KVM_VCPU(r13)
313 /* Clear any pending IPI - we're an offline thread */
314 ld r5, HSTATE_XICS_PHYS(r13)
316 lwzcix r3, r5, r7 /* ack any pending interrupt */
317 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
322 stbcix r0, r5, r6 /* clear the IPI */
323 stwcix r3, r5, r7 /* EOI it */
326 /* increment the nap count and then go to nap mode */
327 ld r4, HSTATE_KVM_VCORE(r13)
328 addi r4, r4, VCORE_NAP_COUNT
329 lwsync /* make previous updates visible */
336 li r0, KVM_HWTHREAD_IN_NAP
337 stb r0, HSTATE_HWTHREAD_STATE(r13)
341 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
344 std r0, HSTATE_SCRATCH0(r13)
346 ld r0, HSTATE_SCRATCH0(r13)
352 /******************************************************************************
356 *****************************************************************************/
358 .global kvmppc_hv_entry
363 * R4 = vcpu pointer (or NULL)
367 * all other volatile GPRS = free
370 std r0, PPC_LR_STKOFF(r1)
373 /* Save R1 in the PACA */
374 std r1, HSTATE_HOST_R1(r13)
376 li r6, KVM_GUEST_MODE_HOST_HV
377 stb r6, HSTATE_IN_GUEST(r13)
387 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
389 * POWER7 host -> guest partition switch code.
390 * We don't have to lock against concurrent tlbies,
391 * but we do have to coordinate across hardware threads.
393 /* Increment entry count iff exit count is zero. */
394 ld r5,HSTATE_KVM_VCORE(r13)
395 addi r9,r5,VCORE_ENTRY_EXIT
397 cmpwi r3,0x100 /* any threads starting to exit? */
398 bge secondary_too_late /* if so we're too late to the party */
403 /* Primary thread switches to guest partition. */
404 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
405 lbz r6,HSTATE_PTID(r13)
410 li r0,LPID_RSVD /* switch to reserved LPID */
413 mtspr SPRN_SDR1,r6 /* switch to partition page table */
417 /* See if we need to flush the TLB */
418 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
419 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
420 srdi r6,r6,6 /* doubleword number */
421 sldi r6,r6,3 /* address offset */
423 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
429 23: ldarx r7,0,r6 /* if set, clear the bit */
433 li r6,128 /* and flush the TLB */
435 li r7,0x800 /* IS field = 0b10 */
442 /* Add timebase offset onto timebase */
443 22: ld r8,VCORE_TB_OFFSET(r5)
446 mftb r6 /* current host timebase */
448 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
449 mftb r7 /* check if lower 24 bits overflowed */
454 addis r8,r8,0x100 /* if so, increment upper 40 bits */
457 /* Load guest PCR value to select appropriate compat mode */
458 37: ld r7, VCORE_PCR(r5)
465 /* DPDES is shared between threads */
466 ld r8, VCORE_DPDES(r5)
468 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
471 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
474 /* Secondary threads wait for primary to have done partition switch */
475 20: lbz r0,VCORE_IN_GUEST(r5)
479 /* Set LPCR and RMOR. */
480 10: ld r8,VCORE_LPCR(r5)
486 /* Check if HDEC expires soon */
488 cmpwi r3,512 /* 1 microsecond */
489 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
494 * PPC970 host -> guest partition switch code.
495 * We have to lock against concurrent tlbies,
496 * using native_tlbie_lock to lock against host tlbies
497 * and kvm->arch.tlbie_lock to lock against guest tlbies.
498 * We also have to invalidate the TLB since its
499 * entries aren't tagged with the LPID.
501 30: ld r5,HSTATE_KVM_VCORE(r13)
502 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
504 /* first take native_tlbie_lock */
507 .tc native_tlbie_lock[TC],native_tlbie_lock
509 ld r3,toc_tlbie_lock@toc(2)
510 #ifdef __BIG_ENDIAN__
511 lwz r8,PACA_LOCK_TOKEN(r13)
513 lwz r8,PACAPACAINDEX(r13)
522 ld r5,HSTATE_KVM_VCORE(r13)
523 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
525 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
529 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
532 stw r0,0(r3) /* drop native_tlbie_lock */
534 /* invalidate the whole TLB */
543 /* Take the guest's tlbie_lock */
544 addi r3,r9,KVM_TLBIE_LOCK
552 mtspr SPRN_SDR1,r6 /* switch to partition page table */
554 /* Set up HID4 with the guest's LPID etc. */
559 /* drop the guest's tlbie_lock */
563 /* Check if HDEC expires soon */
566 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
569 /* Enable HDEC interrupts */
572 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
582 /* Do we have a guest vcpu to run? */
584 beq kvmppc_primary_no_guest
587 /* Load up guest SLB entries */
588 lwz r5,VCPU_SLB_MAX(r4)
593 1: ld r8,VCPU_SLB_E(r6)
596 addi r6,r6,VCPU_SLB_SIZE
599 /* Increment yield count if they have a VPA */
603 lwz r5, LPPACA_YIELDCOUNT(r3)
605 stw r5, LPPACA_YIELDCOUNT(r3)
607 stb r6, VCPU_VPA_DIRTY(r4)
611 /* Save purr/spurr */
614 std r5,HSTATE_PURR(r13)
615 std r6,HSTATE_SPURR(r13)
620 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
623 /* Set partition DABR */
624 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
629 BEGIN_FTR_SECTION_NESTED(89)
631 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
632 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
634 /* Load guest PMU registers */
635 /* R4 is live here (vcpu pointer) */
637 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
638 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
640 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
641 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
642 lwz r6, VCPU_PMC + 8(r4)
643 lwz r7, VCPU_PMC + 12(r4)
644 lwz r8, VCPU_PMC + 16(r4)
645 lwz r9, VCPU_PMC + 20(r4)
647 lwz r10, VCPU_PMC + 24(r4)
648 lwz r11, VCPU_PMC + 28(r4)
649 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
659 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
661 ld r5, VCPU_MMCR + 8(r4)
662 ld r6, VCPU_MMCR + 16(r4)
670 ld r5, VCPU_MMCR + 24(r4)
672 lwz r7, VCPU_PMC + 24(r4)
673 lwz r8, VCPU_PMC + 28(r4)
674 ld r9, VCPU_MMCR + 32(r4)
680 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
684 /* Load up FP, VMX and VSX registers */
687 ld r14, VCPU_GPR(R14)(r4)
688 ld r15, VCPU_GPR(R15)(r4)
689 ld r16, VCPU_GPR(R16)(r4)
690 ld r17, VCPU_GPR(R17)(r4)
691 ld r18, VCPU_GPR(R18)(r4)
692 ld r19, VCPU_GPR(R19)(r4)
693 ld r20, VCPU_GPR(R20)(r4)
694 ld r21, VCPU_GPR(R21)(r4)
695 ld r22, VCPU_GPR(R22)(r4)
696 ld r23, VCPU_GPR(R23)(r4)
697 ld r24, VCPU_GPR(R24)(r4)
698 ld r25, VCPU_GPR(R25)(r4)
699 ld r26, VCPU_GPR(R26)(r4)
700 ld r27, VCPU_GPR(R27)(r4)
701 ld r28, VCPU_GPR(R28)(r4)
702 ld r29, VCPU_GPR(R29)(r4)
703 ld r30, VCPU_GPR(R30)(r4)
704 ld r31, VCPU_GPR(R31)(r4)
707 /* Switch DSCR to guest value */
710 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
713 /* Skip next section on POWER7 or PPC970 */
715 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
716 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
719 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
722 /* Load up POWER8-specific registers */
724 lwz r6, VCPU_PSPB(r4)
730 ld r6, VCPU_DAWRX(r4)
731 ld r7, VCPU_CIABR(r4)
741 ld r5, VCPU_TFHAR(r4)
742 ld r6, VCPU_TFIAR(r4)
743 ld r7, VCPU_TEXASR(r4)
744 ld r8, VCPU_EBBHR(r4)
747 mtspr SPRN_TEXASR, r7
749 ld r5, VCPU_EBBRR(r4)
750 ld r6, VCPU_BESCR(r4)
751 ld r7, VCPU_CSIGR(r4)
757 ld r5, VCPU_TCSCR(r4)
759 lwz r7, VCPU_GUEST_PID(r4)
768 * Set the decrementer to the guest decrementer.
770 ld r8,VCPU_DEC_EXPIRES(r4)
776 ld r5, VCPU_SPRG0(r4)
777 ld r6, VCPU_SPRG1(r4)
778 ld r7, VCPU_SPRG2(r4)
779 ld r8, VCPU_SPRG3(r4)
785 /* Load up DAR and DSISR */
787 lwz r6, VCPU_DSISR(r4)
792 /* Restore AMR and UAMOR, set AMOR to all 1s */
799 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
801 /* Restore state of CTRL run bit; assume 1 on entry */
817 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
821 /* r11 = vcpu->arch.msr & ~MSR_HV */
822 rldicl r11, r11, 63 - MSR_HV_LG, 1
823 rotldi r11, r11, 1 + MSR_HV_LG
826 /* Check if we can deliver an external or decrementer interrupt now */
827 ld r0,VCPU_PENDING_EXC(r4)
828 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
838 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
840 li r0,BOOK3S_INTERRUPT_EXTERNAL
844 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
850 li r0,BOOK3S_INTERRUPT_DECREMENTER
853 /* Move SRR0 and SRR1 into the respective regs */
854 5: mtspr SPRN_SRR0, r6
860 * R10: value for HSRR0
861 * R11: value for HSRR1
866 stb r0,VCPU_CEDED(r4) /* cancel cede */
870 /* Activate guest mode, so faults get handled by KVM */
871 li r9, KVM_GUEST_MODE_GUEST_HV
872 stb r9, HSTATE_IN_GUEST(r13)
879 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
882 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
889 ld r1, VCPU_GPR(R1)(r4)
890 ld r2, VCPU_GPR(R2)(r4)
891 ld r3, VCPU_GPR(R3)(r4)
892 ld r5, VCPU_GPR(R5)(r4)
893 ld r6, VCPU_GPR(R6)(r4)
894 ld r7, VCPU_GPR(R7)(r4)
895 ld r8, VCPU_GPR(R8)(r4)
896 ld r9, VCPU_GPR(R9)(r4)
897 ld r10, VCPU_GPR(R10)(r4)
898 ld r11, VCPU_GPR(R11)(r4)
899 ld r12, VCPU_GPR(R12)(r4)
900 ld r13, VCPU_GPR(R13)(r4)
904 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
905 ld r0, VCPU_GPR(R0)(r4)
906 ld r4, VCPU_GPR(R4)(r4)
911 /******************************************************************************
915 *****************************************************************************/
918 * We come here from the first-level interrupt handlers.
920 .globl kvmppc_interrupt_hv
924 * R12 = interrupt vector
926 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
927 * guest R13 saved in SPRN_SCRATCH0
929 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
930 std r9, HSTATE_HOST_R2(r13)
932 lbz r9, HSTATE_IN_GUEST(r13)
933 cmpwi r9, KVM_GUEST_MODE_HOST_HV
934 beq kvmppc_bad_host_intr
935 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
936 cmpwi r9, KVM_GUEST_MODE_GUEST
937 ld r9, HSTATE_HOST_R2(r13)
938 beq kvmppc_interrupt_pr
940 /* We're now back in the host but in guest MMU context */
941 li r9, KVM_GUEST_MODE_HOST_HV
942 stb r9, HSTATE_IN_GUEST(r13)
944 ld r9, HSTATE_KVM_VCPU(r13)
948 std r0, VCPU_GPR(R0)(r9)
949 std r1, VCPU_GPR(R1)(r9)
950 std r2, VCPU_GPR(R2)(r9)
951 std r3, VCPU_GPR(R3)(r9)
952 std r4, VCPU_GPR(R4)(r9)
953 std r5, VCPU_GPR(R5)(r9)
954 std r6, VCPU_GPR(R6)(r9)
955 std r7, VCPU_GPR(R7)(r9)
956 std r8, VCPU_GPR(R8)(r9)
957 ld r0, HSTATE_HOST_R2(r13)
958 std r0, VCPU_GPR(R9)(r9)
959 std r10, VCPU_GPR(R10)(r9)
960 std r11, VCPU_GPR(R11)(r9)
961 ld r3, HSTATE_SCRATCH0(r13)
962 lwz r4, HSTATE_SCRATCH1(r13)
963 std r3, VCPU_GPR(R12)(r9)
966 ld r3, HSTATE_CFAR(r13)
967 std r3, VCPU_CFAR(r9)
968 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
970 ld r4, HSTATE_PPR(r13)
972 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
974 /* Restore R1/R2 so we can handle faults */
975 ld r1, HSTATE_HOST_R1(r13)
980 std r10, VCPU_SRR0(r9)
981 std r11, VCPU_SRR1(r9)
982 andi. r0, r12, 2 /* need to read HSRR0/1? */
984 mfspr r10, SPRN_HSRR0
985 mfspr r11, SPRN_HSRR1
987 1: std r10, VCPU_PC(r9)
988 std r11, VCPU_MSR(r9)
992 std r3, VCPU_GPR(R13)(r9)
995 stw r12,VCPU_TRAP(r9)
997 /* Save HEIR (HV emulation assist reg) in last_inst
998 if this is an HEI (HV emulation interrupt, e40) */
999 li r3,KVM_INST_FETCH_FAILED
1001 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1004 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1005 11: stw r3,VCPU_LAST_INST(r9)
1007 /* these are volatile across C function calls */
1010 std r3, VCPU_CTR(r9)
1011 stw r4, VCPU_XER(r9)
1014 /* If this is a page table miss then see if it's theirs or ours */
1015 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1017 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1019 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1021 /* See if this is a leftover HDEC interrupt */
1022 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1028 /* See if this is an hcall we can handle in real mode */
1029 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1030 beq hcall_try_real_mode
1032 /* Only handle external interrupts here on arch 206 and later */
1034 b ext_interrupt_to_host
1035 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1037 /* External interrupt ? */
1038 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1039 bne+ ext_interrupt_to_host
1041 /* External interrupt, first check for host_ipi. If this is
1042 * set, we know the host wants us out so let's do it now
1047 bgt ext_interrupt_to_host
1049 /* Allright, looks like an IPI for the guest, we need to set MER */
1050 /* Check if any CPU is heading out to the host, if so head out too */
1051 ld r5, HSTATE_KVM_VCORE(r13)
1052 lwz r0, VCORE_ENTRY_EXIT(r5)
1054 bge ext_interrupt_to_host
1056 /* See if there is a pending interrupt for the guest */
1058 ld r0, VCPU_PENDING_EXC(r9)
1059 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1060 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1061 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1064 /* And if the guest EE is set, we can deliver immediately, else
1065 * we return to the guest with MER set
1067 andi. r0, r11, MSR_EE
1069 mtspr SPRN_SRR0, r10
1070 mtspr SPRN_SRR1, r11
1071 li r10, BOOK3S_INTERRUPT_EXTERNAL
1072 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1078 ext_interrupt_to_host:
1080 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1081 /* Save more register state */
1084 std r6, VCPU_DAR(r9)
1085 stw r7, VCPU_DSISR(r9)
1087 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1088 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1090 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1091 std r6, VCPU_FAULT_DAR(r9)
1092 stw r7, VCPU_FAULT_DSISR(r9)
1094 /* See if it is a machine check */
1095 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1096 beq machine_check_realmode
1099 /* Save guest CTRL register, set runlatch to 1 */
1100 6: mfspr r6,SPRN_CTRLF
1101 stw r6,VCPU_CTRL(r9)
1107 /* Read the guest SLB and save it away */
1108 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1114 andis. r0,r8,SLB_ESID_V@h
1116 add r8,r8,r6 /* put index in */
1118 std r8,VCPU_SLB_E(r7)
1119 std r3,VCPU_SLB_V(r7)
1120 addi r7,r7,VCPU_SLB_SIZE
1124 stw r5,VCPU_SLB_MAX(r9)
1127 * Save the guest PURR/SPURR
1133 ld r8,VCPU_SPURR(r9)
1134 std r5,VCPU_PURR(r9)
1135 std r6,VCPU_SPURR(r9)
1140 * Restore host PURR/SPURR and add guest times
1141 * so that the time in the guest gets accounted.
1143 ld r3,HSTATE_PURR(r13)
1144 ld r4,HSTATE_SPURR(r13)
1149 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1156 std r5,VCPU_DEC_EXPIRES(r9)
1160 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1161 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
1164 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1167 /* Save POWER8-specific registers */
1171 std r5, VCPU_IAMR(r9)
1172 stw r6, VCPU_PSPB(r9)
1173 std r7, VCPU_FSCR(r9)
1178 std r6, VCPU_VTB(r9)
1179 std r7, VCPU_TAR(r9)
1180 mfspr r5, SPRN_TFHAR
1181 mfspr r6, SPRN_TFIAR
1182 mfspr r7, SPRN_TEXASR
1183 mfspr r8, SPRN_EBBHR
1184 std r5, VCPU_TFHAR(r9)
1185 std r6, VCPU_TFIAR(r9)
1186 std r7, VCPU_TEXASR(r9)
1187 std r8, VCPU_EBBHR(r9)
1188 mfspr r5, SPRN_EBBRR
1189 mfspr r6, SPRN_BESCR
1190 mfspr r7, SPRN_CSIGR
1192 std r5, VCPU_EBBRR(r9)
1193 std r6, VCPU_BESCR(r9)
1194 std r7, VCPU_CSIGR(r9)
1195 std r8, VCPU_TACR(r9)
1196 mfspr r5, SPRN_TCSCR
1200 std r5, VCPU_TCSCR(r9)
1201 std r6, VCPU_ACOP(r9)
1202 stw r7, VCPU_GUEST_PID(r9)
1203 std r8, VCPU_WORT(r9)
1206 /* Save and reset AMR and UAMOR before turning on the MMU */
1211 std r6,VCPU_UAMOR(r9)
1214 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1216 /* Switch DSCR back to host value */
1219 ld r7, HSTATE_DSCR(r13)
1220 std r8, VCPU_DSCR(r9)
1222 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1224 /* Save non-volatile GPRs */
1225 std r14, VCPU_GPR(R14)(r9)
1226 std r15, VCPU_GPR(R15)(r9)
1227 std r16, VCPU_GPR(R16)(r9)
1228 std r17, VCPU_GPR(R17)(r9)
1229 std r18, VCPU_GPR(R18)(r9)
1230 std r19, VCPU_GPR(R19)(r9)
1231 std r20, VCPU_GPR(R20)(r9)
1232 std r21, VCPU_GPR(R21)(r9)
1233 std r22, VCPU_GPR(R22)(r9)
1234 std r23, VCPU_GPR(R23)(r9)
1235 std r24, VCPU_GPR(R24)(r9)
1236 std r25, VCPU_GPR(R25)(r9)
1237 std r26, VCPU_GPR(R26)(r9)
1238 std r27, VCPU_GPR(R27)(r9)
1239 std r28, VCPU_GPR(R28)(r9)
1240 std r29, VCPU_GPR(R29)(r9)
1241 std r30, VCPU_GPR(R30)(r9)
1242 std r31, VCPU_GPR(R31)(r9)
1245 mfspr r3, SPRN_SPRG0
1246 mfspr r4, SPRN_SPRG1
1247 mfspr r5, SPRN_SPRG2
1248 mfspr r6, SPRN_SPRG3
1249 std r3, VCPU_SPRG0(r9)
1250 std r4, VCPU_SPRG1(r9)
1251 std r5, VCPU_SPRG2(r9)
1252 std r6, VCPU_SPRG3(r9)
1258 /* Increment yield count if they have a VPA */
1259 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1262 lwz r3, LPPACA_YIELDCOUNT(r8)
1264 stw r3, LPPACA_YIELDCOUNT(r8)
1266 stb r3, VCPU_VPA_DIRTY(r9)
1268 /* Save PMU registers if requested */
1269 /* r8 and cr0.eq are live here */
1271 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1272 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1273 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1274 mfspr r6, SPRN_MMCRA
1276 /* On P7, clear MMCRA in order to disable SDAR updates */
1278 mtspr SPRN_MMCRA, r7
1279 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1281 beq 21f /* if no VPA, save PMU stuff anyway */
1282 lbz r7, LPPACA_PMCINUSE(r8)
1283 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1285 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1287 21: mfspr r5, SPRN_MMCR1
1290 std r4, VCPU_MMCR(r9)
1291 std r5, VCPU_MMCR + 8(r9)
1292 std r6, VCPU_MMCR + 16(r9)
1293 std r7, VCPU_SIAR(r9)
1294 std r8, VCPU_SDAR(r9)
1302 mfspr r10, SPRN_PMC7
1303 mfspr r11, SPRN_PMC8
1304 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1305 stw r3, VCPU_PMC(r9)
1306 stw r4, VCPU_PMC + 4(r9)
1307 stw r5, VCPU_PMC + 8(r9)
1308 stw r6, VCPU_PMC + 12(r9)
1309 stw r7, VCPU_PMC + 16(r9)
1310 stw r8, VCPU_PMC + 20(r9)
1312 stw r10, VCPU_PMC + 24(r9)
1313 stw r11, VCPU_PMC + 28(r9)
1314 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1316 mfspr r4, SPRN_MMCR2
1318 mfspr r6, SPRN_SPMC1
1319 mfspr r7, SPRN_SPMC2
1320 mfspr r8, SPRN_MMCRS
1321 std r4, VCPU_MMCR + 24(r9)
1322 std r5, VCPU_SIER(r9)
1323 stw r6, VCPU_PMC + 24(r9)
1324 stw r7, VCPU_PMC + 28(r9)
1325 std r8, VCPU_MMCR + 32(r9)
1327 mtspr SPRN_MMCRS, r4
1328 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1336 hdec_soon: /* r12 = trap, r13 = paca */
1339 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1341 * POWER7 guest -> host partition switch code.
1342 * We don't have to lock against tlbies but we do
1343 * have to coordinate the hardware threads.
1345 /* Increment the threads-exiting-guest count in the 0xff00
1346 bits of vcore->entry_exit_count */
1348 ld r5,HSTATE_KVM_VCORE(r13)
1349 addi r6,r5,VCORE_ENTRY_EXIT
1357 * At this point we have an interrupt that we have to pass
1358 * up to the kernel or qemu; we can't handle it in real mode.
1359 * Thus we have to do a partition switch, so we have to
1360 * collect the other threads, if we are the first thread
1361 * to take an interrupt. To do this, we set the HDEC to 0,
1362 * which causes an HDEC interrupt in all threads within 2ns
1363 * because the HDEC register is shared between all 4 threads.
1364 * However, we don't need to bother if this is an HDEC
1365 * interrupt, since the other threads will already be on their
1366 * way here in that case.
1368 cmpwi r3,0x100 /* Are we the first here? */
1370 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1376 * Send an IPI to any napping threads, since an HDEC interrupt
1377 * doesn't wake CPUs up from nap.
1379 lwz r3,VCORE_NAPPING_THREADS(r5)
1380 lbz r4,HSTATE_PTID(r13)
1383 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1385 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1389 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1392 stbcix r0,r7,r8 /* trigger the IPI */
1394 addi r6,r6,PACA_SIZE
1398 /* Secondary threads wait for primary to do partition switch */
1399 43: ld r5,HSTATE_KVM_VCORE(r13)
1400 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1401 lbz r3,HSTATE_PTID(r13)
1405 13: lbz r3,VCORE_IN_GUEST(r5)
1411 /* Primary thread waits for all the secondaries to exit guest */
1412 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1419 /* Primary thread switches back to host partition */
1420 ld r6,KVM_HOST_SDR1(r4)
1421 lwz r7,KVM_HOST_LPID(r4)
1422 li r8,LPID_RSVD /* switch to reserved LPID */
1425 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1430 /* DPDES is shared between threads */
1431 mfspr r7, SPRN_DPDES
1432 std r7, VCORE_DPDES(r5)
1433 /* clear DPDES so we don't get guest doorbells in the host */
1435 mtspr SPRN_DPDES, r8
1436 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1438 /* Subtract timebase offset from timebase */
1439 ld r8,VCORE_TB_OFFSET(r5)
1442 mftb r6 /* current host timebase */
1444 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1445 mftb r7 /* check if lower 24 bits overflowed */
1450 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1454 17: ld r0, VCORE_PCR(r5)
1460 /* Signal secondary CPUs to continue */
1461 stb r0,VCORE_IN_GUEST(r5)
1462 lis r8,0x7fff /* MAX_INT@h */
1465 16: ld r8,KVM_HOST_LPCR(r4)
1471 * PPC970 guest -> host partition switch code.
1472 * We have to lock against concurrent tlbies, and
1473 * we have to flush the whole TLB.
1475 32: ld r5,HSTATE_KVM_VCORE(r13)
1476 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1478 /* Take the guest's tlbie_lock */
1479 #ifdef __BIG_ENDIAN__
1480 lwz r8,PACA_LOCK_TOKEN(r13)
1482 lwz r8,PACAPACAINDEX(r13)
1484 addi r3,r4,KVM_TLBIE_LOCK
1492 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1494 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1498 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1501 stw r0,0(r3) /* drop guest tlbie_lock */
1503 /* invalidate the whole TLB */
1512 /* take native_tlbie_lock */
1513 ld r3,toc_tlbie_lock@toc(2)
1521 ld r6,KVM_HOST_SDR1(r4)
1522 mtspr SPRN_SDR1,r6 /* switch to host page table */
1524 /* Set up host HID4 value */
1529 stw r0,0(r3) /* drop native_tlbie_lock */
1531 lis r8,0x7fff /* MAX_INT@h */
1534 /* Disable HDEC interrupts */
1537 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1547 /* load host SLB entries */
1548 33: ld r8,PACA_SLBSHADOWPTR(r13)
1550 .rept SLB_NUM_BOLTED
1551 ld r5,SLBSHADOW_SAVEAREA(r8)
1552 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1553 andis. r7,r5,SLB_ESID_V@h
1559 /* Unset guest mode */
1560 li r0, KVM_GUEST_MODE_NONE
1561 stb r0, HSTATE_IN_GUEST(r13)
1563 ld r0, 112+PPC_LR_STKOFF(r1)
1569 * Check whether an HDSI is an HPTE not found fault or something else.
1570 * If it is an HPTE not found fault that is due to the guest accessing
1571 * a page that they have mapped but which we have paged out, then
1572 * we continue on with the guest exit path. In all other cases,
1573 * reflect the HDSI to the guest as a DSI.
1577 mfspr r6, SPRN_HDSISR
1578 /* HPTE not found fault or protection fault? */
1579 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1580 beq 1f /* if not, send it to the guest */
1581 andi. r0, r11, MSR_DR /* data relocation enabled? */
1584 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1585 bne 1f /* if no SLB entry found */
1586 4: std r4, VCPU_FAULT_DAR(r9)
1587 stw r6, VCPU_FAULT_DSISR(r9)
1589 /* Search the hash table. */
1590 mr r3, r9 /* vcpu pointer */
1591 li r7, 1 /* data fault */
1592 bl .kvmppc_hpte_hv_fault
1593 ld r9, HSTATE_KVM_VCPU(r13)
1595 ld r11, VCPU_MSR(r9)
1596 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1597 cmpdi r3, 0 /* retry the instruction */
1599 cmpdi r3, -1 /* handle in kernel mode */
1601 cmpdi r3, -2 /* MMIO emulation; need instr word */
1604 /* Synthesize a DSI for the guest */
1605 ld r4, VCPU_FAULT_DAR(r9)
1607 1: mtspr SPRN_DAR, r4
1608 mtspr SPRN_DSISR, r6
1609 mtspr SPRN_SRR0, r10
1610 mtspr SPRN_SRR1, r11
1611 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1612 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1614 fast_interrupt_c_return:
1615 6: ld r7, VCPU_CTR(r9)
1616 lwz r8, VCPU_XER(r9)
1622 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1623 ld r5, KVM_VRMA_SLB_V(r5)
1626 /* If this is for emulated MMIO, load the instruction word */
1627 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1629 /* Set guest mode to 'jump over instruction' so if lwz faults
1630 * we'll just continue at the next IP. */
1631 li r0, KVM_GUEST_MODE_SKIP
1632 stb r0, HSTATE_IN_GUEST(r13)
1634 /* Do the access with MSR:DR enabled */
1636 ori r4, r3, MSR_DR /* Enable paging for data */
1641 /* Store the result */
1642 stw r8, VCPU_LAST_INST(r9)
1644 /* Unset guest mode. */
1645 li r0, KVM_GUEST_MODE_HOST_HV
1646 stb r0, HSTATE_IN_GUEST(r13)
1650 * Similarly for an HISI, reflect it to the guest as an ISI unless
1651 * it is an HPTE not found fault for a page that we have paged out.
1654 andis. r0, r11, SRR1_ISI_NOPT@h
1656 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1659 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1660 bne 1f /* if no SLB entry found */
1662 /* Search the hash table. */
1663 mr r3, r9 /* vcpu pointer */
1666 li r7, 0 /* instruction fault */
1667 bl .kvmppc_hpte_hv_fault
1668 ld r9, HSTATE_KVM_VCPU(r13)
1670 ld r11, VCPU_MSR(r9)
1671 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1672 cmpdi r3, 0 /* retry the instruction */
1673 beq fast_interrupt_c_return
1674 cmpdi r3, -1 /* handle in kernel mode */
1677 /* Synthesize an ISI for the guest */
1679 1: mtspr SPRN_SRR0, r10
1680 mtspr SPRN_SRR1, r11
1681 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1682 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1684 b fast_interrupt_c_return
1686 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1687 ld r5, KVM_VRMA_SLB_V(r6)
1691 * Try to handle an hcall in real mode.
1692 * Returns to the guest if we handle it, or continues on up to
1693 * the kernel if we can't (i.e. if we don't have a handler for
1694 * it, or if the handler returns H_TOO_HARD).
1696 .globl hcall_try_real_mode
1697 hcall_try_real_mode:
1698 ld r3,VCPU_GPR(R3)(r9)
1700 /* sc 1 from userspace - reflect to guest syscall */
1701 bne sc_1_fast_return
1703 cmpldi r3,hcall_real_table_end - hcall_real_table
1705 LOAD_REG_ADDR(r4, hcall_real_table)
1711 mr r3,r9 /* get vcpu pointer */
1712 ld r4,VCPU_GPR(R4)(r9)
1715 beq hcall_real_fallback
1716 ld r4,HSTATE_KVM_VCPU(r13)
1717 std r3,VCPU_GPR(R3)(r4)
1725 li r10, BOOK3S_INTERRUPT_SYSCALL
1726 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1731 /* We've attempted a real mode hcall, but it's punted it back
1732 * to userspace. We need to restore some clobbered volatiles
1733 * before resuming the pass-it-to-qemu path */
1734 hcall_real_fallback:
1735 li r12,BOOK3S_INTERRUPT_SYSCALL
1736 ld r9, HSTATE_KVM_VCPU(r13)
1740 .globl hcall_real_table
1742 .long 0 /* 0 - unused */
1743 .long .kvmppc_h_remove - hcall_real_table
1744 .long .kvmppc_h_enter - hcall_real_table
1745 .long .kvmppc_h_read - hcall_real_table
1746 .long 0 /* 0x10 - H_CLEAR_MOD */
1747 .long 0 /* 0x14 - H_CLEAR_REF */
1748 .long .kvmppc_h_protect - hcall_real_table
1749 .long 0 /* 0x1c - H_GET_TCE */
1750 .long .kvmppc_h_put_tce - hcall_real_table
1751 .long 0 /* 0x24 - H_SET_SPRG0 */
1752 .long .kvmppc_h_set_dabr - hcall_real_table
1767 #ifdef CONFIG_KVM_XICS
1768 .long .kvmppc_rm_h_eoi - hcall_real_table
1769 .long .kvmppc_rm_h_cppr - hcall_real_table
1770 .long .kvmppc_rm_h_ipi - hcall_real_table
1771 .long 0 /* 0x70 - H_IPOLL */
1772 .long .kvmppc_rm_h_xirr - hcall_real_table
1774 .long 0 /* 0x64 - H_EOI */
1775 .long 0 /* 0x68 - H_CPPR */
1776 .long 0 /* 0x6c - H_IPI */
1777 .long 0 /* 0x70 - H_IPOLL */
1778 .long 0 /* 0x74 - H_XIRR */
1806 .long .kvmppc_h_cede - hcall_real_table
1823 .long .kvmppc_h_bulk_remove - hcall_real_table
1824 hcall_real_table_end:
1830 _GLOBAL(kvmppc_h_set_dabr)
1833 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1834 std r4,VCPU_DABR(r3)
1835 /* Work around P7 bug where DABR can get corrupted on mtspr */
1836 1: mtspr SPRN_DABR,r4
1844 _GLOBAL(kvmppc_h_cede)
1846 std r11,VCPU_MSR(r3)
1848 stb r0,VCPU_CEDED(r3)
1849 sync /* order setting ceded vs. testing prodded */
1850 lbz r5,VCPU_PRODDED(r3)
1852 bne kvm_cede_prodded
1853 li r0,0 /* set trap to 0 to say hcall is handled */
1854 stw r0,VCPU_TRAP(r3)
1856 std r0,VCPU_GPR(R3)(r3)
1858 b kvm_cede_exit /* just send it up to host on 970 */
1859 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1862 * Set our bit in the bitmask of napping threads unless all the
1863 * other threads are already napping, in which case we send this
1866 ld r5,HSTATE_KVM_VCORE(r13)
1867 lbz r6,HSTATE_PTID(r13)
1868 lwz r8,VCORE_ENTRY_EXIT(r5)
1872 addi r6,r5,VCORE_NAPPING_THREADS
1881 stb r0,HSTATE_NAPPING(r13)
1882 /* order napping_threads update vs testing entry_exit_count */
1885 lwz r7,VCORE_ENTRY_EXIT(r5)
1887 bge 33f /* another thread already exiting */
1890 * Although not specifically required by the architecture, POWER7
1891 * preserves the following registers in nap mode, even if an SMT mode
1892 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1893 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1895 /* Save non-volatile GPRs */
1896 std r14, VCPU_GPR(R14)(r3)
1897 std r15, VCPU_GPR(R15)(r3)
1898 std r16, VCPU_GPR(R16)(r3)
1899 std r17, VCPU_GPR(R17)(r3)
1900 std r18, VCPU_GPR(R18)(r3)
1901 std r19, VCPU_GPR(R19)(r3)
1902 std r20, VCPU_GPR(R20)(r3)
1903 std r21, VCPU_GPR(R21)(r3)
1904 std r22, VCPU_GPR(R22)(r3)
1905 std r23, VCPU_GPR(R23)(r3)
1906 std r24, VCPU_GPR(R24)(r3)
1907 std r25, VCPU_GPR(R25)(r3)
1908 std r26, VCPU_GPR(R26)(r3)
1909 std r27, VCPU_GPR(R27)(r3)
1910 std r28, VCPU_GPR(R28)(r3)
1911 std r29, VCPU_GPR(R29)(r3)
1912 std r30, VCPU_GPR(R30)(r3)
1913 std r31, VCPU_GPR(R31)(r3)
1919 * Take a nap until a decrementer or external interrupt occurs,
1920 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1923 stb r0,HSTATE_HWTHREAD_REQ(r13)
1925 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1929 std r0, HSTATE_SCRATCH0(r13)
1931 ld r0, HSTATE_SCRATCH0(r13)
1938 /* get vcpu pointer */
1939 ld r4, HSTATE_KVM_VCPU(r13)
1941 /* Woken by external or decrementer interrupt */
1942 ld r1, HSTATE_HOST_R1(r13)
1944 /* load up FP state */
1948 ld r14, VCPU_GPR(R14)(r4)
1949 ld r15, VCPU_GPR(R15)(r4)
1950 ld r16, VCPU_GPR(R16)(r4)
1951 ld r17, VCPU_GPR(R17)(r4)
1952 ld r18, VCPU_GPR(R18)(r4)
1953 ld r19, VCPU_GPR(R19)(r4)
1954 ld r20, VCPU_GPR(R20)(r4)
1955 ld r21, VCPU_GPR(R21)(r4)
1956 ld r22, VCPU_GPR(R22)(r4)
1957 ld r23, VCPU_GPR(R23)(r4)
1958 ld r24, VCPU_GPR(R24)(r4)
1959 ld r25, VCPU_GPR(R25)(r4)
1960 ld r26, VCPU_GPR(R26)(r4)
1961 ld r27, VCPU_GPR(R27)(r4)
1962 ld r28, VCPU_GPR(R28)(r4)
1963 ld r29, VCPU_GPR(R29)(r4)
1964 ld r30, VCPU_GPR(R30)(r4)
1965 ld r31, VCPU_GPR(R31)(r4)
1967 /* clear our bit in vcore->napping_threads */
1968 33: ld r5,HSTATE_KVM_VCORE(r13)
1969 lbz r3,HSTATE_PTID(r13)
1972 addi r6,r5,VCORE_NAPPING_THREADS
1978 stb r0,HSTATE_NAPPING(r13)
1980 /* Check the wake reason in SRR1 to see why we got here */
1982 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1983 cmpwi r3, 4 /* was it an external interrupt? */
1984 li r12, BOOK3S_INTERRUPT_EXTERNAL
1987 ld r11, VCPU_MSR(r9)
1988 beq do_ext_interrupt /* if so */
1990 /* see if any other thread is already exiting */
1991 lwz r0,VCORE_ENTRY_EXIT(r5)
1993 blt kvmppc_cede_reentry /* if not go back to guest */
1995 /* some threads are exiting, so go to the guest exit path */
1996 b hcall_real_fallback
1998 /* cede when already previously prodded case */
2001 stb r0,VCPU_PRODDED(r3)
2002 sync /* order testing prodded vs. clearing ceded */
2003 stb r0,VCPU_CEDED(r3)
2007 /* we've ceded but we want to give control to the host */
2009 b hcall_real_fallback
2011 /* Try to handle a machine check in real mode */
2012 machine_check_realmode:
2013 mr r3, r9 /* get vcpu pointer */
2014 bl .kvmppc_realmode_machine_check
2016 cmpdi r3, 0 /* continue exiting from guest? */
2017 ld r9, HSTATE_KVM_VCPU(r13)
2018 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2020 /* If not, deliver a machine check. SRR0/1 are already set */
2021 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2022 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
2024 b fast_interrupt_c_return
2027 * Determine what sort of external interrupt is pending (if any).
2029 * 0 if no interrupt is pending
2030 * 1 if an interrupt is pending that needs to be handled by the host
2031 * -1 if there was a guest wakeup IPI (which has now been cleared)
2034 /* see if a host IPI is pending */
2036 lbz r0, HSTATE_HOST_IPI(r13)
2040 /* Now read the interrupt from the ICP */
2041 ld r6, HSTATE_XICS_PHYS(r13)
2046 rlwinm. r3, r0, 0, 0xffffff
2048 beq 1f /* if nothing pending in the ICP */
2050 /* We found something in the ICP...
2052 * If it's not an IPI, stash it in the PACA and return to
2053 * the host, we don't (yet) handle directing real external
2054 * interrupts directly to the guest
2056 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2060 /* It's an IPI, clear the MFRR and EOI it */
2063 stbcix r3, r6, r8 /* clear the IPI */
2064 stwcix r0, r6, r7 /* EOI it */
2067 /* We need to re-check host IPI now in case it got set in the
2068 * meantime. If it's clear, we bounce the interrupt to the
2071 lbz r0, HSTATE_HOST_IPI(r13)
2075 /* OK, it's an IPI for us */
2079 42: /* It's not an IPI and it's for the host, stash it in the PACA
2080 * before exit, it will be picked up by the host ICP driver
2082 stw r0, HSTATE_SAVED_XIRR(r13)
2085 43: /* We raced with the host, we need to resend that IPI, bummer */
2087 stbcix r0, r6, r8 /* set the IPI */
2092 * Save away FP, VMX and VSX registers.
2094 * N.B. r30 and r31 are volatile across this function,
2095 * thus it is not callable from C.
2102 #ifdef CONFIG_ALTIVEC
2104 oris r8,r8,MSR_VEC@h
2105 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2109 oris r8,r8,MSR_VSX@h
2110 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2114 addi r3,r3,VCPU_FPRS
2116 #ifdef CONFIG_ALTIVEC
2118 addi r3,r31,VCPU_VRS
2120 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2122 mfspr r6,SPRN_VRSAVE
2123 stw r6,VCPU_VRSAVE(r3)
2130 * Load up FP, VMX and VSX registers
2132 * N.B. r30 and r31 are volatile across this function,
2133 * thus it is not callable from C.
2140 #ifdef CONFIG_ALTIVEC
2142 oris r8,r8,MSR_VEC@h
2143 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2147 oris r8,r8,MSR_VSX@h
2148 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2152 addi r3,r4,VCPU_FPRS
2154 #ifdef CONFIG_ALTIVEC
2156 addi r3,r31,VCPU_VRS
2158 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2160 lwz r7,VCPU_VRSAVE(r4)
2161 mtspr SPRN_VRSAVE,r7
2167 * We come here if we get any exception or interrupt while we are
2168 * executing host real mode code while in guest MMU context.
2169 * For now just spin, but we should do something better.
2171 kvmppc_bad_host_intr: