1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
39 #include <asm/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/pgtable.h>
43 #include <asm/mmu_context.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
67 #include <mm/mmu_decl.h>
70 #define DBG(fmt...) udbg_printf(fmt)
76 #define DBG_LOW(fmt...) udbg_printf(fmt)
78 #define DBG_LOW(fmt...)
86 * Note: pte --> Linux PTE
87 * HPTE --> PowerPC Hashed Page Table Entry
90 * htab_initialize is called with the MMU off (of course), but
91 * the kernel has been copied down to zero so it can directly
92 * reference global data. At this point it is very difficult
93 * to print debug info.
97 static unsigned long _SDR1;
98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
99 EXPORT_SYMBOL_GPL(mmu_psize_defs);
101 u8 hpte_page_sizes[1 << LP_BITS];
102 EXPORT_SYMBOL_GPL(hpte_page_sizes);
104 struct hash_pte *htab_address;
105 unsigned long htab_size_bytes;
106 unsigned long htab_hash_mask;
107 EXPORT_SYMBOL_GPL(htab_hash_mask);
108 int mmu_linear_psize = MMU_PAGE_4K;
109 EXPORT_SYMBOL_GPL(mmu_linear_psize);
110 int mmu_virtual_psize = MMU_PAGE_4K;
111 int mmu_vmalloc_psize = MMU_PAGE_4K;
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
113 int mmu_vmemmap_psize = MMU_PAGE_4K;
115 int mmu_io_psize = MMU_PAGE_4K;
116 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
117 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
118 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
119 u16 mmu_slb_size = 64;
120 EXPORT_SYMBOL_GPL(mmu_slb_size);
121 #ifdef CONFIG_PPC_64K_PAGES
122 int mmu_ci_restrictions;
124 #ifdef CONFIG_DEBUG_PAGEALLOC
125 static u8 *linear_map_hash_slots;
126 static unsigned long linear_map_hash_count;
127 static DEFINE_SPINLOCK(linear_map_hash_lock);
128 #endif /* CONFIG_DEBUG_PAGEALLOC */
129 struct mmu_hash_ops mmu_hash_ops;
130 EXPORT_SYMBOL(mmu_hash_ops);
133 * These are definitions of page sizes arrays to be used when none
134 * is provided by the firmware.
138 * Fallback (4k pages only)
140 static struct mmu_psize_def mmu_psize_defaults[] = {
144 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
151 * POWER4, GPUL, POWER5
153 * Support for 16Mb large pages
155 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
159 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
166 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
167 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
174 * 'R' and 'C' update notes:
175 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
176 * create writeable HPTEs without C set, because the hcall H_PROTECT
177 * that we use in that case will not update C
178 * - The above is however not a problem, because we also don't do that
179 * fancy "no flush" variant of eviction and we use H_REMOVE which will
180 * do the right thing and thus we don't have the race I described earlier
182 * - Under bare metal, we do have the race, so we need R and C set
183 * - We make sure R is always set and never lost
184 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
186 unsigned long htab_convert_pte_flags(unsigned long pteflags)
188 unsigned long rflags = 0;
190 /* _PAGE_EXEC -> NOEXEC */
191 if ((pteflags & _PAGE_EXEC) == 0)
195 * Linux uses slb key 0 for kernel and 1 for user.
196 * kernel RW areas are mapped with PPP=0b000
197 * User area is mapped with PPP=0b010 for read/write
198 * or PPP=0b011 for read-only (including writeable but clean pages).
200 if (pteflags & _PAGE_PRIVILEGED) {
202 * Kernel read only mapped with ppp bits 0b110
204 if (!(pteflags & _PAGE_WRITE)) {
205 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
206 rflags |= (HPTE_R_PP0 | 0x2);
211 if (pteflags & _PAGE_RWX)
213 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
217 * We can't allow hardware to update hpte bits. Hence always
218 * set 'R' bit and set 'C' if it is a write fault
222 if (pteflags & _PAGE_DIRTY)
228 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
231 rflags |= (HPTE_R_I | HPTE_R_G);
232 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
233 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
236 * Add memory coherence if cache inhibited is not set
240 rflags |= pte_to_hpte_pkey_bits(pteflags);
244 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
245 unsigned long pstart, unsigned long prot,
246 int psize, int ssize)
248 unsigned long vaddr, paddr;
249 unsigned int step, shift;
252 shift = mmu_psize_defs[psize].shift;
255 prot = htab_convert_pte_flags(prot);
257 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
258 vstart, vend, pstart, prot, psize, ssize);
260 for (vaddr = vstart, paddr = pstart; vaddr < vend;
261 vaddr += step, paddr += step) {
262 unsigned long hash, hpteg;
263 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
264 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
265 unsigned long tprot = prot;
266 bool secondary_hash = false;
269 * If we hit a bad address return error.
273 /* Make kernel text executable */
274 if (overlaps_kernel_text(vaddr, vaddr + step))
278 * If relocatable, check if it overlaps interrupt vectors that
279 * are copied down to real 0. For relocatable kernel
280 * (e.g. kdump case) we copy interrupt vectors down to real
281 * address 0. Mark that region as executable. This is
282 * because on p8 system with relocation on exception feature
283 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
284 * in order to execute the interrupt handlers in virtual
285 * mode the vector region need to be marked as executable.
287 if ((PHYSICAL_START > MEMORY_START) &&
288 overlaps_interrupt_vector_text(vaddr, vaddr + step))
291 hash = hpt_hash(vpn, shift, ssize);
292 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
294 BUG_ON(!mmu_hash_ops.hpte_insert);
296 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
297 HPTE_V_BOLTED, psize, psize,
301 * Try to to keep bolted entries in primary.
302 * Remove non bolted entries and try insert again
304 ret = mmu_hash_ops.hpte_remove(hpteg);
306 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
307 HPTE_V_BOLTED, psize, psize,
309 if (ret == -1 && !secondary_hash) {
310 secondary_hash = true;
311 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
320 #ifdef CONFIG_DEBUG_PAGEALLOC
321 if (debug_pagealloc_enabled() &&
322 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
323 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
324 #endif /* CONFIG_DEBUG_PAGEALLOC */
326 return ret < 0 ? ret : 0;
329 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
330 int psize, int ssize)
333 unsigned int step, shift;
337 shift = mmu_psize_defs[psize].shift;
340 if (!mmu_hash_ops.hpte_removebolted)
343 for (vaddr = vstart; vaddr < vend; vaddr += step) {
344 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
356 static bool disable_1tb_segments = false;
358 static int __init parse_disable_1tb_segments(char *p)
360 disable_1tb_segments = true;
363 early_param("disable_1tb_segments", parse_disable_1tb_segments);
365 static int __init htab_dt_scan_seg_sizes(unsigned long node,
366 const char *uname, int depth,
369 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
373 /* We are scanning "cpu" nodes only */
374 if (type == NULL || strcmp(type, "cpu") != 0)
377 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
380 for (; size >= 4; size -= 4, ++prop) {
381 if (be32_to_cpu(prop[0]) == 40) {
382 DBG("1T segment support detected\n");
384 if (disable_1tb_segments) {
385 DBG("1T segments disabled by command line\n");
389 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
393 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
397 static int __init get_idx_from_shift(unsigned int shift)
421 static int __init htab_dt_scan_page_sizes(unsigned long node,
422 const char *uname, int depth,
425 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
429 /* We are scanning "cpu" nodes only */
430 if (type == NULL || strcmp(type, "cpu") != 0)
433 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
437 pr_info("Page sizes from device-tree:\n");
439 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
441 unsigned int base_shift = be32_to_cpu(prop[0]);
442 unsigned int slbenc = be32_to_cpu(prop[1]);
443 unsigned int lpnum = be32_to_cpu(prop[2]);
444 struct mmu_psize_def *def;
447 size -= 3; prop += 3;
448 base_idx = get_idx_from_shift(base_shift);
450 /* skip the pte encoding also */
451 prop += lpnum * 2; size -= lpnum * 2;
454 def = &mmu_psize_defs[base_idx];
455 if (base_idx == MMU_PAGE_16M)
456 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
458 def->shift = base_shift;
459 if (base_shift <= 23)
462 def->avpnm = (1 << (base_shift - 23)) - 1;
465 * We don't know for sure what's up with tlbiel, so
466 * for now we only set it for 4K and 64K pages
468 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
473 while (size > 0 && lpnum) {
474 unsigned int shift = be32_to_cpu(prop[0]);
475 int penc = be32_to_cpu(prop[1]);
477 prop += 2; size -= 2;
480 idx = get_idx_from_shift(shift);
485 pr_err("Invalid penc for base_shift=%d "
486 "shift=%d\n", base_shift, shift);
488 def->penc[idx] = penc;
489 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
490 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
491 base_shift, shift, def->sllp,
492 def->avpnm, def->tlbiel, def->penc[idx]);
499 #ifdef CONFIG_HUGETLB_PAGE
501 * Scan for 16G memory blocks that have been set aside for huge pages
502 * and reserve those blocks for 16G huge pages.
504 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
505 const char *uname, int depth,
507 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
508 const __be64 *addr_prop;
509 const __be32 *page_count_prop;
510 unsigned int expected_pages;
511 long unsigned int phys_addr;
512 long unsigned int block_size;
514 /* We are scanning "memory" nodes only */
515 if (type == NULL || strcmp(type, "memory") != 0)
519 * This property is the log base 2 of the number of virtual pages that
520 * will represent this memory block.
522 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
523 if (page_count_prop == NULL)
525 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
526 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
527 if (addr_prop == NULL)
529 phys_addr = be64_to_cpu(addr_prop[0]);
530 block_size = be64_to_cpu(addr_prop[1]);
531 if (block_size != (16 * GB))
533 printk(KERN_INFO "Huge page(16GB) memory: "
534 "addr = 0x%lX size = 0x%lX pages = %d\n",
535 phys_addr, block_size, expected_pages);
536 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
537 memblock_reserve(phys_addr, block_size * expected_pages);
538 pseries_add_gpage(phys_addr, block_size, expected_pages);
542 #endif /* CONFIG_HUGETLB_PAGE */
544 static void mmu_psize_set_default_penc(void)
547 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
548 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
549 mmu_psize_defs[bpsize].penc[apsize] = -1;
552 #ifdef CONFIG_PPC_64K_PAGES
554 static bool might_have_hea(void)
557 * The HEA ethernet adapter requires awareness of the
558 * GX bus. Without that awareness we can easily assume
559 * we will never see an HEA ethernet device.
561 #ifdef CONFIG_IBMEBUS
562 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
563 firmware_has_feature(FW_FEATURE_SPLPAR);
569 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
571 static void __init htab_scan_page_sizes(void)
575 /* se the invalid penc to -1 */
576 mmu_psize_set_default_penc();
578 /* Default to 4K pages only */
579 memcpy(mmu_psize_defs, mmu_psize_defaults,
580 sizeof(mmu_psize_defaults));
583 * Try to find the available page sizes in the device-tree
585 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
586 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
588 * Nothing in the device-tree, but the CPU supports 16M pages,
589 * so let's fallback on a known size list for 16M capable CPUs.
591 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
592 sizeof(mmu_psize_defaults_gp));
595 #ifdef CONFIG_HUGETLB_PAGE
596 if (!hugetlb_disabled) {
597 /* Reserve 16G huge page memory sections for huge pages */
598 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
600 #endif /* CONFIG_HUGETLB_PAGE */
604 * Fill in the hpte_page_sizes[] array.
605 * We go through the mmu_psize_defs[] array looking for all the
606 * supported base/actual page size combinations. Each combination
607 * has a unique pagesize encoding (penc) value in the low bits of
608 * the LP field of the HPTE. For actual page sizes less than 1MB,
609 * some of the upper LP bits are used for RPN bits, meaning that
610 * we need to fill in several entries in hpte_page_sizes[].
612 * In diagrammatic form, with r = RPN bits and z = page size bits:
613 * PTE LP actual page size
620 * The zzzz bits are implementation-specific but are chosen so that
621 * no encoding for a larger page size uses the same value in its
622 * low-order N bits as the encoding for the 2^(12+N) byte page size
625 static void init_hpte_page_sizes(void)
628 long int shift, penc;
630 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
631 if (!mmu_psize_defs[bp].shift)
632 continue; /* not a supported page size */
633 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
634 penc = mmu_psize_defs[bp].penc[ap];
635 if (penc == -1 || !mmu_psize_defs[ap].shift)
637 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
639 continue; /* should never happen */
641 * For page sizes less than 1MB, this loop
642 * replicates the entry for all possible values
645 while (penc < (1 << LP_BITS)) {
646 hpte_page_sizes[penc] = (ap << 4) | bp;
653 static void __init htab_init_page_sizes(void)
656 init_hpte_page_sizes();
658 if (!debug_pagealloc_enabled()) {
660 * Pick a size for the linear mapping. Currently, we only
661 * support 16M, 1M and 4K which is the default
663 if (IS_ENABLED(STRICT_KERNEL_RWX) &&
664 (unsigned long)_stext % 0x1000000) {
665 if (mmu_psize_defs[MMU_PAGE_16M].shift)
666 pr_warn("Kernel not 16M aligned, "
667 "disabling 16M linear map alignment");
671 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
672 mmu_linear_psize = MMU_PAGE_16M;
673 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
674 mmu_linear_psize = MMU_PAGE_1M;
677 #ifdef CONFIG_PPC_64K_PAGES
679 * Pick a size for the ordinary pages. Default is 4K, we support
680 * 64K for user mappings and vmalloc if supported by the processor.
681 * We only use 64k for ioremap if the processor
682 * (and firmware) support cache-inhibited large pages.
683 * If not, we use 4k and set mmu_ci_restrictions so that
684 * hash_page knows to switch processes that use cache-inhibited
685 * mappings to 4k pages.
687 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
688 mmu_virtual_psize = MMU_PAGE_64K;
689 mmu_vmalloc_psize = MMU_PAGE_64K;
690 if (mmu_linear_psize == MMU_PAGE_4K)
691 mmu_linear_psize = MMU_PAGE_64K;
692 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
694 * When running on pSeries using 64k pages for ioremap
695 * would stop us accessing the HEA ethernet. So if we
696 * have the chance of ever seeing one, stay at 4k.
698 if (!might_have_hea())
699 mmu_io_psize = MMU_PAGE_64K;
701 mmu_ci_restrictions = 1;
703 #endif /* CONFIG_PPC_64K_PAGES */
705 #ifdef CONFIG_SPARSEMEM_VMEMMAP
707 * We try to use 16M pages for vmemmap if that is supported
708 * and we have at least 1G of RAM at boot
710 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
711 memblock_phys_mem_size() >= 0x40000000)
712 mmu_vmemmap_psize = MMU_PAGE_16M;
714 mmu_vmemmap_psize = mmu_virtual_psize;
715 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
717 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
718 "virtual = %d, io = %d"
719 #ifdef CONFIG_SPARSEMEM_VMEMMAP
723 mmu_psize_defs[mmu_linear_psize].shift,
724 mmu_psize_defs[mmu_virtual_psize].shift,
725 mmu_psize_defs[mmu_io_psize].shift
726 #ifdef CONFIG_SPARSEMEM_VMEMMAP
727 ,mmu_psize_defs[mmu_vmemmap_psize].shift
732 static int __init htab_dt_scan_pftsize(unsigned long node,
733 const char *uname, int depth,
736 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
739 /* We are scanning "cpu" nodes only */
740 if (type == NULL || strcmp(type, "cpu") != 0)
743 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
745 /* pft_size[0] is the NUMA CEC cookie */
746 ppc64_pft_size = be32_to_cpu(prop[1]);
752 unsigned htab_shift_for_mem_size(unsigned long mem_size)
754 unsigned memshift = __ilog2(mem_size);
755 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
758 /* round mem_size up to next power of 2 */
759 if ((1UL << memshift) < mem_size)
762 /* aim for 2 pages / pteg */
763 pteg_shift = memshift - (pshift + 1);
766 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
767 * size permitted by the architecture.
769 return max(pteg_shift + 7, 18U);
772 static unsigned long __init htab_get_table_size(void)
775 * If hash size isn't already provided by the platform, we try to
776 * retrieve it from the device-tree. If it's not there neither, we
777 * calculate it now based on the total RAM size
779 if (ppc64_pft_size == 0)
780 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
782 return 1UL << ppc64_pft_size;
784 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
787 #ifdef CONFIG_MEMORY_HOTPLUG
788 int resize_hpt_for_hotplug(unsigned long new_mem_size)
790 unsigned target_hpt_shift;
792 if (!mmu_hash_ops.resize_hpt)
795 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
798 * To avoid lots of HPT resizes if memory size is fluctuating
799 * across a boundary, we deliberately have some hysterisis
800 * here: we immediately increase the HPT size if the target
801 * shift exceeds the current shift, but we won't attempt to
802 * reduce unless the target shift is at least 2 below the
805 if (target_hpt_shift > ppc64_pft_size ||
806 target_hpt_shift < ppc64_pft_size - 1)
807 return mmu_hash_ops.resize_hpt(target_hpt_shift);
812 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
816 if (end >= H_VMALLOC_START) {
817 pr_warn("Outside the supported range\n");
821 rc = htab_bolt_mapping(start, end, __pa(start),
822 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
826 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
828 BUG_ON(rc2 && (rc2 != -ENOENT));
833 int hash__remove_section_mapping(unsigned long start, unsigned long end)
835 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
840 #endif /* CONFIG_MEMORY_HOTPLUG */
842 static void __init hash_init_partition_table(phys_addr_t hash_table,
843 unsigned long htab_size)
845 mmu_partition_table_init();
848 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
849 * For now, UPRT is 0 and we have no segment table.
851 htab_size = __ilog2(htab_size) - 18;
852 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
853 pr_info("Partition table %p\n", partition_tb);
856 static void __init htab_initialize(void)
859 unsigned long pteg_count;
861 unsigned long base = 0, size = 0;
862 struct memblock_region *reg;
864 DBG(" -> htab_initialize()\n");
866 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
867 mmu_kernel_ssize = MMU_SEGSIZE_1T;
868 mmu_highuser_ssize = MMU_SEGSIZE_1T;
869 printk(KERN_INFO "Using 1TB segments\n");
873 * Calculate the required size of the htab. We want the number of
874 * PTEGs to equal one half the number of real pages.
876 htab_size_bytes = htab_get_table_size();
877 pteg_count = htab_size_bytes >> 7;
879 htab_hash_mask = pteg_count - 1;
881 if (firmware_has_feature(FW_FEATURE_LPAR) ||
882 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
883 /* Using a hypervisor which owns the htab */
886 #ifdef CONFIG_FA_DUMP
888 * If firmware assisted dump is active firmware preserves
889 * the contents of htab along with entire partition memory.
890 * Clear the htab if firmware assisted dump is active so
891 * that we dont end up using old mappings.
893 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
894 mmu_hash_ops.hpte_clear_all();
897 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
899 #ifdef CONFIG_PPC_CELL
901 * Cell may require the hash table down low when using the
902 * Axon IOMMU in order to fit the dynamic region over it, see
903 * comments in cell/iommu.c
905 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
907 pr_info("Hash table forced below 2G for Axon IOMMU\n");
909 #endif /* CONFIG_PPC_CELL */
911 table = memblock_phys_alloc_range(htab_size_bytes,
915 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
916 &htab_size_bytes, &limit);
918 DBG("Hash table allocated at %lx, size: %lx\n", table,
921 htab_address = __va(table);
923 /* htab absolute addr + encoded htabsize */
924 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
926 /* Initialize the HPT with no entries */
927 memset((void *)table, 0, htab_size_bytes);
929 if (!cpu_has_feature(CPU_FTR_ARCH_300))
931 mtspr(SPRN_SDR1, _SDR1);
933 hash_init_partition_table(table, htab_size_bytes);
936 prot = pgprot_val(PAGE_KERNEL);
938 #ifdef CONFIG_DEBUG_PAGEALLOC
939 if (debug_pagealloc_enabled()) {
940 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
941 linear_map_hash_slots = memblock_alloc_try_nid(
942 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
943 ppc64_rma_size, NUMA_NO_NODE);
944 if (!linear_map_hash_slots)
945 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
946 __func__, linear_map_hash_count, &ppc64_rma_size);
948 #endif /* CONFIG_DEBUG_PAGEALLOC */
950 /* create bolted the linear mapping in the hash table */
951 for_each_memblock(memory, reg) {
952 base = (unsigned long)__va(reg->base);
955 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
958 if ((base + size) >= H_VMALLOC_START) {
959 pr_warn("Outside the supported range\n");
963 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
964 prot, mmu_linear_psize, mmu_kernel_ssize));
966 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
969 * If we have a memory_limit and we've allocated TCEs then we need to
970 * explicitly map the TCE area at the top of RAM. We also cope with the
971 * case that the TCEs start below memory_limit.
972 * tce_alloc_start/end are 16MB aligned so the mapping should work
973 * for either 4K or 16MB pages.
975 if (tce_alloc_start) {
976 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
977 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
979 if (base + size >= tce_alloc_start)
980 tce_alloc_start = base + size + 1;
982 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
983 __pa(tce_alloc_start), prot,
984 mmu_linear_psize, mmu_kernel_ssize));
988 DBG(" <- htab_initialize()\n");
993 void __init hash__early_init_devtree(void)
995 /* Initialize segment sizes */
996 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
998 /* Initialize page sizes */
999 htab_scan_page_sizes();
1002 static struct hash_mm_context init_hash_mm_context;
1003 void __init hash__early_init_mmu(void)
1005 #ifndef CONFIG_PPC_64K_PAGES
1007 * We have code in __hash_page_4K() and elsewhere, which assumes it can
1009 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1011 * Where the slot number is between 0-15, and values of 8-15 indicate
1012 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1013 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1014 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1015 * with a BUILD_BUG_ON().
1017 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1018 #endif /* CONFIG_PPC_64K_PAGES */
1020 htab_init_page_sizes();
1023 * initialize page table size
1025 __pte_frag_nr = H_PTE_FRAG_NR;
1026 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1027 __pmd_frag_nr = H_PMD_FRAG_NR;
1028 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1030 __pte_index_size = H_PTE_INDEX_SIZE;
1031 __pmd_index_size = H_PMD_INDEX_SIZE;
1032 __pud_index_size = H_PUD_INDEX_SIZE;
1033 __pgd_index_size = H_PGD_INDEX_SIZE;
1034 __pud_cache_index = H_PUD_CACHE_INDEX;
1035 __pte_table_size = H_PTE_TABLE_SIZE;
1036 __pmd_table_size = H_PMD_TABLE_SIZE;
1037 __pud_table_size = H_PUD_TABLE_SIZE;
1038 __pgd_table_size = H_PGD_TABLE_SIZE;
1040 * 4k use hugepd format, so for hash set then to
1043 __pmd_val_bits = HASH_PMD_VAL_BITS;
1044 __pud_val_bits = HASH_PUD_VAL_BITS;
1045 __pgd_val_bits = HASH_PGD_VAL_BITS;
1047 __kernel_virt_start = H_KERN_VIRT_START;
1048 __vmalloc_start = H_VMALLOC_START;
1049 __vmalloc_end = H_VMALLOC_END;
1050 __kernel_io_start = H_KERN_IO_START;
1051 __kernel_io_end = H_KERN_IO_END;
1052 vmemmap = (struct page *)H_VMEMMAP_START;
1053 ioremap_bot = IOREMAP_BASE;
1056 pci_io_base = ISA_IO_BASE;
1059 /* Select appropriate backend */
1060 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1061 ps3_early_mm_init();
1062 else if (firmware_has_feature(FW_FEATURE_LPAR))
1063 hpte_init_pseries();
1064 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1067 if (!mmu_hash_ops.hpte_insert)
1068 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1071 * Initialize the MMU Hash table and create the linear mapping
1072 * of memory. Has to be done before SLB initialization as this is
1073 * currently where the page size encoding is obtained.
1077 init_mm.context.hash_context = &init_hash_mm_context;
1078 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1080 pr_info("Initializing hash mmu with SLB\n");
1081 /* Initialize SLB management */
1084 if (cpu_has_feature(CPU_FTR_ARCH_206)
1085 && cpu_has_feature(CPU_FTR_HVMODE))
1090 void hash__early_init_mmu_secondary(void)
1092 /* Initialize hash table for that CPU */
1093 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1095 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1096 mtspr(SPRN_SDR1, _SDR1);
1098 set_ptcr_when_no_uv(__pa(partition_tb) |
1099 (PATB_SIZE_SHIFT - 12));
1101 /* Initialize SLB */
1104 if (cpu_has_feature(CPU_FTR_ARCH_206)
1105 && cpu_has_feature(CPU_FTR_HVMODE))
1108 #endif /* CONFIG_SMP */
1111 * Called by asm hashtable.S for doing lazy icache flush
1113 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1117 if (!pfn_valid(pte_pfn(pte)))
1120 page = pte_page(pte);
1123 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1124 if (trap == 0x400) {
1125 flush_dcache_icache_page(page);
1126 set_bit(PG_arch_1, &page->flags);
1133 #ifdef CONFIG_PPC_MM_SLICES
1134 static unsigned int get_paca_psize(unsigned long addr)
1136 unsigned char *psizes;
1137 unsigned long index, mask_index;
1139 if (addr < SLICE_LOW_TOP) {
1140 psizes = get_paca()->mm_ctx_low_slices_psize;
1141 index = GET_LOW_SLICE_INDEX(addr);
1143 psizes = get_paca()->mm_ctx_high_slices_psize;
1144 index = GET_HIGH_SLICE_INDEX(addr);
1146 mask_index = index & 0x1;
1147 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1151 unsigned int get_paca_psize(unsigned long addr)
1153 return get_paca()->mm_ctx_user_psize;
1158 * Demote a segment to using 4k pages.
1159 * For now this makes the whole process use 4k pages.
1161 #ifdef CONFIG_PPC_64K_PAGES
1162 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1164 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1166 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1167 copro_flush_all_slbs(mm);
1168 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1170 copy_mm_to_paca(mm);
1171 slb_flush_and_restore_bolted();
1174 #endif /* CONFIG_PPC_64K_PAGES */
1176 #ifdef CONFIG_PPC_SUBPAGE_PROT
1178 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1179 * Userspace sets the subpage permissions using the subpage_prot system call.
1181 * Result is 0: full permissions, _PAGE_RW: read-only,
1182 * _PAGE_RWX: no access.
1184 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1186 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1193 if (ea >= spt->maxaddr)
1195 if (ea < 0x100000000UL) {
1196 /* addresses below 4GB use spt->low_prot */
1197 sbpm = spt->low_prot;
1199 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1203 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1206 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1208 /* extract 2-bit bitfield for this 4k subpage */
1209 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1212 * 0 -> full premission
1215 * We return the flag that need to be cleared.
1217 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1221 #else /* CONFIG_PPC_SUBPAGE_PROT */
1222 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1228 void hash_failure_debug(unsigned long ea, unsigned long access,
1229 unsigned long vsid, unsigned long trap,
1230 int ssize, int psize, int lpsize, unsigned long pte)
1232 if (!printk_ratelimit())
1234 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1235 ea, access, current->comm);
1236 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1237 trap, vsid, ssize, psize, lpsize, pte);
1240 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1241 int psize, bool user_region)
1244 if (psize != get_paca_psize(ea)) {
1245 copy_mm_to_paca(mm);
1246 slb_flush_and_restore_bolted();
1248 } else if (get_paca()->vmalloc_sllp !=
1249 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1250 get_paca()->vmalloc_sllp =
1251 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1252 slb_vmalloc_update();
1259 * 1 - normal page fault
1260 * -1 - critical hash insertion error
1261 * -2 - access not permitted by subpage protection mechanism
1263 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1264 unsigned long access, unsigned long trap,
1265 unsigned long flags)
1268 enum ctx_state prev_state = exception_enter();
1273 int rc, user_region = 0;
1276 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1278 trace_hash_fault(ea, access, trap);
1280 /* Get region & vsid */
1281 switch (get_region_id(ea)) {
1282 case USER_REGION_ID:
1285 DBG_LOW(" user region with no mm !\n");
1289 psize = get_slice_psize(mm, ea);
1290 ssize = user_segment_size(ea);
1291 vsid = get_user_vsid(&mm->context, ea, ssize);
1293 case VMALLOC_REGION_ID:
1294 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1295 psize = mmu_vmalloc_psize;
1296 ssize = mmu_kernel_ssize;
1300 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1301 psize = mmu_io_psize;
1302 ssize = mmu_kernel_ssize;
1307 * Send the problem up to do_page_fault()
1312 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1316 DBG_LOW("Bad address!\n");
1322 if (pgdir == NULL) {
1327 /* Check CPU locality */
1328 if (user_region && mm_is_thread_local(mm))
1329 flags |= HPTE_LOCAL_UPDATE;
1331 #ifndef CONFIG_PPC_64K_PAGES
1333 * If we use 4K pages and our psize is not 4K, then we might
1334 * be hitting a special driver mapping, and need to align the
1335 * address before we fetch the PTE.
1337 * It could also be a hugepage mapping, in which case this is
1338 * not necessary, but it's not harmful, either.
1340 if (psize != MMU_PAGE_4K)
1341 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1342 #endif /* CONFIG_PPC_64K_PAGES */
1344 /* Get PTE and page size from page tables */
1345 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1346 if (ptep == NULL || !pte_present(*ptep)) {
1347 DBG_LOW(" no PTE !\n");
1352 /* Add _PAGE_PRESENT to the required access perm */
1353 access |= _PAGE_PRESENT;
1356 * Pre-check access permissions (will be re-checked atomically
1357 * in __hash_page_XX but this pre-check is a fast path
1359 if (!check_pte_access(access, pte_val(*ptep))) {
1360 DBG_LOW(" no access !\n");
1367 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1368 trap, flags, ssize, psize);
1369 #ifdef CONFIG_HUGETLB_PAGE
1371 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1372 flags, ssize, hugeshift, psize);
1376 * if we have hugeshift, and is not transhuge with
1377 * hugetlb disabled, something is really wrong.
1383 if (current->mm == mm)
1384 check_paca_psize(ea, mm, psize, user_region);
1389 #ifndef CONFIG_PPC_64K_PAGES
1390 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1392 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1393 pte_val(*(ptep + PTRS_PER_PTE)));
1395 /* Do actual hashing */
1396 #ifdef CONFIG_PPC_64K_PAGES
1397 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1398 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1399 demote_segment_4k(mm, ea);
1400 psize = MMU_PAGE_4K;
1404 * If this PTE is non-cacheable and we have restrictions on
1405 * using non cacheable large pages, then we switch to 4k
1407 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1409 demote_segment_4k(mm, ea);
1410 psize = MMU_PAGE_4K;
1411 } else if (ea < VMALLOC_END) {
1413 * some driver did a non-cacheable mapping
1414 * in vmalloc space, so switch vmalloc
1417 printk(KERN_ALERT "Reducing vmalloc segment "
1418 "to 4kB pages because of "
1419 "non-cacheable mapping\n");
1420 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1421 copro_flush_all_slbs(mm);
1425 #endif /* CONFIG_PPC_64K_PAGES */
1427 if (current->mm == mm)
1428 check_paca_psize(ea, mm, psize, user_region);
1430 #ifdef CONFIG_PPC_64K_PAGES
1431 if (psize == MMU_PAGE_64K)
1432 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1435 #endif /* CONFIG_PPC_64K_PAGES */
1437 int spp = subpage_protection(mm, ea);
1441 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1446 * Dump some info in case of hash insertion failure, they should
1447 * never happen so it is really useful to know if/when they do
1450 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1451 psize, pte_val(*ptep));
1452 #ifndef CONFIG_PPC_64K_PAGES
1453 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1455 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1456 pte_val(*(ptep + PTRS_PER_PTE)));
1458 DBG_LOW(" -> rc=%d\n", rc);
1461 exception_exit(prev_state);
1464 EXPORT_SYMBOL_GPL(hash_page_mm);
1466 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1467 unsigned long dsisr)
1469 unsigned long flags = 0;
1470 struct mm_struct *mm = current->mm;
1472 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1473 (get_region_id(ea) == IO_REGION_ID))
1476 if (dsisr & DSISR_NOHPTE)
1477 flags |= HPTE_NOHPTE_UPDATE;
1479 return hash_page_mm(mm, ea, access, trap, flags);
1481 EXPORT_SYMBOL_GPL(hash_page);
1483 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1486 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1487 unsigned long flags = 0;
1488 struct mm_struct *mm = current->mm;
1489 unsigned int region_id = get_region_id(ea);
1491 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1494 if (dsisr & DSISR_NOHPTE)
1495 flags |= HPTE_NOHPTE_UPDATE;
1497 if (dsisr & DSISR_ISSTORE)
1498 access |= _PAGE_WRITE;
1500 * We set _PAGE_PRIVILEGED only when
1501 * kernel mode access kernel space.
1503 * _PAGE_PRIVILEGED is NOT set
1504 * 1) when kernel mode access user space
1505 * 2) user space access kernel space.
1507 access |= _PAGE_PRIVILEGED;
1508 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1509 access &= ~_PAGE_PRIVILEGED;
1512 access |= _PAGE_EXEC;
1514 return hash_page_mm(mm, ea, access, trap, flags);
1517 #ifdef CONFIG_PPC_MM_SLICES
1518 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1520 int psize = get_slice_psize(mm, ea);
1522 /* We only prefault standard pages for now */
1523 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1527 * Don't prefault if subpage protection is enabled for the EA.
1529 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1535 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1541 static void hash_preload(struct mm_struct *mm, unsigned long ea,
1542 bool is_exec, unsigned long trap)
1548 unsigned long flags;
1549 int rc, ssize, update_flags = 0;
1550 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1552 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1554 if (!should_hash_preload(mm, ea))
1557 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1558 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1560 /* Get Linux PTE if available */
1566 ssize = user_segment_size(ea);
1567 vsid = get_user_vsid(&mm->context, ea, ssize);
1571 * Hash doesn't like irqs. Walking linux page table with irq disabled
1572 * saves us from holding multiple locks.
1574 local_irq_save(flags);
1577 * THP pages use update_mmu_cache_pmd. We don't do
1578 * hash preload there. Hence can ignore THP here
1580 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1584 WARN_ON(hugepage_shift);
1585 #ifdef CONFIG_PPC_64K_PAGES
1586 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1587 * a 64K kernel), then we don't preload, hash_page() will take
1588 * care of it once we actually try to access the page.
1589 * That way we don't have to duplicate all of the logic for segment
1590 * page size demotion here
1592 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1594 #endif /* CONFIG_PPC_64K_PAGES */
1596 /* Is that local to this CPU ? */
1597 if (mm_is_thread_local(mm))
1598 update_flags |= HPTE_LOCAL_UPDATE;
1601 #ifdef CONFIG_PPC_64K_PAGES
1602 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1603 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1604 update_flags, ssize);
1606 #endif /* CONFIG_PPC_64K_PAGES */
1607 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1608 ssize, subpage_protection(mm, ea));
1610 /* Dump some info in case of hash insertion failure, they should
1611 * never happen so it is really useful to know if/when they do
1614 hash_failure_debug(ea, access, vsid, trap, ssize,
1615 mm_ctx_user_psize(&mm->context),
1616 mm_ctx_user_psize(&mm->context),
1619 local_irq_restore(flags);
1623 * This is called at the end of handling a user page fault, when the
1624 * fault has been handled by updating a PTE in the linux page tables.
1625 * We use it to preload an HPTE into the hash table corresponding to
1626 * the updated linux PTE.
1628 * This must always be called with the pte lock held.
1630 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1634 * We don't need to worry about _PAGE_PRESENT here because we are
1635 * called with either mm->page_table_lock held or ptl lock held
1640 if (radix_enabled()) {
1641 prefetch((void *)address);
1645 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1646 if (!pte_young(*ptep) || address >= TASK_SIZE)
1650 * We try to figure out if we are coming from an instruction
1651 * access fault and pass that down to __hash_page so we avoid
1652 * double-faulting on execution of fresh text. We have to test
1653 * for regs NULL since init will get here first thing at boot.
1655 * We also avoid filling the hash if not coming from a fault.
1658 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1670 hash_preload(vma->vm_mm, address, is_exec, trap);
1673 #ifdef CONFIG_PPC_MEM_KEYS
1675 * Return the protection key associated with the given address and the
1678 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1682 unsigned long flags;
1684 if (!mm || !mm->pgd)
1687 local_irq_save(flags);
1688 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1690 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1691 local_irq_restore(flags);
1695 #endif /* CONFIG_PPC_MEM_KEYS */
1697 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1698 static inline void tm_flush_hash_page(int local)
1701 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1702 * page back to a block device w/PIO could pick up transactional data
1703 * (bad!) so we force an abort here. Before the sync the page will be
1704 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1705 * kernel uses a page from userspace without unmapping it first, it may
1706 * see the speculated version.
1708 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1709 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1711 tm_abort(TM_CAUSE_TLBI);
1715 static inline void tm_flush_hash_page(int local)
1721 * Return the global hash slot, corresponding to the given PTE, which contains
1724 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1725 int ssize, real_pte_t rpte, unsigned int subpg_index)
1727 unsigned long hash, gslot, hidx;
1729 hash = hpt_hash(vpn, shift, ssize);
1730 hidx = __rpte_to_hidx(rpte, subpg_index);
1731 if (hidx & _PTEIDX_SECONDARY)
1733 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1734 gslot += hidx & _PTEIDX_GROUP_IX;
1739 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1740 * do not forget to update the assembly call site !
1742 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1743 unsigned long flags)
1745 unsigned long index, shift, gslot;
1746 int local = flags & HPTE_LOCAL_UPDATE;
1748 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1749 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1750 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1751 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1753 * We use same base page size and actual psize, because we don't
1754 * use these functions for hugepage
1756 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1758 } pte_iterate_hashed_end();
1760 tm_flush_hash_page(local);
1763 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1764 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1765 pmd_t *pmdp, unsigned int psize, int ssize,
1766 unsigned long flags)
1768 int i, max_hpte_count, valid;
1769 unsigned long s_addr;
1770 unsigned char *hpte_slot_array;
1771 unsigned long hidx, shift, vpn, hash, slot;
1772 int local = flags & HPTE_LOCAL_UPDATE;
1774 s_addr = addr & HPAGE_PMD_MASK;
1775 hpte_slot_array = get_hpte_slot_array(pmdp);
1777 * IF we try to do a HUGE PTE update after a withdraw is done.
1778 * we will find the below NULL. This happens when we do
1781 if (!hpte_slot_array)
1784 if (mmu_hash_ops.hugepage_invalidate) {
1785 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1786 psize, ssize, local);
1790 * No bluk hpte removal support, invalidate each entry
1792 shift = mmu_psize_defs[psize].shift;
1793 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1794 for (i = 0; i < max_hpte_count; i++) {
1796 * 8 bits per each hpte entries
1797 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1799 valid = hpte_valid(hpte_slot_array, i);
1802 hidx = hpte_hash_index(hpte_slot_array, i);
1805 addr = s_addr + (i * (1ul << shift));
1806 vpn = hpt_vpn(addr, vsid, ssize);
1807 hash = hpt_hash(vpn, shift, ssize);
1808 if (hidx & _PTEIDX_SECONDARY)
1811 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1812 slot += hidx & _PTEIDX_GROUP_IX;
1813 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1814 MMU_PAGE_16M, ssize, local);
1817 tm_flush_hash_page(local);
1819 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1821 void flush_hash_range(unsigned long number, int local)
1823 if (mmu_hash_ops.flush_hash_range)
1824 mmu_hash_ops.flush_hash_range(number, local);
1827 struct ppc64_tlb_batch *batch =
1828 this_cpu_ptr(&ppc64_tlb_batch);
1830 for (i = 0; i < number; i++)
1831 flush_hash_page(batch->vpn[i], batch->pte[i],
1832 batch->psize, batch->ssize, local);
1837 * low_hash_fault is called when we the low level hash code failed
1838 * to instert a PTE due to an hypervisor error
1840 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1842 enum ctx_state prev_state = exception_enter();
1844 if (user_mode(regs)) {
1845 #ifdef CONFIG_PPC_SUBPAGE_PROT
1847 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1850 _exception(SIGBUS, regs, BUS_ADRERR, address);
1852 bad_page_fault(regs, address, SIGBUS);
1854 exception_exit(prev_state);
1857 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1858 unsigned long pa, unsigned long rflags,
1859 unsigned long vflags, int psize, int ssize)
1861 unsigned long hpte_group;
1865 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1867 /* Insert into the hash table, primary slot */
1868 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1869 psize, psize, ssize);
1871 /* Primary is full, try the secondary */
1872 if (unlikely(slot == -1)) {
1873 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1874 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1875 vflags | HPTE_V_SECONDARY,
1876 psize, psize, ssize);
1879 hpte_group = (hash & htab_hash_mask) *
1882 mmu_hash_ops.hpte_remove(hpte_group);
1890 #ifdef CONFIG_DEBUG_PAGEALLOC
1891 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1894 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1895 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1896 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1899 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1901 /* Don't create HPTE entries for bad address */
1905 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1907 mmu_linear_psize, mmu_kernel_ssize);
1910 spin_lock(&linear_map_hash_lock);
1911 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1912 linear_map_hash_slots[lmi] = ret | 0x80;
1913 spin_unlock(&linear_map_hash_lock);
1916 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1918 unsigned long hash, hidx, slot;
1919 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1920 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1922 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1923 spin_lock(&linear_map_hash_lock);
1924 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1925 hidx = linear_map_hash_slots[lmi] & 0x7f;
1926 linear_map_hash_slots[lmi] = 0;
1927 spin_unlock(&linear_map_hash_lock);
1928 if (hidx & _PTEIDX_SECONDARY)
1930 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1931 slot += hidx & _PTEIDX_GROUP_IX;
1932 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1934 mmu_kernel_ssize, 0);
1937 void __kernel_map_pages(struct page *page, int numpages, int enable)
1939 unsigned long flags, vaddr, lmi;
1942 local_irq_save(flags);
1943 for (i = 0; i < numpages; i++, page++) {
1944 vaddr = (unsigned long)page_address(page);
1945 lmi = __pa(vaddr) >> PAGE_SHIFT;
1946 if (lmi >= linear_map_hash_count)
1949 kernel_map_linear_page(vaddr, lmi);
1951 kernel_unmap_linear_page(vaddr, lmi);
1953 local_irq_restore(flags);
1955 #endif /* CONFIG_DEBUG_PAGEALLOC */
1957 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1958 phys_addr_t first_memblock_size)
1961 * We don't currently support the first MEMBLOCK not mapping 0
1962 * physical on those processors
1964 BUG_ON(first_memblock_base != 0);
1967 * On virtualized systems the first entry is our RMA region aka VRMA,
1968 * non-virtualized 64-bit hash MMU systems don't have a limitation
1969 * on real mode access.
1971 * For guests on platforms before POWER9, we clamp the it limit to 1G
1972 * to avoid some funky things such as RTAS bugs etc...
1974 * On POWER9 we limit to 1TB in case the host erroneously told us that
1975 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1976 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1977 * for virtual real mode addressing and so it doesn't make sense to
1978 * have an area larger than 1TB as it can't be addressed.
1980 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1981 ppc64_rma_size = first_memblock_size;
1982 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1983 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1985 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1986 1UL << SID_SHIFT_1T);
1988 /* Finally limit subsequent allocations */
1989 memblock_set_current_limit(ppc64_rma_size);
1991 ppc64_rma_size = ULONG_MAX;
1995 #ifdef CONFIG_DEBUG_FS
1997 static int hpt_order_get(void *data, u64 *val)
1999 *val = ppc64_pft_size;
2003 static int hpt_order_set(void *data, u64 val)
2007 if (!mmu_hash_ops.resize_hpt)
2011 ret = mmu_hash_ops.resize_hpt(val);
2017 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2019 static int __init hash64_debugfs(void)
2021 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL,
2025 machine_device_initcall(pseries, hash64_debugfs);
2026 #endif /* CONFIG_DEBUG_FS */
2028 void __init print_system_hash_info(void)
2030 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2033 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);