1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Regents of the University of California
6 #ifndef _ASM_RISCV_CSR_H
7 #define _ASM_RISCV_CSR_H
10 #include <linux/const.h>
12 /* Status register flags */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14 #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
22 #define SR_FS_OFF _AC(0x00000000, UL)
23 #define SR_FS_INITIAL _AC(0x00002000, UL)
24 #define SR_FS_CLEAN _AC(0x00004000, UL)
25 #define SR_FS_DIRTY _AC(0x00006000, UL)
27 #define SR_XS _AC(0x00018000, UL) /* Extension Status */
28 #define SR_XS_OFF _AC(0x00000000, UL)
29 #define SR_XS_INITIAL _AC(0x00008000, UL)
30 #define SR_XS_CLEAN _AC(0x00010000, UL)
31 #define SR_XS_DIRTY _AC(0x00018000, UL)
34 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
36 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
41 #define SATP_PPN _AC(0x003FFFFF, UL)
42 #define SATP_MODE_32 _AC(0x80000000, UL)
43 #define SATP_MODE SATP_MODE_32
45 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
46 #define SATP_MODE_39 _AC(0x8000000000000000, UL)
47 #define SATP_MODE SATP_MODE_39
50 /* Exception cause high bit - is an interrupt if set */
51 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
53 /* Interrupt causes (minus the high bit) */
64 /* Exception causes */
65 #define EXC_INST_MISALIGNED 0
66 #define EXC_INST_ACCESS 1
67 #define EXC_BREAKPOINT 3
68 #define EXC_LOAD_ACCESS 5
69 #define EXC_STORE_ACCESS 7
71 #define EXC_INST_PAGE_FAULT 12
72 #define EXC_LOAD_PAGE_FAULT 13
73 #define EXC_STORE_PAGE_FAULT 15
75 /* symbolic CSR names: */
76 #define CSR_CYCLE 0xc00
77 #define CSR_TIME 0xc01
78 #define CSR_INSTRET 0xc02
79 #define CSR_CYCLEH 0xc80
80 #define CSR_TIMEH 0xc81
81 #define CSR_INSTRETH 0xc82
83 #define CSR_SSTATUS 0x100
85 #define CSR_STVEC 0x105
86 #define CSR_SCOUNTEREN 0x106
87 #define CSR_SSCRATCH 0x140
88 #define CSR_SEPC 0x141
89 #define CSR_SCAUSE 0x142
90 #define CSR_STVAL 0x143
92 #define CSR_SATP 0x180
94 #define CSR_MSTATUS 0x300
95 #define CSR_MISA 0x301
97 #define CSR_MTVEC 0x305
98 #define CSR_MSCRATCH 0x340
99 #define CSR_MEPC 0x341
100 #define CSR_MCAUSE 0x342
101 #define CSR_MTVAL 0x343
102 #define CSR_MIP 0x344
103 #define CSR_MHARTID 0xf14
105 #ifdef CONFIG_RISCV_M_MODE
106 # define CSR_STATUS CSR_MSTATUS
107 # define CSR_IE CSR_MIE
108 # define CSR_TVEC CSR_MTVEC
109 # define CSR_SCRATCH CSR_MSCRATCH
110 # define CSR_EPC CSR_MEPC
111 # define CSR_CAUSE CSR_MCAUSE
112 # define CSR_TVAL CSR_MTVAL
113 # define CSR_IP CSR_MIP
115 # define SR_IE SR_MIE
116 # define SR_PIE SR_MPIE
117 # define SR_PP SR_MPP
119 # define RV_IRQ_SOFT IRQ_M_SOFT
120 # define RV_IRQ_TIMER IRQ_M_TIMER
121 # define RV_IRQ_EXT IRQ_M_EXT
122 #else /* CONFIG_RISCV_M_MODE */
123 # define CSR_STATUS CSR_SSTATUS
124 # define CSR_IE CSR_SIE
125 # define CSR_TVEC CSR_STVEC
126 # define CSR_SCRATCH CSR_SSCRATCH
127 # define CSR_EPC CSR_SEPC
128 # define CSR_CAUSE CSR_SCAUSE
129 # define CSR_TVAL CSR_STVAL
130 # define CSR_IP CSR_SIP
132 # define SR_IE SR_SIE
133 # define SR_PIE SR_SPIE
134 # define SR_PP SR_SPP
136 # define RV_IRQ_SOFT IRQ_S_SOFT
137 # define RV_IRQ_TIMER IRQ_S_TIMER
138 # define RV_IRQ_EXT IRQ_S_EXT
139 #endif /* CONFIG_RISCV_M_MODE */
141 /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
142 #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
143 #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
144 #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
148 #define csr_swap(csr, val) \
150 unsigned long __v = (unsigned long)(val); \
151 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
152 : "=r" (__v) : "rK" (__v) \
157 #define csr_read(csr) \
159 register unsigned long __v; \
160 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
166 #define csr_write(csr, val) \
168 unsigned long __v = (unsigned long)(val); \
169 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
174 #define csr_read_set(csr, val) \
176 unsigned long __v = (unsigned long)(val); \
177 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
178 : "=r" (__v) : "rK" (__v) \
183 #define csr_set(csr, val) \
185 unsigned long __v = (unsigned long)(val); \
186 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
191 #define csr_read_clear(csr, val) \
193 unsigned long __v = (unsigned long)(val); \
194 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
195 : "=r" (__v) : "rK" (__v) \
200 #define csr_clear(csr, val) \
202 unsigned long __v = (unsigned long)(val); \
203 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
208 #endif /* __ASSEMBLY__ */
210 #endif /* _ASM_RISCV_CSR_H */