2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_PROCESSOR_H
16 #define _ASM_TILE_PROCESSOR_H
18 #include <arch/chip.h>
23 * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
24 * normally would, due to #include dependencies.
26 #include <linux/types.h>
27 #include <asm/ptrace.h>
28 #include <asm/percpu.h>
30 #include <arch/spr_def.h>
40 * Default implementation of macro that returns current
41 * instruction pointer ("program counter").
43 void *current_text_addr(void);
45 #if CHIP_HAS_TILE_DMA()
46 /* Capture the state of a suspended DMA. */
47 struct tile_dma_state {
51 unsigned long strides;
52 unsigned long chunk_size;
53 unsigned long src_chunk;
54 unsigned long dest_chunk;
60 * A mask of the DMA status register for selecting only the 'running'
63 #define DMA_STATUS_MASK \
64 (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
68 * Track asynchronous TLB events (faults and access violations)
69 * that occur while we are in kernel mode from DMA or the SN processor.
72 short fault_num; /* original fault number; 0 if none */
73 char is_fault; /* was it a fault (vs an access violation) */
74 char is_write; /* for fault: was it caused by a write? */
75 unsigned long address; /* what address faulted? */
78 #ifdef CONFIG_HARDWALL
80 struct hardwall_task {
81 /* Which hardwall is this task tied to? (or NULL if none) */
82 struct hardwall_info *info;
83 /* Chains this task into the list at info->task_head. */
84 struct list_head list;
87 #define HARDWALL_TYPES 1 /* udn */
89 #define HARDWALL_TYPES 3 /* udn, idn, and ipi */
93 struct thread_struct {
94 /* kernel stack pointer */
98 /* starting user stack pointer (for page migration) */
100 /* pid of process that created this one */
102 #if CHIP_HAS_TILE_DMA()
103 /* DMA info for suspended threads (byte == 0 means no DMA state) */
104 struct tile_dma_state tile_dma_state;
106 /* User EX_CONTEXT registers */
107 unsigned long ex_context[2];
108 /* User SYSTEM_SAVE registers */
109 unsigned long system_save[4];
110 /* User interrupt mask */
111 unsigned long long interrupt_mask;
112 /* User interrupt-control 0 state */
113 unsigned long intctrl_0;
114 /* Is this task currently doing a backtrace? */
116 #if CHIP_HAS_PROC_STATUS_SPR()
117 /* Any other miscellaneous processor state bits */
118 unsigned long proc_status;
120 #if !CHIP_HAS_FIXED_INTVEC_BASE()
121 /* Interrupt base for PL0 interrupts */
122 unsigned long interrupt_vector_base;
124 #if CHIP_HAS_TILE_RTF_HWM()
125 /* Tile cache retry fifo high-water mark */
126 unsigned long tile_rtf_hwm;
128 #if CHIP_HAS_DSTREAM_PF()
129 /* Data stream prefetch control */
130 unsigned long dstream_pf;
132 #ifdef CONFIG_HARDWALL
133 /* Hardwall information for various resources. */
134 struct hardwall_task hardwall[HARDWALL_TYPES];
136 #if CHIP_HAS_TILE_DMA()
137 /* Async DMA TLB fault information */
138 struct async_tlb dma_async_tlb;
140 #if CHIP_HAS_SN_PROC()
141 /* Was static network processor when we were switched out? */
143 /* Async SNI TLB fault information */
144 struct async_tlb sn_async_tlb;
148 #endif /* !__ASSEMBLY__ */
151 * Start with "sp" this many bytes below the top of the kernel stack.
152 * This allows us to be cache-aware when handling the initial save
153 * of the pt_regs value to the stack.
155 #define STACK_TOP_DELTA 64
158 * When entering the kernel via a fault, start with the top of the
159 * pt_regs structure this many bytes below the top of the page.
160 * This aligns the pt_regs structure optimally for cache-line access.
163 #define KSTK_PTREGS_GAP 48
165 #define KSTK_PTREGS_GAP 56
171 #define TASK_SIZE_MAX (MEM_LOW_END + 1)
173 #define TASK_SIZE_MAX PAGE_OFFSET
176 /* TASK_SIZE and related variables are always checked in "current" context. */
178 #define COMPAT_TASK_SIZE (1UL << 31)
179 #define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
180 COMPAT_TASK_SIZE : TASK_SIZE_MAX)
182 #define TASK_SIZE TASK_SIZE_MAX
185 #define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
186 #define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
188 #define STACK_TOP TASK_SIZE
190 /* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
191 #define STACK_TOP_MAX TASK_SIZE_MAX
194 * This decides where the kernel will search for a free chunk of vm
195 * space during mmap's, if it is using bottom-up mapping.
197 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
199 #define HAVE_ARCH_PICK_MMAP_LAYOUT
201 #define INIT_THREAD { \
202 .ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
203 .interrupt_mask = -1ULL \
206 /* Kernel stack top for the task that first boots on this cpu. */
207 DECLARE_PER_CPU(unsigned long, boot_sp);
209 /* PC to boot from on this cpu. */
210 DECLARE_PER_CPU(unsigned long, boot_pc);
212 /* Do necessary setup to start up a newly executed thread. */
213 static inline void start_thread(struct pt_regs *regs,
214 unsigned long pc, unsigned long usp)
218 single_step_execve();
221 /* Free all resources held by a thread. */
222 static inline void release_thread(struct task_struct *dead_task)
224 /* Nothing for now */
227 extern int do_work_pending(struct pt_regs *regs, u32 flags);
231 * Return saved (kernel) PC of a blocked thread.
232 * Only used in a printk() in kernel/sched/core.c, so don't work too hard.
234 #define thread_saved_pc(t) ((t)->thread.pc)
236 unsigned long get_wchan(struct task_struct *p);
238 /* Return initial ksp value for given task. */
239 #define task_ksp0(task) \
240 ((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
242 /* Return some info about the user process TASK. */
243 #define task_pt_regs(task) \
244 ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
245 #define current_pt_regs() \
246 ((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
247 STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
248 #define task_sp(task) (task_pt_regs(task)->sp)
249 #define task_pc(task) (task_pt_regs(task)->pc)
250 /* Aliases for pc and sp (used in fs/proc/array.c) */
251 #define KSTK_EIP(task) task_pc(task)
252 #define KSTK_ESP(task) task_sp(task)
254 /* Fine-grained unaligned JIT support */
255 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
256 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
258 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
259 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
261 /* Standard format for printing registers and other word-size data. */
263 # define REGFMT "0x%016lx"
265 # define REGFMT "0x%08lx"
269 * Do some slow action (e.g. read a slow SPR).
270 * Note that this must also have compiler-barrier semantics since
271 * it may be used in a busy loop reading memory.
273 static inline void cpu_relax(void)
275 __insn_mfspr(SPR_PASS);
279 /* Info on this processor (see fs/proc/cpuinfo.c) */
280 struct seq_operations;
281 extern const struct seq_operations cpuinfo_op;
283 /* Provide information about the chip model. */
284 extern char chip_model[64];
286 /* Data on which physical memory controller corresponds to which NUMA node. */
287 extern int node_controller[];
289 #if CHIP_HAS_CBOX_HOME_MAP()
290 /* Does the heap allocator return hash-for-home pages by default? */
291 extern int hash_default;
293 /* Should kernel stack pages be hash-for-home? */
294 extern int kstack_hash;
296 /* Does MAP_ANONYMOUS return hash-for-home pages by default? */
297 #define uheap_hash hash_default
300 #define hash_default 0
301 #define kstack_hash 0
305 /* Are we using huge pages in the TLB for kernel data? */
306 extern int kdata_huge;
308 /* Support standard Linux prefetching. */
309 #define ARCH_HAS_PREFETCH
310 #define prefetch(x) __builtin_prefetch(x)
311 #define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
313 /* Bring a value into the L1D, faulting the TLB if necessary. */
315 #define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
317 #define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
320 #else /* __ASSEMBLY__ */
322 /* Do some slow action (e.g. read a slow SPR). */
323 #define CPU_RELAX mfspr zero, SPR_PASS
325 #endif /* !__ASSEMBLY__ */
327 /* Assembly code assumes that the PL is in the low bits. */
328 #if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
329 # error Fix assembly assumptions about PL
332 /* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
333 #if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
334 SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
335 SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
336 SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
337 # error Fix assumptions that EX1 macros work for both PL0 and PL1
340 /* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
341 #define EX1_PL(ex1) \
342 (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
343 #define EX1_ICS(ex1) \
344 (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
345 #define PL_ICS_EX1(pl, ics) \
346 (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
347 ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
350 * Provide symbolic constants for PLs.
353 #if CONFIG_KERNEL_PL == 2
356 #define KERNEL_PL CONFIG_KERNEL_PL
358 /* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
361 #if CHIP_VA_WIDTH() > CPU_SHIFT
362 # error Too many VA bits!
364 #define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
365 #define raw_smp_processor_id() \
366 ((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
367 #define get_current_ksp0() \
368 ((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
369 (64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
370 #define next_current_ksp0(task) ({ \
371 unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
372 unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
376 #define LOG2_NR_CPU_IDS 6
377 #define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
378 #define raw_smp_processor_id() \
379 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
380 #define get_current_ksp0() \
381 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
382 #define next_current_ksp0(task) ({ \
383 unsigned long __ksp0 = task_ksp0(task); \
384 int __cpu = raw_smp_processor_id(); \
385 BUG_ON(__ksp0 & MAX_CPU_ID); \
389 #if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
390 # error Too many cpus!
393 #endif /* _ASM_TILE_PROCESSOR_H */