arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14
  15 /*
  16  * While not explicitly listed in the TLFS, Hyper-V always runs with a page size
  17  * of 4096. These definitions are used when communicating with Hyper-V using
  18  * guest physical pages and guest physical page addresses, since the guest page
  19  * size may not be 4096 on all architectures.
  20  */
  21 #define HV_HYP_PAGE_SHIFT      12
  22 #define HV_HYP_PAGE_SIZE       BIT(HV_HYP_PAGE_SHIFT)
  23 #define HV_HYP_PAGE_MASK       (~(HV_HYP_PAGE_SIZE - 1))
  24
  25 /*
  26  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  27  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  28  */
  29 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  30 #define HYPERV_CPUID_INTERFACE                  0x40000001
  31 #define HYPERV_CPUID_VERSION                    0x40000002
  32 #define HYPERV_CPUID_FEATURES                   0x40000003
  33 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  34 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  35 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  36
  37 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  38 #define HYPERV_CPUID_MIN                        0x40000005
  39 #define HYPERV_CPUID_MAX                        0x4000ffff
  40
  41 /*
  42  * Feature identification. EAX indicates which features are available
  43  * to the partition based upon the current partition privileges.
  44  * These are HYPERV_CPUID_FEATURES.EAX bits.
  45  */
  46
  47 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  48 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         BIT(0)
  49 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  50 #define HV_MSR_TIME_REF_COUNT_AVAILABLE         BIT(1)
  51 /*
  52  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  53  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  54  */
  55 #define HV_X64_MSR_SYNIC_AVAILABLE              BIT(2)
  56 /*
  57  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  58  * HV_X64_MSR_STIMER3_COUNT) available
  59  */
  60 #define HV_MSR_SYNTIMER_AVAILABLE               BIT(3)
  61 /*
  62  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  63  * are available
  64  */
  65 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        BIT(4)
  66 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  67 #define HV_X64_MSR_HYPERCALL_AVAILABLE          BIT(5)
  68 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  69 #define HV_X64_MSR_VP_INDEX_AVAILABLE           BIT(6)
  70 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  71 #define HV_X64_MSR_RESET_AVAILABLE              BIT(7)
  72 /*
  73  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  74  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  75  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  76  */
  77 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         BIT(8)
  78 /* Partition reference TSC MSR is available */
  79 #define HV_MSR_REFERENCE_TSC_AVAILABLE          BIT(9)
  80 /* Partition Guest IDLE MSR is available */
  81 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE         BIT(10)
  82 /*
  83  * There is a single feature flag that signifies if the partition has access
  84  * to MSRs with local APIC and TSC frequencies.
  85  */
  86 #define HV_X64_ACCESS_FREQUENCY_MSRS            BIT(11)
  87 /* AccessReenlightenmentControls privilege */
  88 #define HV_X64_ACCESS_REENLIGHTENMENT           BIT(13)
  89 /* AccessTscInvariantControls privilege */
  90 #define HV_X64_ACCESS_TSC_INVARIANT             BIT(15)
  91
  92 /*
  93  * Feature identification: indicates which flags were specified at partition
  94  * creation. The format is the same as the partition creation flag structure
  95  * defined in section Partition Creation Flags.
  96  * These are HYPERV_CPUID_FEATURES.EBX bits.
  97  */
  98 #define HV_X64_CREATE_PARTITIONS                BIT(0)
  99 #define HV_X64_ACCESS_PARTITION_ID              BIT(1)
 100 #define HV_X64_ACCESS_MEMORY_POOL               BIT(2)
 101 #define HV_X64_ADJUST_MESSAGE_BUFFERS           BIT(3)
 102 #define HV_X64_POST_MESSAGES                    BIT(4)
 103 #define HV_X64_SIGNAL_EVENTS                    BIT(5)
 104 #define HV_X64_CREATE_PORT                      BIT(6)
 105 #define HV_X64_CONNECT_PORT                     BIT(7)
 106 #define HV_X64_ACCESS_STATS                     BIT(8)
 107 #define HV_X64_DEBUGGING                        BIT(11)
 108 #define HV_X64_CPU_POWER_MANAGEMENT             BIT(12)
 109
 110 /*
 111  * Feature identification. EDX indicates which miscellaneous features
 112  * are available to the partition.
 113  * These are HYPERV_CPUID_FEATURES.EDX bits.
 114  */
 115 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
 116 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
 117 /* Guest debugging support is available */
 118 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
 119 /* Performance Monitor support is available*/
 120 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
 121 /* Support for physical CPU dynamic partitioning events is available*/
 122 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
 123 /*
 124  * Support for passing hypercall input parameter block via XMM
 125  * registers is available
 126  */
 127 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           BIT(4)
 128 /* Support for a virtual guest idle state is available */
 129 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
 130 /* Frequency MSRs available */
 131 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
 132 /* Crash MSR available */
 133 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
 134 /* Support for debug MSRs available */
 135 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE                 BIT(11)
 136 /* stimer Direct Mode is available */
 137 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
 138
 139 /*
 140  * Implementation recommendations. Indicates which behaviors the hypervisor
 141  * recommends the OS implement for optimal performance.
 142  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
 143  */
 144 /*
 145  * Recommend using hypercall for address space switches rather
 146  * than MOV to CR3 instruction
 147  */
 148 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
 149 /* Recommend using hypercall for local TLB flushes rather
 150  * than INVLPG or MOV to CR3 instructions */
 151 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
 152 /*
 153  * Recommend using hypercall for remote TLB flushes rather
 154  * than inter-processor interrupts
 155  */
 156 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
 157 /*
 158  * Recommend using MSRs for accessing APIC registers
 159  * EOI, ICR and TPR rather than their memory-mapped counterparts
 160  */
 161 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
 162 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 163 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
 164 /*
 165  * Recommend using relaxed timing for this partition. If used,
 166  * the VM should disable any watchdog timeouts that rely on the
 167  * timely delivery of external interrupts
 168  */
 169 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 170
 171 /*
 172  * Recommend not using Auto End-Of-Interrupt feature
 173  */
 174 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 175
 176 /*
 177  * Recommend using cluster IPI hypercalls.
 178  */
 179 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 180
 181 /* Recommend using the newer ExProcessorMasks interface */
 182 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 183
 184 /* Recommend using enlightened VMCS */
 185 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 186
 187 /*
 188  * Virtual processor will never share a physical core with another virtual
 189  * processor, except for virtual processors that are reported as sibling SMT
 190  * threads.
 191  */
 192 #define HV_X64_NO_NONARCH_CORESHARING                  BIT(18)
 193
 194 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 195 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 196 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 197 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 198
 199 /* Hyper-V specific model specific registers (MSRs) */
 200
 201 /* MSR used to identify the guest OS. */
 202 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 203
 204 /* MSR used to setup pages used to communicate with the hypervisor. */
 205 #define HV_X64_MSR_HYPERCALL                    0x40000001
 206
 207 /* MSR used to provide vcpu index */
 208 #define HV_X64_MSR_VP_INDEX                     0x40000002
 209
 210 /* MSR used to reset the guest OS. */
 211 #define HV_X64_MSR_RESET                        0x40000003
 212
 213 /* MSR used to provide vcpu runtime in 100ns units */
 214 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 215
 216 /* MSR used to read the per-partition time reference counter */
 217 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 218
 219 /* A partition's reference time stamp counter (TSC) page */
 220 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
 221
 222 /* MSR used to retrieve the TSC frequency */
 223 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 224
 225 /* MSR used to retrieve the local APIC timer frequency */
 226 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 227
 228 /* Define the virtual APIC registers */
 229 #define HV_X64_MSR_EOI                          0x40000070
 230 #define HV_X64_MSR_ICR                          0x40000071
 231 #define HV_X64_MSR_TPR                          0x40000072
 232 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 233
 234 /* Define synthetic interrupt controller model specific registers. */
 235 #define HV_X64_MSR_SCONTROL                     0x40000080
 236 #define HV_X64_MSR_SVERSION                     0x40000081
 237 #define HV_X64_MSR_SIEFP                        0x40000082
 238 #define HV_X64_MSR_SIMP                         0x40000083
 239 #define HV_X64_MSR_EOM                          0x40000084
 240 #define HV_X64_MSR_SINT0                        0x40000090
 241 #define HV_X64_MSR_SINT1                        0x40000091
 242 #define HV_X64_MSR_SINT2                        0x40000092
 243 #define HV_X64_MSR_SINT3                        0x40000093
 244 #define HV_X64_MSR_SINT4                        0x40000094
 245 #define HV_X64_MSR_SINT5                        0x40000095
 246 #define HV_X64_MSR_SINT6                        0x40000096
 247 #define HV_X64_MSR_SINT7                        0x40000097
 248 #define HV_X64_MSR_SINT8                        0x40000098
 249 #define HV_X64_MSR_SINT9                        0x40000099
 250 #define HV_X64_MSR_SINT10                       0x4000009A
 251 #define HV_X64_MSR_SINT11                       0x4000009B
 252 #define HV_X64_MSR_SINT12                       0x4000009C
 253 #define HV_X64_MSR_SINT13                       0x4000009D
 254 #define HV_X64_MSR_SINT14                       0x4000009E
 255 #define HV_X64_MSR_SINT15                       0x4000009F
 256
 257 /*
 258  * Synthetic Timer MSRs. Four timers per vcpu.
 259  */
 260 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 261 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 262 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 263 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 264 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 265 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 266 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 267 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 268
 269 /* Hyper-V guest idle MSR */
 270 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 271
 272 /* Hyper-V guest crash notification MSR's */
 273 #define HV_X64_MSR_CRASH_P0                     0x40000100
 274 #define HV_X64_MSR_CRASH_P1                     0x40000101
 275 #define HV_X64_MSR_CRASH_P2                     0x40000102
 276 #define HV_X64_MSR_CRASH_P3                     0x40000103
 277 #define HV_X64_MSR_CRASH_P4                     0x40000104
 278 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 279
 280 /* TSC emulation after migration */
 281 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 282 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 283 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 284
 285 /* TSC invariant control */
 286 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 287
 288 /*
 289  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 290  */
 291 union hv_x64_msr_hypercall_contents {
 292         u64 as_uint64;
 293         struct {
 294                 u64 enable:1;
 295                 u64 reserved:11;
 296                 u64 guest_physical_address:52;
 297         } __packed;
 298 };
 299
 300 /*
 301  * TSC page layout.
 302  */
 303 struct ms_hyperv_tsc_page {
 304         volatile u32 tsc_sequence;
 305         u32 reserved1;
 306         volatile u64 tsc_scale;
 307         volatile s64 tsc_offset;
 308         u64 reserved2[509];
 309 }  __packed;
 310
 311 /*
 312  * The guest OS needs to register the guest ID with the hypervisor.
 313  * The guest ID is a 64 bit entity and the structure of this ID is
 314  * specified in the Hyper-V specification:
 315  *
 316  * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx
 317  *
 318  * While the current guideline does not specify how Linux guest ID(s)
 319  * need to be generated, our plan is to publish the guidelines for
 320  * Linux and other guest operating systems that currently are hosted
 321  * on Hyper-V. The implementation here conforms to this yet
 322  * unpublished guidelines.
 323  *
 324  *
 325  * Bit(s)
 326  * 63 - Indicates if the OS is Open Source or not; 1 is Open Source
 327  * 62:56 - Os Type; Linux is 0x100
 328  * 55:48 - Distro specific identification
 329  * 47:16 - Linux kernel version number
 330  * 15:0  - Distro specific identification
 331  *
 332  *
 333  */
 334
 335 #define HV_LINUX_VENDOR_ID              0x8100
 336
 337 struct hv_reenlightenment_control {
 338         __u64 vector:8;
 339         __u64 reserved1:8;
 340         __u64 enabled:1;
 341         __u64 reserved2:15;
 342         __u64 target_vp:32;
 343 }  __packed;
 344
 345 struct hv_tsc_emulation_control {
 346         __u64 enabled:1;
 347         __u64 reserved:63;
 348 } __packed;
 349
 350 struct hv_tsc_emulation_status {
 351         __u64 inprogress:1;
 352         __u64 reserved:63;
 353 } __packed;
 354
 355 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 356 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 357 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 358                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 359
 360 /*
 361  * Crash notification (HV_X64_MSR_CRASH_CTL) flags.
 362  */
 363 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG           BIT_ULL(62)
 364 #define HV_CRASH_CTL_CRASH_NOTIFY               BIT_ULL(63)
 365 #define HV_X64_MSR_CRASH_PARAMS         \
 366                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 367
 368 #define HV_IPI_LOW_VECTOR       0x10
 369 #define HV_IPI_HIGH_VECTOR      0xff
 370
 371 /* Declare the various hypercall operations. */
 372 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 373 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 374 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 375 #define HVCALL_SEND_IPI                         0x000b
 376 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 377 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 378 #define HVCALL_SEND_IPI_EX                      0x0015
 379 #define HVCALL_POST_MESSAGE                     0x005c
 380 #define HVCALL_SIGNAL_EVENT                     0x005d
 381 #define HVCALL_POST_DEBUG_DATA                  0x0069
 382 #define HVCALL_RETRIEVE_DEBUG_DATA              0x006a
 383 #define HVCALL_RESET_DEBUG_SESSION              0x006b
 384 #define HVCALL_RETARGET_INTERRUPT               0x007e
 385 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
 386 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
 387
 388 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 389 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 390 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 391                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 392
 393 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 394 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 395
 396 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 397 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 398
 399 #define HV_PROCESSOR_POWER_STATE_C0             0
 400 #define HV_PROCESSOR_POWER_STATE_C1             1
 401 #define HV_PROCESSOR_POWER_STATE_C2             2
 402 #define HV_PROCESSOR_POWER_STATE_C3             3
 403
 404 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 405 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 406 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 407 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 408
 409 enum HV_GENERIC_SET_FORMAT {
 410         HV_GENERIC_SET_SPARSE_4K,
 411         HV_GENERIC_SET_ALL,
 412 };
 413
 414 #define HV_PARTITION_ID_SELF                    ((u64)-1)
 415
 416 #define HV_HYPERCALL_RESULT_MASK        GENMASK_ULL(15, 0)
 417 #define HV_HYPERCALL_FAST_BIT           BIT(16)
 418 #define HV_HYPERCALL_VARHEAD_OFFSET     17
 419 #define HV_HYPERCALL_REP_COMP_OFFSET    32
 420 #define HV_HYPERCALL_REP_COMP_MASK      GENMASK_ULL(43, 32)
 421 #define HV_HYPERCALL_REP_START_OFFSET   48
 422 #define HV_HYPERCALL_REP_START_MASK     GENMASK_ULL(59, 48)
 423
 424 /* hypercall status code */
 425 #define HV_STATUS_SUCCESS                       0
 426 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 427 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 428 #define HV_STATUS_INVALID_ALIGNMENT             4
 429 #define HV_STATUS_INVALID_PARAMETER             5
 430 #define HV_STATUS_OPERATION_DENIED              8
 431 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 432 #define HV_STATUS_INVALID_PORT_ID               17
 433 #define HV_STATUS_INVALID_CONNECTION_ID         18
 434 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 435
 436 /*
 437  * The Hyper-V TimeRefCount register and the TSC
 438  * page provide a guest VM clock with 100ns tick rate
 439  */
 440 #define HV_CLOCK_HZ (NSEC_PER_SEC/100)
 441
 442 typedef struct _HV_REFERENCE_TSC_PAGE {
 443         __u32 tsc_sequence;
 444         __u32 res1;
 445         __u64 tsc_scale;
 446         __s64 tsc_offset;
 447 }  __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 448
 449 /* Define the number of synthetic interrupt sources. */
 450 #define HV_SYNIC_SINT_COUNT             (16)
 451 /* Define the expected SynIC version. */
 452 #define HV_SYNIC_VERSION_1              (0x1)
 453 /* Valid SynIC vectors are 16-255. */
 454 #define HV_SYNIC_FIRST_VALID_VECTOR     (16)
 455
 456 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 457 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 458 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 459 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 460 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 461 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 462
 463 #define HV_SYNIC_STIMER_COUNT           (4)
 464
 465 /* Define synthetic interrupt controller message constants. */
 466 #define HV_MESSAGE_SIZE                 (256)
 467 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 468 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 469
 470 /* Define hypervisor message types. */
 471 enum hv_message_type {
 472         HVMSG_NONE                      = 0x00000000,
 473
 474         /* Memory access messages. */
 475         HVMSG_UNMAPPED_GPA              = 0x80000000,
 476         HVMSG_GPA_INTERCEPT             = 0x80000001,
 477
 478         /* Timer notification messages. */
 479         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 480
 481         /* Error messages. */
 482         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 483         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 484         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 485
 486         /* Trace buffer complete messages. */
 487         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 488
 489         /* Platform-specific processor intercept messages. */
 490         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 491         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 492         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 493         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 494         HVMSG_X64_APIC_EOI                      = 0x80010004,
 495         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 496 };
 497
 498 /* Define synthetic interrupt controller message flags. */
 499 union hv_message_flags {
 500         __u8 asu8;
 501         struct {
 502                 __u8 msg_pending:1;
 503                 __u8 reserved:7;
 504         } __packed;
 505 };
 506
 507 /* Define port identifier type. */
 508 union hv_port_id {
 509         __u32 asu32;
 510         struct {
 511                 __u32 id:24;
 512                 __u32 reserved:8;
 513         } __packed u;
 514 };
 515
 516 /* Define synthetic interrupt controller message header. */
 517 struct hv_message_header {
 518         __u32 message_type;
 519         __u8 payload_size;
 520         union hv_message_flags message_flags;
 521         __u8 reserved[2];
 522         union {
 523                 __u64 sender;
 524                 union hv_port_id port;
 525         };
 526 } __packed;
 527
 528 /* Define synthetic interrupt controller message format. */
 529 struct hv_message {
 530         struct hv_message_header header;
 531         union {
 532                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 533         } u;
 534 } __packed;
 535
 536 /* Define the synthetic interrupt message page layout. */
 537 struct hv_message_page {
 538         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 539 } __packed;
 540
 541 /* Define timer message payload structure. */
 542 struct hv_timer_message_payload {
 543         __u32 timer_index;
 544         __u32 reserved;
 545         __u64 expiration_time;  /* When the timer expired */
 546         __u64 delivery_time;    /* When the message was delivered */
 547 } __packed;
 548
 549 struct hv_nested_enlightenments_control {
 550         struct {
 551                 __u32 directhypercall:1;
 552                 __u32 reserved:31;
 553         } features;
 554         struct {
 555                 __u32 reserved;
 556         } hypercallControls;
 557 } __packed;
 558
 559 /* Define virtual processor assist page structure. */
 560 struct hv_vp_assist_page {
 561         __u32 apic_assist;
 562         __u32 reserved1;
 563         __u64 vtl_control[3];
 564         struct hv_nested_enlightenments_control nested_control;
 565         __u8 enlighten_vmentry;
 566         __u8 reserved2[7];
 567         __u64 current_nested_vmcs;
 568 } __packed;
 569
 570 struct hv_enlightened_vmcs {
 571         u32 revision_id;
 572         u32 abort;
 573
 574         u16 host_es_selector;
 575         u16 host_cs_selector;
 576         u16 host_ss_selector;
 577         u16 host_ds_selector;
 578         u16 host_fs_selector;
 579         u16 host_gs_selector;
 580         u16 host_tr_selector;
 581
 582         u16 padding16_1;
 583
 584         u64 host_ia32_pat;
 585         u64 host_ia32_efer;
 586
 587         u64 host_cr0;
 588         u64 host_cr3;
 589         u64 host_cr4;
 590
 591         u64 host_ia32_sysenter_esp;
 592         u64 host_ia32_sysenter_eip;
 593         u64 host_rip;
 594         u32 host_ia32_sysenter_cs;
 595
 596         u32 pin_based_vm_exec_control;
 597         u32 vm_exit_controls;
 598         u32 secondary_vm_exec_control;
 599
 600         u64 io_bitmap_a;
 601         u64 io_bitmap_b;
 602         u64 msr_bitmap;
 603
 604         u16 guest_es_selector;
 605         u16 guest_cs_selector;
 606         u16 guest_ss_selector;
 607         u16 guest_ds_selector;
 608         u16 guest_fs_selector;
 609         u16 guest_gs_selector;
 610         u16 guest_ldtr_selector;
 611         u16 guest_tr_selector;
 612
 613         u32 guest_es_limit;
 614         u32 guest_cs_limit;
 615         u32 guest_ss_limit;
 616         u32 guest_ds_limit;
 617         u32 guest_fs_limit;
 618         u32 guest_gs_limit;
 619         u32 guest_ldtr_limit;
 620         u32 guest_tr_limit;
 621         u32 guest_gdtr_limit;
 622         u32 guest_idtr_limit;
 623
 624         u32 guest_es_ar_bytes;
 625         u32 guest_cs_ar_bytes;
 626         u32 guest_ss_ar_bytes;
 627         u32 guest_ds_ar_bytes;
 628         u32 guest_fs_ar_bytes;
 629         u32 guest_gs_ar_bytes;
 630         u32 guest_ldtr_ar_bytes;
 631         u32 guest_tr_ar_bytes;
 632
 633         u64 guest_es_base;
 634         u64 guest_cs_base;
 635         u64 guest_ss_base;
 636         u64 guest_ds_base;
 637         u64 guest_fs_base;
 638         u64 guest_gs_base;
 639         u64 guest_ldtr_base;
 640         u64 guest_tr_base;
 641         u64 guest_gdtr_base;
 642         u64 guest_idtr_base;
 643
 644         u64 padding64_1[3];
 645
 646         u64 vm_exit_msr_store_addr;
 647         u64 vm_exit_msr_load_addr;
 648         u64 vm_entry_msr_load_addr;
 649
 650         u64 cr3_target_value0;
 651         u64 cr3_target_value1;
 652         u64 cr3_target_value2;
 653         u64 cr3_target_value3;
 654
 655         u32 page_fault_error_code_mask;
 656         u32 page_fault_error_code_match;
 657
 658         u32 cr3_target_count;
 659         u32 vm_exit_msr_store_count;
 660         u32 vm_exit_msr_load_count;
 661         u32 vm_entry_msr_load_count;
 662
 663         u64 tsc_offset;
 664         u64 virtual_apic_page_addr;
 665         u64 vmcs_link_pointer;
 666
 667         u64 guest_ia32_debugctl;
 668         u64 guest_ia32_pat;
 669         u64 guest_ia32_efer;
 670
 671         u64 guest_pdptr0;
 672         u64 guest_pdptr1;
 673         u64 guest_pdptr2;
 674         u64 guest_pdptr3;
 675
 676         u64 guest_pending_dbg_exceptions;
 677         u64 guest_sysenter_esp;
 678         u64 guest_sysenter_eip;
 679
 680         u32 guest_activity_state;
 681         u32 guest_sysenter_cs;
 682
 683         u64 cr0_guest_host_mask;
 684         u64 cr4_guest_host_mask;
 685         u64 cr0_read_shadow;
 686         u64 cr4_read_shadow;
 687         u64 guest_cr0;
 688         u64 guest_cr3;
 689         u64 guest_cr4;
 690         u64 guest_dr7;
 691
 692         u64 host_fs_base;
 693         u64 host_gs_base;
 694         u64 host_tr_base;
 695         u64 host_gdtr_base;
 696         u64 host_idtr_base;
 697         u64 host_rsp;
 698
 699         u64 ept_pointer;
 700
 701         u16 virtual_processor_id;
 702         u16 padding16_2[3];
 703
 704         u64 padding64_2[5];
 705         u64 guest_physical_address;
 706
 707         u32 vm_instruction_error;
 708         u32 vm_exit_reason;
 709         u32 vm_exit_intr_info;
 710         u32 vm_exit_intr_error_code;
 711         u32 idt_vectoring_info_field;
 712         u32 idt_vectoring_error_code;
 713         u32 vm_exit_instruction_len;
 714         u32 vmx_instruction_info;
 715
 716         u64 exit_qualification;
 717         u64 exit_io_instruction_ecx;
 718         u64 exit_io_instruction_esi;
 719         u64 exit_io_instruction_edi;
 720         u64 exit_io_instruction_eip;
 721
 722         u64 guest_linear_address;
 723         u64 guest_rsp;
 724         u64 guest_rflags;
 725
 726         u32 guest_interruptibility_info;
 727         u32 cpu_based_vm_exec_control;
 728         u32 exception_bitmap;
 729         u32 vm_entry_controls;
 730         u32 vm_entry_intr_info_field;
 731         u32 vm_entry_exception_error_code;
 732         u32 vm_entry_instruction_len;
 733         u32 tpr_threshold;
 734
 735         u64 guest_rip;
 736
 737         u32 hv_clean_fields;
 738         u32 hv_padding_32;
 739         u32 hv_synthetic_controls;
 740         struct {
 741                 u32 nested_flush_hypercall:1;
 742                 u32 msr_bitmap:1;
 743                 u32 reserved:30;
 744         }  __packed hv_enlightenments_control;
 745         u32 hv_vp_id;
 746
 747         u64 hv_vm_id;
 748         u64 partition_assist_page;
 749         u64 padding64_4[4];
 750         u64 guest_bndcfgs;
 751         u64 padding64_5[7];
 752         u64 xss_exit_bitmap;
 753         u64 padding64_6[7];
 754 } __packed;
 755
 756 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 757 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 758 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 759 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 760 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 761 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 762 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 763 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 764 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 765 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 766 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 767 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 768 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 769 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 770 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 771 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 772 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 773
 774 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 775
 776 /* Define synthetic interrupt controller flag constants. */
 777 #define HV_EVENT_FLAGS_COUNT            (256 * 8)
 778 #define HV_EVENT_FLAGS_LONG_COUNT       (256 / sizeof(unsigned long))
 779
 780 /*
 781  * Synthetic timer configuration.
 782  */
 783 union hv_stimer_config {
 784         u64 as_uint64;
 785         struct {
 786                 u64 enable:1;
 787                 u64 periodic:1;
 788                 u64 lazy:1;
 789                 u64 auto_enable:1;
 790                 u64 apic_vector:8;
 791                 u64 direct_mode:1;
 792                 u64 reserved_z0:3;
 793                 u64 sintx:4;
 794                 u64 reserved_z1:44;
 795         } __packed;
 796 };
 797
 798
 799 /* Define the synthetic interrupt controller event flags format. */
 800 union hv_synic_event_flags {
 801         unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT];
 802 };
 803
 804 /* Define SynIC control register. */
 805 union hv_synic_scontrol {
 806         u64 as_uint64;
 807         struct {
 808                 u64 enable:1;
 809                 u64 reserved:63;
 810         } __packed;
 811 };
 812
 813 /* Define synthetic interrupt source. */
 814 union hv_synic_sint {
 815         u64 as_uint64;
 816         struct {
 817                 u64 vector:8;
 818                 u64 reserved1:8;
 819                 u64 masked:1;
 820                 u64 auto_eoi:1;
 821                 u64 polling:1;
 822                 u64 reserved2:45;
 823         } __packed;
 824 };
 825
 826 /* Define the format of the SIMP register */
 827 union hv_synic_simp {
 828         u64 as_uint64;
 829         struct {
 830                 u64 simp_enabled:1;
 831                 u64 preserved:11;
 832                 u64 base_simp_gpa:52;
 833         } __packed;
 834 };
 835
 836 /* Define the format of the SIEFP register */
 837 union hv_synic_siefp {
 838         u64 as_uint64;
 839         struct {
 840                 u64 siefp_enabled:1;
 841                 u64 preserved:11;
 842                 u64 base_siefp_gpa:52;
 843         } __packed;
 844 };
 845
 846 struct hv_vpset {
 847         u64 format;
 848         u64 valid_bank_mask;
 849         u64 bank_contents[];
 850 } __packed;
 851
 852 /* HvCallSendSyntheticClusterIpi hypercall */
 853 struct hv_send_ipi {
 854         u32 vector;
 855         u32 reserved;
 856         u64 cpu_mask;
 857 } __packed;
 858
 859 /* HvCallSendSyntheticClusterIpiEx hypercall */
 860 struct hv_send_ipi_ex {
 861         u32 vector;
 862         u32 reserved;
 863         struct hv_vpset vp_set;
 864 } __packed;
 865
 866 /* HvFlushGuestPhysicalAddressSpace hypercalls */
 867 struct hv_guest_mapping_flush {
 868         u64 address_space;
 869         u64 flags;
 870 } __packed;
 871
 872 /*
 873  *  HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
 874  *  by the bitwidth of "additional_pages" in union hv_gpa_page_range.
 875  */
 876 #define HV_MAX_FLUSH_PAGES (2048)
 877
 878 /* HvFlushGuestPhysicalAddressList hypercall */
 879 union hv_gpa_page_range {
 880         u64 address_space;
 881         struct {
 882                 u64 additional_pages:11;
 883                 u64 largepage:1;
 884                 u64 basepfn:52;
 885         } page;
 886 };
 887
 888 /*
 889  * All input flush parameters should be in single page. The max flush
 890  * count is equal with how many entries of union hv_gpa_page_range can
 891  * be populated into the input parameter page.
 892  */
 893 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) /  \
 894                                 sizeof(union hv_gpa_page_range))
 895
 896 struct hv_guest_mapping_flush_list {
 897         u64 address_space;
 898         u64 flags;
 899         union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
 900 };
 901
 902 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */
 903 struct hv_tlb_flush {
 904         u64 address_space;
 905         u64 flags;
 906         u64 processor_mask;
 907         u64 gva_list[];
 908 } __packed;
 909
 910 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
 911 struct hv_tlb_flush_ex {
 912         u64 address_space;
 913         u64 flags;
 914         struct hv_vpset hv_vp_set;
 915         u64 gva_list[];
 916 } __packed;
 917
 918 struct hv_partition_assist_pg {
 919         u32 tlb_lock_count;
 920 };
 921
 922 union hv_msi_entry {
 923         u64 as_uint64;
 924         struct {
 925                 u32 address;
 926                 u32 data;
 927         } __packed;
 928 };
 929
 930 struct hv_interrupt_entry {
 931         u32 source;                     /* 1 for MSI(-X) */
 932         u32 reserved1;
 933         union hv_msi_entry msi_entry;
 934 } __packed;
 935
 936 /*
 937  * flags for hv_device_interrupt_target.flags
 938  */
 939 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST            1
 940 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET        2
 941
 942 struct hv_device_interrupt_target {
 943         u32 vector;
 944         u32 flags;
 945         union {
 946                 u64 vp_mask;
 947                 struct hv_vpset vp_set;
 948         };
 949 } __packed;
 950
 951 /* HvRetargetDeviceInterrupt hypercall */
 952 struct hv_retarget_device_interrupt {
 953         u64 partition_id;               /* use "self" */
 954         u64 device_id;
 955         struct hv_interrupt_entry int_entry;
 956         u64 reserved2;
 957         struct hv_device_interrupt_target int_target;
 958 } __packed __aligned(8);
 959 #endif