1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
37 * Based on this we disable the IP header alignment in network drivers.
39 #define NET_IP_ALIGN 0
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
46 static inline void *current_text_addr(void)
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
56 * These alignment constraints are for performance in the vSMP case,
57 * but in the task_struct case we must also meet hardware imposed
58 * alignment requirements of the FPU state:
60 #ifdef CONFIG_X86_VSMP
61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
65 # define ARCH_MIN_MMSTRUCT_ALIGN 0
73 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
74 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
75 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
76 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
77 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
78 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
82 * CPU type and hardware bug flags. Kept separately for each CPU.
83 * Members of this structure are referenced in head.S, so think twice
84 * before touching them. [mj]
88 __u8 x86; /* CPU family */
89 __u8 x86_vendor; /* CPU vendor */
93 char wp_works_ok; /* It doesn't on 386's */
95 /* Problems on some 486Dx4's and old 386's: */
100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
105 /* CPUID returned core id bits: */
106 __u8 x86_coreid_bits;
108 /* Max extended CPUID function supported: */
109 __u32 extended_cpuid_level;
110 /* Maximum supported CPUID level, -1=no CPUID: */
112 __u32 x86_capability[NCAPINTS + NBUGINTS];
113 char x86_vendor_id[16];
114 char x86_model_id[64];
115 /* in KB - valid for CPUS which support this call: */
117 int x86_cache_alignment; /* In bytes */
118 /* Cache QoS architectural values: */
119 int x86_cache_max_rmid; /* max index */
120 int x86_cache_occ_scale; /* scale to bytes */
122 unsigned long loops_per_jiffy;
123 /* cpuid returned max cores value: */
127 u16 x86_clflush_size;
128 /* number of cores as seen by the OS: */
130 /* Physical processor id: */
132 /* Logical processor id: */
136 /* Index into per_cpu list: */
141 #define X86_VENDOR_INTEL 0
142 #define X86_VENDOR_CYRIX 1
143 #define X86_VENDOR_AMD 2
144 #define X86_VENDOR_UMC 3
145 #define X86_VENDOR_CENTAUR 5
146 #define X86_VENDOR_TRANSMETA 7
147 #define X86_VENDOR_NSC 8
148 #define X86_VENDOR_NUM 9
150 #define X86_VENDOR_UNKNOWN 0xff
153 * capabilities of CPUs
155 extern struct cpuinfo_x86 boot_cpu_data;
156 extern struct cpuinfo_x86 new_cpu_data;
158 extern struct tss_struct doublefault_tss;
159 extern __u32 cpu_caps_cleared[NCAPINTS];
160 extern __u32 cpu_caps_set[NCAPINTS];
163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
164 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
166 #define cpu_info boot_cpu_data
167 #define cpu_data(cpu) boot_cpu_data
170 extern const struct seq_operations cpuinfo_op;
172 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
174 extern void cpu_detect(struct cpuinfo_x86 *c);
176 extern void early_cpu_init(void);
177 extern void identify_boot_cpu(void);
178 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
179 extern void print_cpu_info(struct cpuinfo_x86 *);
180 void print_cpu_msr(struct cpuinfo_x86 *);
181 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
182 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
183 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
185 extern void detect_extended_topology(struct cpuinfo_x86 *c);
186 extern void detect_ht(struct cpuinfo_x86 *c);
189 extern int have_cpuid_p(void);
191 static inline int have_cpuid_p(void)
196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
197 unsigned int *ecx, unsigned int *edx)
199 /* ecx is often an input as well as an output. */
205 : "0" (*eax), "2" (*ecx)
209 static inline void load_cr3(pgd_t *pgdir)
211 write_cr3(__pa(pgdir));
215 /* This is the TSS defined by the hardware. */
217 unsigned short back_link, __blh;
219 unsigned short ss0, __ss0h;
223 * We don't use ring 1, so ss1 is a convenient scratch space in
224 * the same cacheline as sp0. We use ss1 to cache the value in
225 * MSR_IA32_SYSENTER_CS. When we context switch
226 * MSR_IA32_SYSENTER_CS, we first check if the new value being
227 * written matches ss1, and, if it's not, then we wrmsr the new
228 * value and update ss1.
230 * The only reason we context switch MSR_IA32_SYSENTER_CS is
231 * that we set it to zero in vm86 tasks to avoid corrupting the
232 * stack if we were to go through the sysenter path from vm86
235 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
237 unsigned short __ss1h;
239 unsigned short ss2, __ss2h;
251 unsigned short es, __esh;
252 unsigned short cs, __csh;
253 unsigned short ss, __ssh;
254 unsigned short ds, __dsh;
255 unsigned short fs, __fsh;
256 unsigned short gs, __gsh;
257 unsigned short ldt, __ldth;
258 unsigned short trace;
259 unsigned short io_bitmap_base;
261 } __attribute__((packed));
275 } __attribute__((packed)) ____cacheline_aligned;
281 #define IO_BITMAP_BITS 65536
282 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
283 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
284 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
285 #define INVALID_IO_BITMAP_OFFSET 0x8000
289 * The hardware state:
291 struct x86_hw_tss x86_tss;
294 * The extra 1 is there because the CPU will access an
295 * additional byte beyond the end of the IO permission
296 * bitmap. The extra byte must be all 1 bits, and must
297 * be within the limit.
299 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
303 * Space for the temporary SYSENTER stack.
305 unsigned long SYSENTER_stack_canary;
306 unsigned long SYSENTER_stack[64];
309 } ____cacheline_aligned;
311 DECLARE_PER_CPU_SHARED_ALIGNED_USER_MAPPED(struct tss_struct, cpu_tss);
314 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
318 * Save the original ist values for checking stack pointers during debugging
321 unsigned long ist[7];
325 DECLARE_PER_CPU(struct orig_ist, orig_ist);
327 union irq_stack_union {
328 char irq_stack[IRQ_STACK_SIZE];
330 * GCC hardcodes the stack canary as %gs:40. Since the
331 * irq_stack is the object at %gs:0, we reserve the bottom
332 * 48 bytes of the irq stack for the canary.
336 unsigned long stack_canary;
340 char irq_stack_pointer[64];
341 char unused[IRQ_STACK_SIZE - 64];
345 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
346 DECLARE_INIT_PER_CPU(irq_stack_union);
348 DECLARE_PER_CPU(char *, irq_stack_ptr);
349 DECLARE_PER_CPU(unsigned int, irq_count);
350 extern asmlinkage void ignore_sysret(void);
352 #ifdef CONFIG_CC_STACKPROTECTOR
354 * Make sure stack canary segment base is cached-aligned:
355 * "For Intel Atom processors, avoid non zero segment base address
356 * that is not aligned to cache line boundary at all cost."
357 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
359 struct stack_canary {
360 char __pad[20]; /* canary at %gs:20 */
361 unsigned long canary;
363 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
366 * per-CPU IRQ handling stacks
369 u32 stack[THREAD_SIZE/sizeof(u32)];
370 } __aligned(THREAD_SIZE);
372 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
373 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
376 extern unsigned int fpu_kernel_xstate_size;
377 extern unsigned int fpu_user_xstate_size;
385 struct thread_struct {
386 /* Cached TLS descriptors: */
387 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
391 unsigned long sysenter_cs;
395 unsigned short fsindex;
396 unsigned short gsindex;
399 u32 status; /* thread synchronous flags */
402 unsigned long fsbase;
403 unsigned long gsbase;
406 * XXX: this could presumably be unsigned short. Alternatively,
407 * 32-bit kernels could be taught to use fsindex instead.
413 /* Save middle states of ptrace breakpoints */
414 struct perf_event *ptrace_bps[HBP_NUM];
415 /* Debug status used for traps, single steps, etc... */
416 unsigned long debugreg6;
417 /* Keep track of the exact dr7 value set by the user */
418 unsigned long ptrace_dr7;
421 unsigned long trap_nr;
422 unsigned long error_code;
424 /* Virtual 86 mode info */
427 /* IO permissions: */
428 unsigned long *io_bitmap_ptr;
430 /* Max allowed port in the bitmap, in bytes: */
431 unsigned io_bitmap_max;
433 mm_segment_t addr_limit;
435 unsigned int sig_on_uaccess_err:1;
436 unsigned int uaccess_err:1; /* uaccess failed */
438 /* Floating point and extended processor state */
441 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
447 * Thread-synchronous status.
449 * This is different from the flags in that nobody else
450 * ever touches our thread-synchronous status, so we don't
451 * have to worry about atomic accesses.
453 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
456 * Set IOPL bits in EFLAGS from given mask
458 static inline void native_set_iopl_mask(unsigned mask)
463 asm volatile ("pushfl;"
470 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
475 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
477 tss->x86_tss.sp0 = thread->sp0;
479 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
480 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
481 tss->x86_tss.ss1 = thread->sysenter_cs;
482 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
487 static inline void native_swapgs(void)
490 asm volatile("swapgs" ::: "memory");
494 static inline unsigned long current_top_of_stack(void)
497 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
499 /* sp0 on x86_32 is special in and around vm86 mode. */
500 return this_cpu_read_stable(cpu_current_top_of_stack);
504 #ifdef CONFIG_PARAVIRT
505 #include <asm/paravirt.h>
507 #define __cpuid native_cpuid
509 static inline void load_sp0(struct tss_struct *tss,
510 struct thread_struct *thread)
512 native_load_sp0(tss, thread);
515 #define set_iopl_mask native_set_iopl_mask
516 #endif /* CONFIG_PARAVIRT */
518 /* Free all resources held by a thread. */
519 extern void release_thread(struct task_struct *);
521 unsigned long get_wchan(struct task_struct *p);
524 * Generic CPUID function
525 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
526 * resulting in stale register contents being returned.
528 static inline void cpuid(unsigned int op,
529 unsigned int *eax, unsigned int *ebx,
530 unsigned int *ecx, unsigned int *edx)
534 __cpuid(eax, ebx, ecx, edx);
537 /* Some CPUID calls want 'count' to be placed in ecx */
538 static inline void cpuid_count(unsigned int op, int count,
539 unsigned int *eax, unsigned int *ebx,
540 unsigned int *ecx, unsigned int *edx)
544 __cpuid(eax, ebx, ecx, edx);
548 * CPUID functions returning a single datum
550 static inline unsigned int cpuid_eax(unsigned int op)
552 unsigned int eax, ebx, ecx, edx;
554 cpuid(op, &eax, &ebx, &ecx, &edx);
559 static inline unsigned int cpuid_ebx(unsigned int op)
561 unsigned int eax, ebx, ecx, edx;
563 cpuid(op, &eax, &ebx, &ecx, &edx);
568 static inline unsigned int cpuid_ecx(unsigned int op)
570 unsigned int eax, ebx, ecx, edx;
572 cpuid(op, &eax, &ebx, &ecx, &edx);
577 static inline unsigned int cpuid_edx(unsigned int op)
579 unsigned int eax, ebx, ecx, edx;
581 cpuid(op, &eax, &ebx, &ecx, &edx);
586 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
587 static __always_inline void rep_nop(void)
589 asm volatile("rep; nop" ::: "memory");
592 static __always_inline void cpu_relax(void)
597 #define cpu_relax_lowlatency() cpu_relax()
599 /* Stop speculative execution and prefetching of modified code. */
600 static inline void sync_core(void)
606 * Do a CPUID if available, otherwise do a jump. The jump
607 * can conveniently enough be the jump around CPUID.
609 asm volatile("cmpl %2,%1\n\t"
614 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
615 : "ebx", "ecx", "edx", "memory");
618 * CPUID is a barrier to speculative execution.
619 * Prefetched instructions are automatically
620 * invalidated when modified.
625 : "ebx", "ecx", "edx", "memory");
629 extern void select_idle_routine(const struct cpuinfo_x86 *c);
630 extern void init_amd_e400_c1e_mask(void);
632 extern unsigned long boot_option_idle_override;
633 extern bool amd_e400_c1e_detected;
635 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
638 extern void enable_sep_cpu(void);
639 extern int sysenter_setup(void);
641 extern void early_trap_init(void);
642 void early_trap_pf_init(void);
644 /* Defined in head.S */
645 extern struct desc_ptr early_gdt_descr;
647 extern void cpu_set_gdt(int);
648 extern void switch_to_new_gdt(int);
649 extern void load_percpu_segment(int);
650 extern void cpu_init(void);
652 static inline unsigned long get_debugctlmsr(void)
654 unsigned long debugctlmsr = 0;
656 #ifndef CONFIG_X86_DEBUGCTLMSR
657 if (boot_cpu_data.x86 < 6)
660 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
665 static inline void update_debugctlmsr(unsigned long debugctlmsr)
667 #ifndef CONFIG_X86_DEBUGCTLMSR
668 if (boot_cpu_data.x86 < 6)
671 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
674 extern void set_task_blockstep(struct task_struct *task, bool on);
676 /* Boot loader type from the setup header: */
677 extern int bootloader_type;
678 extern int bootloader_version;
680 extern char ignore_fpu_irq;
682 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
683 #define ARCH_HAS_PREFETCHW
684 #define ARCH_HAS_SPINLOCK_PREFETCH
687 # define BASE_PREFETCH ""
688 # define ARCH_HAS_PREFETCH
690 # define BASE_PREFETCH "prefetcht0 %P1"
694 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
696 * It's not worth to care about 3dnow prefetches for the K6
697 * because they are microcoded there and very slow.
699 static inline void prefetch(const void *x)
701 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
703 "m" (*(const char *)x));
707 * 3dnow prefetch to get an exclusive cache line.
708 * Useful for spinlocks to avoid one state transition in the
709 * cache coherency protocol:
711 static inline void prefetchw(const void *x)
713 alternative_input(BASE_PREFETCH, "prefetchw %P1",
714 X86_FEATURE_3DNOWPREFETCH,
715 "m" (*(const char *)x));
718 static inline void spin_lock_prefetch(const void *x)
723 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
724 TOP_OF_KERNEL_STACK_PADDING)
728 * User space process size: 3GB (default).
730 #define TASK_SIZE PAGE_OFFSET
731 #define TASK_SIZE_MAX TASK_SIZE
732 #define STACK_TOP TASK_SIZE
733 #define STACK_TOP_MAX STACK_TOP
735 #define INIT_THREAD { \
736 .sp0 = TOP_OF_INIT_STACK, \
737 .sysenter_cs = __KERNEL_CS, \
738 .io_bitmap_ptr = NULL, \
739 .addr_limit = KERNEL_DS, \
743 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
744 * This is necessary to guarantee that the entire "struct pt_regs"
745 * is accessible even if the CPU haven't stored the SS/ESP registers
746 * on the stack (interrupt gate does not save these registers
747 * when switching to the same priv ring).
748 * Therefore beware: accessing the ss/esp fields of the
749 * "struct pt_regs" is possible, but they may contain the
750 * completely wrong values.
752 #define task_pt_regs(task) \
754 unsigned long __ptr = (unsigned long)task_stack_page(task); \
755 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
756 ((struct pt_regs *)__ptr) - 1; \
759 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
763 * User space process size. 47bits minus one guard page. The guard
764 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
765 * the highest possible canonical userspace address, then that
766 * syscall will enter the kernel with a non-canonical return
767 * address, and SYSRET will explode dangerously. We avoid this
768 * particular problem by preventing anything from being mapped
769 * at the maximum canonical address.
771 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
773 /* This decides where the kernel will search for a free chunk of vm
774 * space during mmap's.
776 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
777 0xc0000000 : 0xFFFFe000)
779 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
780 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
781 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
782 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
784 #define STACK_TOP TASK_SIZE
785 #define STACK_TOP_MAX TASK_SIZE_MAX
787 #define INIT_THREAD { \
788 .sp0 = TOP_OF_INIT_STACK, \
789 .addr_limit = KERNEL_DS, \
792 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
793 extern unsigned long KSTK_ESP(struct task_struct *task);
795 #endif /* CONFIG_X86_64 */
797 extern unsigned long thread_saved_pc(struct task_struct *tsk);
799 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
800 unsigned long new_sp);
803 * This decides where the kernel will search for a free chunk of vm
804 * space during mmap's.
806 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
808 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
810 /* Get/set a process' ability to use the timestamp counter instruction */
811 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
812 #define SET_TSC_CTL(val) set_tsc_mode((val))
814 extern int get_tsc_mode(unsigned long adr);
815 extern int set_tsc_mode(unsigned int val);
817 /* Register/unregister a process' MPX related resource */
818 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
819 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
821 #ifdef CONFIG_X86_INTEL_MPX
822 extern int mpx_enable_management(void);
823 extern int mpx_disable_management(void);
825 static inline int mpx_enable_management(void)
829 static inline int mpx_disable_management(void)
833 #endif /* CONFIG_X86_INTEL_MPX */
835 extern u16 amd_get_nb_id(int cpu);
836 extern u32 amd_get_nodes_per_socket(void);
838 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
840 uint32_t base, eax, signature[3];
842 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
843 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
845 if (!memcmp(sig, signature, 12) &&
846 (leaves == 0 || ((eax - base) >= leaves)))
853 extern unsigned long arch_align_stack(unsigned long sp);
854 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
856 void default_idle(void);
858 bool xen_set_default_idle(void);
860 #define xen_set_default_idle 0
863 void stop_this_cpu(void *dummy);
864 void df_debug(struct pt_regs *regs, long error_code);
865 #endif /* _ASM_X86_PROCESSOR_H */