2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
58 unsigned int num_processors;
60 unsigned disabled_cpus;
62 /* Processor that is doing the boot up */
63 unsigned int boot_cpu_physical_apicid = -1U;
64 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
66 u8 boot_cpu_apic_version;
69 * The highest APIC ID seen during enumeration.
71 static unsigned int max_physical_apicid;
74 * Bitmask of physically existing CPUs:
76 physid_mask_t phys_cpu_present_map;
79 * Processor to be disabled specified by kernel parameter
80 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
81 * avoid undefined behaviour caused by sending INIT from AP to BSP.
83 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
86 * This variable controls which CPUs receive external NMIs. By default,
87 * external NMIs are delivered only to the BSP.
89 static int apic_extnmi = APIC_EXTNMI_BSP;
92 * Map cpu index to physical APIC ID
94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
97 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
104 * On x86_32, the mapping between cpu and logical apicid may vary
105 * depending on apic in use. The following early percpu variable is
106 * used for the mapping. This is where the behaviors of x86_64 and 32
107 * actually diverge. Let's keep it ugly for now.
109 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
111 /* Local APIC was disabled by the BIOS and enabled by the kernel */
112 static int enabled_via_apicbase;
115 * Handle interrupt mode configuration register (IMCR).
116 * This register controls whether the interrupt signals
117 * that reach the BSP come from the master PIC or from the
118 * local APIC. Before entering Symmetric I/O Mode, either
119 * the BIOS or the operating system must switch out of
120 * PIC Mode by changing the IMCR.
122 static inline void imcr_pic_to_apic(void)
124 /* select IMCR register */
126 /* NMI and 8259 INTR go through APIC */
130 static inline void imcr_apic_to_pic(void)
132 /* select IMCR register */
134 /* NMI and 8259 INTR go directly to BSP */
140 * Knob to control our willingness to enable the local APIC.
144 static int force_enable_local_apic __initdata;
147 * APIC command line parameters
149 static int __init parse_lapic(char *arg)
151 if (IS_ENABLED(CONFIG_X86_32) && !arg)
152 force_enable_local_apic = 1;
153 else if (arg && !strncmp(arg, "notscdeadline", 13))
154 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
157 early_param("lapic", parse_lapic);
160 static int apic_calibrate_pmtmr __initdata;
161 static __init int setup_apicpmtimer(char *s)
163 apic_calibrate_pmtmr = 1;
167 __setup("apicpmtimer", setup_apicpmtimer);
170 unsigned long mp_lapic_addr;
172 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
173 static int disable_apic_timer __initdata;
174 /* Local APIC timer works in C2 */
175 int local_apic_timer_c2_ok;
176 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
178 int first_system_vector = FIRST_SYSTEM_VECTOR;
181 * Debug level, exported for io_apic.c
183 unsigned int apic_verbosity;
187 /* Have we found an MP table */
188 int smp_found_config;
190 static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 unsigned int lapic_timer_frequency = 0;
197 static void apic_pm_activate(void);
199 static unsigned long apic_phys;
202 * Get the LAPIC version
204 static inline int lapic_get_version(void)
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
210 * Check, if the APIC is integrated or a separate chip
212 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
222 * Check, whether this is a modern or a first generation APIC
224 static int modern_apic(void)
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
228 boot_cpu_data.x86 >= 0xf)
230 return lapic_get_version() >= 0x14;
234 * right after this call apic become NOOP driven
235 * so apic->write/read doesn't do anything
237 static void __init apic_disable(void)
239 pr_info("APIC: switched to apic NOOP\n");
243 void native_apic_wait_icr_idle(void)
245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
249 u32 native_safe_apic_wait_icr_idle(void)
256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
259 inc_irq_stat(icr_read_retry_count);
261 } while (timeout++ < 1000);
266 void native_apic_icr_write(u32 low, u32 id)
270 local_irq_save(flags);
271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272 apic_write(APIC_ICR, low);
273 local_irq_restore(flags);
276 u64 native_apic_icr_read(void)
280 icr2 = apic_read(APIC_ICR2);
281 icr1 = apic_read(APIC_ICR);
283 return icr1 | ((u64)icr2 << 32);
288 * get_physical_broadcast - Get number of physical broadcast IDs
290 int get_physical_broadcast(void)
292 return modern_apic() ? 0xff : 0xf;
297 * lapic_get_maxlvt - get the maximum number of local vector table entries
299 int lapic_get_maxlvt(void)
303 v = apic_read(APIC_LVR);
305 * - we always have APIC integrated on 64bit mode
306 * - 82489DXs do not report # of LVT entries
308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR 8
320 * This function sets up the local APIC timer, with a timeout of
321 * 'clocks' APIC bus clock. During calibration we actually call
322 * this function twice on the boot CPU, once with a bogus timeout
323 * value, second time for real. The other (noncalibrating) CPUs
324 * call this function only once, with the real, calibrated value.
326 * We do reads before writes even if unnecessary, to get around the
327 * P5 APIC double write bug.
329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 unsigned int lvtt_value, tmp_value;
333 lvtt_value = LOCAL_TIMER_VECTOR;
335 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 if (!lapic_is_integrated())
340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343 lvtt_value |= APIC_LVT_MASKED;
345 apic_write(APIC_LVTT, lvtt_value);
347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351 * According to Intel, MFENCE can do the serialization here.
353 asm volatile("mfence" : : : "memory");
355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372 * Setup extended LVT, AMD specific
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 return (old & APIC_EILVT_MASKED)
396 || (new == APIC_EILVT_MASKED)
397 || ((new & ~APIC_EILVT_MASKED) == old);
400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 unsigned int rsvd, vector;
404 if (offset >= APIC_EILVT_NR_MAX)
407 rsvd = atomic_read(&eilvt_offsets[offset]);
409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
410 if (vector && !eilvt_entry_is_changeable(vector, new))
411 /* may not change if vectors are different */
413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
414 } while (rsvd != new);
416 rsvd &= ~APIC_EILVT_MASKED;
417 if (rsvd && rsvd != vector)
418 pr_info("LVT offset %d assigned for vector 0x%02x\n",
425 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 * enables the vector. See also the BKDGs. Must be called with
427 * preemption disabled.
430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 unsigned long reg = APIC_EILVTn(offset);
433 unsigned int new, old, reserved;
435 new = (mask << 16) | (msg_type << 8) | vector;
436 old = apic_read(reg);
437 reserved = reserve_eilvt_offset(offset, new);
439 if (reserved != new) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on another cpu\n",
443 smp_processor_id(), reg, offset, new, reserved);
447 if (!eilvt_entry_is_changeable(old, new)) {
448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449 "vector 0x%x, but the register is already in use for "
450 "vector 0x%x on this cpu\n",
451 smp_processor_id(), reg, offset, new, old);
455 apic_write(reg, new);
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
462 * Program the next event, relative to now
464 static int lapic_next_event(unsigned long delta,
465 struct clock_event_device *evt)
467 apic_write(APIC_TMICT, delta);
471 static int lapic_next_deadline(unsigned long delta,
472 struct clock_event_device *evt)
477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
481 static int lapic_timer_shutdown(struct clock_event_device *evt)
485 /* Lapic used as dummy for broadcast ? */
486 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
489 v = apic_read(APIC_LVTT);
490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
491 apic_write(APIC_LVTT, v);
492 apic_write(APIC_TMICT, 0);
497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499 /* Lapic used as dummy for broadcast ? */
500 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
507 static int lapic_timer_set_periodic(struct clock_event_device *evt)
509 return lapic_timer_set_periodic_oneshot(evt, false);
512 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514 return lapic_timer_set_periodic_oneshot(evt, true);
518 * Local APIC timer broadcast function
520 static void lapic_timer_broadcast(const struct cpumask *mask)
523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
529 * The local apic timer can be used for any function which is CPU local.
531 static struct clock_event_device lapic_clockevent = {
533 .features = CLOCK_EVT_FEAT_PERIODIC |
534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
535 | CLOCK_EVT_FEAT_DUMMY,
537 .set_state_shutdown = lapic_timer_shutdown,
538 .set_state_periodic = lapic_timer_set_periodic,
539 .set_state_oneshot = lapic_timer_set_oneshot,
540 .set_state_oneshot_stopped = lapic_timer_shutdown,
541 .set_next_event = lapic_next_event,
542 .broadcast = lapic_timer_broadcast,
546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
549 * Setup the local APIC timer for this CPU. Copy the initialized values
550 * of the boot CPU and register the clock event in the framework.
552 static void setup_APIC_timer(void)
554 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
556 if (this_cpu_has(X86_FEATURE_ARAT)) {
557 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
558 /* Make LAPIC timer preferrable over percpu HPET */
559 lapic_clockevent.rating = 150;
562 memcpy(levt, &lapic_clockevent, sizeof(*levt));
563 levt->cpumask = cpumask_of(smp_processor_id());
565 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
566 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
567 CLOCK_EVT_FEAT_DUMMY);
568 levt->set_next_event = lapic_next_deadline;
569 clockevents_config_and_register(levt,
570 tsc_khz * (1000 / TSC_DIVISOR),
573 clockevents_register_device(levt);
577 * Install the updated TSC frequency from recalibration at the TSC
578 * deadline clockevent devices.
580 static void __lapic_update_tsc_freq(void *info)
582 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
584 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
587 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
590 void lapic_update_tsc_freq(void)
593 * The clockevent device's ->mult and ->shift can both be
594 * changed. In order to avoid races, schedule the frequency
595 * update code on each CPU.
597 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
601 * In this functions we calibrate APIC bus clocks to the external timer.
603 * We want to do the calibration only once since we want to have local timer
604 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
607 * This was previously done by reading the PIT/HPET and waiting for a wrap
608 * around to find out, that a tick has elapsed. I have a box, where the PIT
609 * readout is broken, so it never gets out of the wait loop again. This was
610 * also reported by others.
612 * Monitoring the jiffies value is inaccurate and the clockevents
613 * infrastructure allows us to do a simple substitution of the interrupt
616 * The calibration routine also uses the pm_timer when possible, as the PIT
617 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
618 * back to normal later in the boot process).
621 #define LAPIC_CAL_LOOPS (HZ/10)
623 static __initdata int lapic_cal_loops = -1;
624 static __initdata long lapic_cal_t1, lapic_cal_t2;
625 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
626 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
627 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
630 * Temporary interrupt handler.
632 static void __init lapic_cal_handler(struct clock_event_device *dev)
634 unsigned long long tsc = 0;
635 long tapic = apic_read(APIC_TMCCT);
636 unsigned long pm = acpi_pm_read_early();
638 if (boot_cpu_has(X86_FEATURE_TSC))
641 switch (lapic_cal_loops++) {
643 lapic_cal_t1 = tapic;
644 lapic_cal_tsc1 = tsc;
646 lapic_cal_j1 = jiffies;
649 case LAPIC_CAL_LOOPS:
650 lapic_cal_t2 = tapic;
651 lapic_cal_tsc2 = tsc;
652 if (pm < lapic_cal_pm1)
653 pm += ACPI_PM_OVRRUN;
655 lapic_cal_j2 = jiffies;
661 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
663 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
664 const long pm_thresh = pm_100ms / 100;
668 #ifndef CONFIG_X86_PM_TIMER
672 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
674 /* Check, if the PM timer is available */
678 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
680 if (deltapm > (pm_100ms - pm_thresh) &&
681 deltapm < (pm_100ms + pm_thresh)) {
682 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
686 res = (((u64)deltapm) * mult) >> 22;
687 do_div(res, 1000000);
688 pr_warning("APIC calibration not consistent "
689 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
691 /* Correct the lapic counter value */
692 res = (((u64)(*delta)) * pm_100ms);
693 do_div(res, deltapm);
694 pr_info("APIC delta adjusted to PM-Timer: "
695 "%lu (%ld)\n", (unsigned long)res, *delta);
698 /* Correct the tsc counter value */
699 if (boot_cpu_has(X86_FEATURE_TSC)) {
700 res = (((u64)(*deltatsc)) * pm_100ms);
701 do_div(res, deltapm);
702 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
703 "PM-Timer: %lu (%ld)\n",
704 (unsigned long)res, *deltatsc);
705 *deltatsc = (long)res;
711 static int __init calibrate_APIC_clock(void)
713 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
714 void (*real_handler)(struct clock_event_device *dev);
715 unsigned long deltaj;
716 long delta, deltatsc;
717 int pm_referenced = 0;
720 * check if lapic timer has already been calibrated by platform
721 * specific routine, such as tsc calibration code. if so, we just fill
722 * in the clockevent structure and return.
725 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
727 } else if (lapic_timer_frequency) {
728 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
729 lapic_timer_frequency);
730 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
731 TICK_NSEC, lapic_clockevent.shift);
732 lapic_clockevent.max_delta_ns =
733 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
734 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
735 lapic_clockevent.min_delta_ns =
736 clockevent_delta2ns(0xF, &lapic_clockevent);
737 lapic_clockevent.min_delta_ticks = 0xF;
738 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
742 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
743 "calibrating APIC timer ...\n");
747 /* Replace the global interrupt handler */
748 real_handler = global_clock_event->event_handler;
749 global_clock_event->event_handler = lapic_cal_handler;
752 * Setup the APIC counter to maximum. There is no way the lapic
753 * can underflow in the 100ms detection time frame
755 __setup_APIC_LVTT(0xffffffff, 0, 0);
757 /* Let the interrupts run */
760 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
765 /* Restore the real event handler */
766 global_clock_event->event_handler = real_handler;
768 /* Build delta t1-t2 as apic timer counts down */
769 delta = lapic_cal_t1 - lapic_cal_t2;
770 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
772 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
774 /* we trust the PM based calibration if possible */
775 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
778 /* Calculate the scaled math multiplication factor */
779 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
780 lapic_clockevent.shift);
781 lapic_clockevent.max_delta_ns =
782 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
783 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
784 lapic_clockevent.min_delta_ns =
785 clockevent_delta2ns(0xF, &lapic_clockevent);
786 lapic_clockevent.min_delta_ticks = 0xF;
788 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
790 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
791 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
792 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
793 lapic_timer_frequency);
795 if (boot_cpu_has(X86_FEATURE_TSC)) {
796 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
798 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
799 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
802 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
804 lapic_timer_frequency / (1000000 / HZ),
805 lapic_timer_frequency % (1000000 / HZ));
808 * Do a sanity check on the APIC calibration result
810 if (lapic_timer_frequency < (1000000 / HZ)) {
812 pr_warning("APIC frequency too slow, disabling apic timer\n");
816 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
819 * PM timer calibration failed or not turned on
820 * so lets try APIC timer based calibration
822 if (!pm_referenced) {
823 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
826 * Setup the apic timer manually
828 levt->event_handler = lapic_cal_handler;
829 lapic_timer_set_periodic(levt);
830 lapic_cal_loops = -1;
832 /* Let the interrupts run */
835 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
838 /* Stop the lapic timer */
840 lapic_timer_shutdown(levt);
843 deltaj = lapic_cal_j2 - lapic_cal_j1;
844 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
846 /* Check, if the jiffies result is consistent */
847 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
848 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
850 levt->features |= CLOCK_EVT_FEAT_DUMMY;
854 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
855 pr_warning("APIC timer disabled due to verification failure\n");
863 * Setup the boot APIC
865 * Calibrate and verify the result.
867 void __init setup_boot_APIC_clock(void)
870 * The local apic timer can be disabled via the kernel
871 * commandline or from the CPU detection code. Register the lapic
872 * timer as a dummy clock event source on SMP systems, so the
873 * broadcast mechanism is used. On UP systems simply ignore it.
875 if (disable_apic_timer) {
876 pr_info("Disabling APIC timer\n");
877 /* No broadcast on UP ! */
878 if (num_possible_cpus() > 1) {
879 lapic_clockevent.mult = 1;
885 if (calibrate_APIC_clock()) {
886 /* No broadcast on UP ! */
887 if (num_possible_cpus() > 1)
893 * If nmi_watchdog is set to IO_APIC, we need the
894 * PIT/HPET going. Otherwise register lapic as a dummy
897 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
899 /* Setup the lapic or request the broadcast */
901 amd_e400_c1e_apic_setup();
904 void setup_secondary_APIC_clock(void)
907 amd_e400_c1e_apic_setup();
911 * The guts of the apic timer interrupt
913 static void local_apic_timer_interrupt(void)
915 int cpu = smp_processor_id();
916 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
919 * Normally we should not be here till LAPIC has been initialized but
920 * in some cases like kdump, its possible that there is a pending LAPIC
921 * timer interrupt from previous kernel's context and is delivered in
922 * new kernel the moment interrupts are enabled.
924 * Interrupts are enabled early and LAPIC is setup much later, hence
925 * its possible that when we get here evt->event_handler is NULL.
926 * Check for event_handler being NULL and discard the interrupt as
929 if (!evt->event_handler) {
930 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
932 lapic_timer_shutdown(evt);
937 * the NMI deadlock-detector uses this.
939 inc_irq_stat(apic_timer_irqs);
941 evt->event_handler(evt);
945 * Local APIC timer interrupt. This is the most natural way for doing
946 * local interrupts, but local timer interrupts can be emulated by
947 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
949 * [ if a single-CPU system runs an SMP kernel then we call the local
950 * interrupt as well. Thus we cannot inline the local irq ... ]
952 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
954 struct pt_regs *old_regs = set_irq_regs(regs);
957 * NOTE! We'd better ACK the irq immediately,
958 * because timer handling can be slow.
960 * update_process_times() expects us to have done irq_enter().
961 * Besides, if we don't timer interrupts ignore the global
962 * interrupt lock, which is the WrongThing (tm) to do.
965 local_apic_timer_interrupt();
968 set_irq_regs(old_regs);
971 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
973 struct pt_regs *old_regs = set_irq_regs(regs);
976 * NOTE! We'd better ACK the irq immediately,
977 * because timer handling can be slow.
979 * update_process_times() expects us to have done irq_enter().
980 * Besides, if we don't timer interrupts ignore the global
981 * interrupt lock, which is the WrongThing (tm) to do.
984 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
985 local_apic_timer_interrupt();
986 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
989 set_irq_regs(old_regs);
992 int setup_profiling_timer(unsigned int multiplier)
998 * Local APIC start and shutdown
1002 * clear_local_APIC - shutdown the local APIC
1004 * This is called, when a CPU is disabled and before rebooting, so the state of
1005 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1006 * leftovers during boot.
1008 void clear_local_APIC(void)
1013 /* APIC hasn't been mapped yet */
1014 if (!x2apic_mode && !apic_phys)
1017 maxlvt = lapic_get_maxlvt();
1019 * Masking an LVT entry can trigger a local APIC error
1020 * if the vector is zero. Mask LVTERR first to prevent this.
1023 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1024 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1027 * Careful: we have to set masks only first to deassert
1028 * any level-triggered sources.
1030 v = apic_read(APIC_LVTT);
1031 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1032 v = apic_read(APIC_LVT0);
1033 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1034 v = apic_read(APIC_LVT1);
1035 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1037 v = apic_read(APIC_LVTPC);
1038 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1041 /* lets not touch this if we didn't frob it */
1042 #ifdef CONFIG_X86_THERMAL_VECTOR
1044 v = apic_read(APIC_LVTTHMR);
1045 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1048 #ifdef CONFIG_X86_MCE_INTEL
1050 v = apic_read(APIC_LVTCMCI);
1051 if (!(v & APIC_LVT_MASKED))
1052 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1057 * Clean APIC state for other OSs:
1059 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1060 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1061 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1063 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1065 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1067 /* Integrated APIC (!82489DX) ? */
1068 if (lapic_is_integrated()) {
1070 /* Clear ESR due to Pentium errata 3AP and 11AP */
1071 apic_write(APIC_ESR, 0);
1072 apic_read(APIC_ESR);
1077 * disable_local_APIC - clear and disable the local APIC
1079 void disable_local_APIC(void)
1083 /* APIC hasn't been mapped yet */
1084 if (!x2apic_mode && !apic_phys)
1090 * Disable APIC (implies clearing of registers
1093 value = apic_read(APIC_SPIV);
1094 value &= ~APIC_SPIV_APIC_ENABLED;
1095 apic_write(APIC_SPIV, value);
1097 #ifdef CONFIG_X86_32
1099 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1100 * restore the disabled state.
1102 if (enabled_via_apicbase) {
1105 rdmsr(MSR_IA32_APICBASE, l, h);
1106 l &= ~MSR_IA32_APICBASE_ENABLE;
1107 wrmsr(MSR_IA32_APICBASE, l, h);
1113 * If Linux enabled the LAPIC against the BIOS default disable it down before
1114 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1115 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1116 * for the case where Linux didn't enable the LAPIC.
1118 void lapic_shutdown(void)
1120 unsigned long flags;
1122 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1125 local_irq_save(flags);
1127 #ifdef CONFIG_X86_32
1128 if (!enabled_via_apicbase)
1132 disable_local_APIC();
1135 local_irq_restore(flags);
1139 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1141 void __init sync_Arb_IDs(void)
1144 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1147 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1153 apic_wait_icr_idle();
1155 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1156 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1157 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1161 * An initial setup of the virtual wire mode.
1163 void __init init_bsp_APIC(void)
1168 * Don't do the setup now if we have a SMP BIOS as the
1169 * through-I/O-APIC virtual wire mode might be active.
1171 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1175 * Do not trust the local APIC being empty at bootup.
1182 value = apic_read(APIC_SPIV);
1183 value &= ~APIC_VECTOR_MASK;
1184 value |= APIC_SPIV_APIC_ENABLED;
1186 #ifdef CONFIG_X86_32
1187 /* This bit is reserved on P4/Xeon and should be cleared */
1188 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1189 (boot_cpu_data.x86 == 15))
1190 value &= ~APIC_SPIV_FOCUS_DISABLED;
1193 value |= APIC_SPIV_FOCUS_DISABLED;
1194 value |= SPURIOUS_APIC_VECTOR;
1195 apic_write(APIC_SPIV, value);
1198 * Set up the virtual wire mode.
1200 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1201 value = APIC_DM_NMI;
1202 if (!lapic_is_integrated()) /* 82489DX */
1203 value |= APIC_LVT_LEVEL_TRIGGER;
1204 if (apic_extnmi == APIC_EXTNMI_NONE)
1205 value |= APIC_LVT_MASKED;
1206 apic_write(APIC_LVT1, value);
1209 static void lapic_setup_esr(void)
1211 unsigned int oldvalue, value, maxlvt;
1213 if (!lapic_is_integrated()) {
1214 pr_info("No ESR for 82489DX.\n");
1218 if (apic->disable_esr) {
1220 * Something untraceable is creating bad interrupts on
1221 * secondary quads ... for the moment, just leave the
1222 * ESR disabled - we can't do anything useful with the
1223 * errors anyway - mbligh
1225 pr_info("Leaving ESR disabled.\n");
1229 maxlvt = lapic_get_maxlvt();
1230 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1231 apic_write(APIC_ESR, 0);
1232 oldvalue = apic_read(APIC_ESR);
1234 /* enables sending errors */
1235 value = ERROR_APIC_VECTOR;
1236 apic_write(APIC_LVTERR, value);
1239 * spec says clear errors after enabling vector.
1242 apic_write(APIC_ESR, 0);
1243 value = apic_read(APIC_ESR);
1244 if (value != oldvalue)
1245 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1246 "vector: 0x%08x after: 0x%08x\n",
1251 * setup_local_APIC - setup the local APIC
1253 * Used to setup local APIC while initializing BSP or bringing up APs.
1254 * Always called with preemption disabled.
1256 void setup_local_APIC(void)
1258 int cpu = smp_processor_id();
1259 unsigned int value, queued;
1260 int i, j, acked = 0;
1261 unsigned long long tsc = 0, ntsc;
1262 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1264 if (boot_cpu_has(X86_FEATURE_TSC))
1268 disable_ioapic_support();
1272 #ifdef CONFIG_X86_32
1273 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1274 if (lapic_is_integrated() && apic->disable_esr) {
1275 apic_write(APIC_ESR, 0);
1276 apic_write(APIC_ESR, 0);
1277 apic_write(APIC_ESR, 0);
1278 apic_write(APIC_ESR, 0);
1281 perf_events_lapic_init();
1284 * Double-check whether this APIC is really registered.
1285 * This is meaningless in clustered apic mode, so we skip it.
1287 BUG_ON(!apic->apic_id_registered());
1290 * Intel recommends to set DFR, LDR and TPR before enabling
1291 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1292 * document number 292116). So here it goes...
1294 apic->init_apic_ldr();
1296 #ifdef CONFIG_X86_32
1298 * APIC LDR is initialized. If logical_apicid mapping was
1299 * initialized during get_smp_config(), make sure it matches the
1302 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1303 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1304 /* always use the value from LDR */
1305 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1306 logical_smp_processor_id();
1310 * Set Task Priority to 'accept all'. We never change this
1313 value = apic_read(APIC_TASKPRI);
1314 value &= ~APIC_TPRI_MASK;
1315 apic_write(APIC_TASKPRI, value);
1318 * After a crash, we no longer service the interrupts and a pending
1319 * interrupt from previous kernel might still have ISR bit set.
1321 * Most probably by now CPU has serviced that pending interrupt and
1322 * it might not have done the ack_APIC_irq() because it thought,
1323 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1324 * does not clear the ISR bit and cpu thinks it has already serivced
1325 * the interrupt. Hence a vector might get locked. It was noticed
1326 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1330 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1331 queued |= apic_read(APIC_IRR + i*0x10);
1333 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1334 value = apic_read(APIC_ISR + i*0x10);
1335 for (j = 31; j >= 0; j--) {
1336 if (value & (1<<j)) {
1343 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1348 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1350 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1354 } while (queued && max_loops > 0);
1355 WARN_ON(max_loops <= 0);
1358 * Now that we are all set up, enable the APIC
1360 value = apic_read(APIC_SPIV);
1361 value &= ~APIC_VECTOR_MASK;
1365 value |= APIC_SPIV_APIC_ENABLED;
1367 #ifdef CONFIG_X86_32
1369 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1370 * certain networking cards. If high frequency interrupts are
1371 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1372 * entry is masked/unmasked at a high rate as well then sooner or
1373 * later IOAPIC line gets 'stuck', no more interrupts are received
1374 * from the device. If focus CPU is disabled then the hang goes
1377 * [ This bug can be reproduced easily with a level-triggered
1378 * PCI Ne2000 networking cards and PII/PIII processors, dual
1382 * Actually disabling the focus CPU check just makes the hang less
1383 * frequent as it makes the interrupt distributon model be more
1384 * like LRU than MRU (the short-term load is more even across CPUs).
1388 * - enable focus processor (bit==0)
1389 * - 64bit mode always use processor focus
1390 * so no need to set it
1392 value &= ~APIC_SPIV_FOCUS_DISABLED;
1396 * Set spurious IRQ vector
1398 value |= SPURIOUS_APIC_VECTOR;
1399 apic_write(APIC_SPIV, value);
1402 * Set up LVT0, LVT1:
1404 * set up through-local-APIC on the BP's LINT0. This is not
1405 * strictly necessary in pure symmetric-IO mode, but sometimes
1406 * we delegate interrupts to the 8259A.
1409 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1411 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1412 if (!cpu && (pic_mode || !value)) {
1413 value = APIC_DM_EXTINT;
1414 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1416 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1417 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1419 apic_write(APIC_LVT0, value);
1422 * Only the BSP sees the LINT1 NMI signal by default. This can be
1423 * modified by apic_extnmi= boot option.
1425 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1426 apic_extnmi == APIC_EXTNMI_ALL)
1427 value = APIC_DM_NMI;
1429 value = APIC_DM_NMI | APIC_LVT_MASKED;
1430 if (!lapic_is_integrated()) /* 82489DX */
1431 value |= APIC_LVT_LEVEL_TRIGGER;
1432 apic_write(APIC_LVT1, value);
1434 #ifdef CONFIG_X86_MCE_INTEL
1435 /* Recheck CMCI information after local APIC is up on CPU #0 */
1441 static void end_local_APIC_setup(void)
1445 #ifdef CONFIG_X86_32
1448 /* Disable the local apic timer */
1449 value = apic_read(APIC_LVTT);
1450 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1451 apic_write(APIC_LVTT, value);
1459 * APIC setup function for application processors. Called from smpboot.c
1461 void apic_ap_setup(void)
1464 end_local_APIC_setup();
1467 #ifdef CONFIG_X86_X2APIC
1475 static int x2apic_state;
1477 static void __x2apic_disable(void)
1481 if (!boot_cpu_has(X86_FEATURE_APIC))
1484 rdmsrl(MSR_IA32_APICBASE, msr);
1485 if (!(msr & X2APIC_ENABLE))
1487 /* Disable xapic and x2apic first and then reenable xapic mode */
1488 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1489 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1490 printk_once(KERN_INFO "x2apic disabled\n");
1493 static void __x2apic_enable(void)
1497 rdmsrl(MSR_IA32_APICBASE, msr);
1498 if (msr & X2APIC_ENABLE)
1500 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1501 printk_once(KERN_INFO "x2apic enabled\n");
1504 static int __init setup_nox2apic(char *str)
1506 if (x2apic_enabled()) {
1507 int apicid = native_apic_msr_read(APIC_ID);
1509 if (apicid >= 255) {
1510 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1514 pr_warning("x2apic already enabled.\n");
1517 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1518 x2apic_state = X2APIC_DISABLED;
1522 early_param("nox2apic", setup_nox2apic);
1524 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1525 void x2apic_setup(void)
1528 * If x2apic is not in ON state, disable it if already enabled
1531 if (x2apic_state != X2APIC_ON) {
1538 static __init void x2apic_disable(void)
1540 u32 x2apic_id, state = x2apic_state;
1543 x2apic_state = X2APIC_DISABLED;
1545 if (state != X2APIC_ON)
1548 x2apic_id = read_apic_id();
1549 if (x2apic_id >= 255)
1550 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1553 register_lapic_address(mp_lapic_addr);
1556 static __init void x2apic_enable(void)
1558 if (x2apic_state != X2APIC_OFF)
1562 x2apic_state = X2APIC_ON;
1566 static __init void try_to_enable_x2apic(int remap_mode)
1568 if (x2apic_state == X2APIC_DISABLED)
1571 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1572 /* IR is required if there is APIC ID > 255 even when running
1575 if (max_physical_apicid > 255 ||
1576 !hypervisor_x2apic_available()) {
1577 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1583 * without IR all CPUs can be addressed by IOAPIC/MSI
1584 * only in physical mode
1591 void __init check_x2apic(void)
1593 if (x2apic_enabled()) {
1594 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1596 x2apic_state = X2APIC_ON;
1597 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1598 x2apic_state = X2APIC_DISABLED;
1601 #else /* CONFIG_X86_X2APIC */
1602 static int __init validate_x2apic(void)
1604 if (!apic_is_x2apic_enabled())
1607 * Checkme: Can we simply turn off x2apic here instead of panic?
1609 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1611 early_initcall(validate_x2apic);
1613 static inline void try_to_enable_x2apic(int remap_mode) { }
1614 static inline void __x2apic_enable(void) { }
1615 #endif /* !CONFIG_X86_X2APIC */
1617 void __init enable_IR_x2apic(void)
1619 unsigned long flags;
1622 if (skip_ioapic_setup) {
1623 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1627 ir_stat = irq_remapping_prepare();
1628 if (ir_stat < 0 && !x2apic_supported())
1631 ret = save_ioapic_entries();
1633 pr_info("Saving IO-APIC state failed: %d\n", ret);
1637 local_irq_save(flags);
1638 legacy_pic->mask_all();
1639 mask_ioapic_entries();
1641 /* If irq_remapping_prepare() succeeded, try to enable it */
1643 ir_stat = irq_remapping_enable();
1644 /* ir_stat contains the remap mode or an error code */
1645 try_to_enable_x2apic(ir_stat);
1648 restore_ioapic_entries();
1649 legacy_pic->restore_mask();
1650 local_irq_restore(flags);
1653 #ifdef CONFIG_X86_64
1655 * Detect and enable local APICs on non-SMP boards.
1656 * Original code written by Keir Fraser.
1657 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1658 * not correctly set up (usually the APIC timer won't work etc.)
1660 static int __init detect_init_APIC(void)
1662 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1663 pr_info("No local APIC present\n");
1667 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1672 static int __init apic_verify(void)
1677 * The APIC feature bit should now be enabled
1680 features = cpuid_edx(1);
1681 if (!(features & (1 << X86_FEATURE_APIC))) {
1682 pr_warning("Could not enable APIC!\n");
1685 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1686 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1688 /* The BIOS may have set up the APIC at some other address */
1689 if (boot_cpu_data.x86 >= 6) {
1690 rdmsr(MSR_IA32_APICBASE, l, h);
1691 if (l & MSR_IA32_APICBASE_ENABLE)
1692 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1695 pr_info("Found and enabled local APIC!\n");
1699 int __init apic_force_enable(unsigned long addr)
1707 * Some BIOSes disable the local APIC in the APIC_BASE
1708 * MSR. This can only be done in software for Intel P6 or later
1709 * and AMD K7 (Model > 1) or later.
1711 if (boot_cpu_data.x86 >= 6) {
1712 rdmsr(MSR_IA32_APICBASE, l, h);
1713 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1714 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1715 l &= ~MSR_IA32_APICBASE_BASE;
1716 l |= MSR_IA32_APICBASE_ENABLE | addr;
1717 wrmsr(MSR_IA32_APICBASE, l, h);
1718 enabled_via_apicbase = 1;
1721 return apic_verify();
1725 * Detect and initialize APIC
1727 static int __init detect_init_APIC(void)
1729 /* Disabled by kernel option? */
1733 switch (boot_cpu_data.x86_vendor) {
1734 case X86_VENDOR_AMD:
1735 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1736 (boot_cpu_data.x86 >= 15))
1739 case X86_VENDOR_INTEL:
1740 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1741 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1748 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1750 * Over-ride BIOS and try to enable the local APIC only if
1751 * "lapic" specified.
1753 if (!force_enable_local_apic) {
1754 pr_info("Local APIC disabled by BIOS -- "
1755 "you can enable it with \"lapic\"\n");
1758 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1770 pr_info("No local APIC present or hardware disabled\n");
1776 * init_apic_mappings - initialize APIC mappings
1778 void __init init_apic_mappings(void)
1780 unsigned int new_apicid;
1783 boot_cpu_physical_apicid = read_apic_id();
1787 /* If no local APIC can be found return early */
1788 if (!smp_found_config && detect_init_APIC()) {
1789 /* lets NOP'ify apic operations */
1790 pr_info("APIC: disable apic facility\n");
1793 apic_phys = mp_lapic_addr;
1796 * acpi lapic path already maps that address in
1797 * acpi_register_lapic_address()
1799 if (!acpi_lapic && !smp_found_config)
1800 register_lapic_address(apic_phys);
1804 * Fetch the APIC ID of the BSP in case we have a
1805 * default configuration (or the MP table is broken).
1807 new_apicid = read_apic_id();
1808 if (boot_cpu_physical_apicid != new_apicid) {
1809 boot_cpu_physical_apicid = new_apicid;
1811 * yeah -- we lie about apic_version
1812 * in case if apic was disabled via boot option
1813 * but it's not a problem for SMP compiled kernel
1814 * since smp_sanity_check is prepared for such a case
1815 * and disable smp mode
1817 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1821 void __init register_lapic_address(unsigned long address)
1823 mp_lapic_addr = address;
1826 set_fixmap_nocache(FIX_APIC_BASE, address);
1827 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1828 APIC_BASE, address);
1830 if (boot_cpu_physical_apicid == -1U) {
1831 boot_cpu_physical_apicid = read_apic_id();
1832 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1837 * Local APIC interrupts
1841 * This interrupt should _never_ happen with our APIC/SMP architecture
1843 static void __smp_spurious_interrupt(u8 vector)
1848 * Check if this really is a spurious interrupt and ACK it
1849 * if it is a vectored one. Just in case...
1850 * Spurious interrupts should not be ACKed.
1852 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1853 if (v & (1 << (vector & 0x1f)))
1856 inc_irq_stat(irq_spurious_count);
1858 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1859 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1860 "should never happen.\n", vector, smp_processor_id());
1863 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1866 __smp_spurious_interrupt(~regs->orig_ax);
1870 __visible void __irq_entry smp_trace_spurious_interrupt(struct pt_regs *regs)
1872 u8 vector = ~regs->orig_ax;
1875 trace_spurious_apic_entry(vector);
1876 __smp_spurious_interrupt(vector);
1877 trace_spurious_apic_exit(vector);
1882 * This interrupt should never happen with our APIC/SMP architecture
1884 static void __smp_error_interrupt(struct pt_regs *regs)
1888 static const char * const error_interrupt_reason[] = {
1889 "Send CS error", /* APIC Error Bit 0 */
1890 "Receive CS error", /* APIC Error Bit 1 */
1891 "Send accept error", /* APIC Error Bit 2 */
1892 "Receive accept error", /* APIC Error Bit 3 */
1893 "Redirectable IPI", /* APIC Error Bit 4 */
1894 "Send illegal vector", /* APIC Error Bit 5 */
1895 "Received illegal vector", /* APIC Error Bit 6 */
1896 "Illegal register address", /* APIC Error Bit 7 */
1899 /* First tickle the hardware, only then report what went on. -- REW */
1900 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1901 apic_write(APIC_ESR, 0);
1902 v = apic_read(APIC_ESR);
1904 atomic_inc(&irq_err_count);
1906 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1907 smp_processor_id(), v);
1912 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1917 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1921 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
1924 __smp_error_interrupt(regs);
1928 __visible void __irq_entry smp_trace_error_interrupt(struct pt_regs *regs)
1931 trace_error_apic_entry(ERROR_APIC_VECTOR);
1932 __smp_error_interrupt(regs);
1933 trace_error_apic_exit(ERROR_APIC_VECTOR);
1938 * connect_bsp_APIC - attach the APIC to the interrupt system
1940 static void __init connect_bsp_APIC(void)
1942 #ifdef CONFIG_X86_32
1945 * Do not trust the local APIC being empty at bootup.
1949 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1950 * local APIC to INT and NMI lines.
1952 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1953 "enabling APIC mode.\n");
1960 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1961 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1963 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1966 void disconnect_bsp_APIC(int virt_wire_setup)
1970 #ifdef CONFIG_X86_32
1973 * Put the board back into PIC mode (has an effect only on
1974 * certain older boards). Note that APIC interrupts, including
1975 * IPIs, won't work beyond this point! The only exception are
1978 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1979 "entering PIC mode.\n");
1985 /* Go back to Virtual Wire compatibility mode */
1987 /* For the spurious interrupt use vector F, and enable it */
1988 value = apic_read(APIC_SPIV);
1989 value &= ~APIC_VECTOR_MASK;
1990 value |= APIC_SPIV_APIC_ENABLED;
1992 apic_write(APIC_SPIV, value);
1994 if (!virt_wire_setup) {
1996 * For LVT0 make it edge triggered, active high,
1997 * external and enabled
1999 value = apic_read(APIC_LVT0);
2000 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2001 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2002 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2003 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2004 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2005 apic_write(APIC_LVT0, value);
2008 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2012 * For LVT1 make it edge triggered, active high,
2015 value = apic_read(APIC_LVT1);
2016 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2017 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2018 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2019 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2020 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2021 apic_write(APIC_LVT1, value);
2025 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2026 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2027 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2028 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2030 * NOTE: Reserve 0 for BSP.
2032 static int nr_logical_cpuids = 1;
2035 * Used to store mapping between logical CPU IDs and APIC IDs.
2037 static int cpuid_to_apicid[] = {
2038 [0 ... NR_CPUS - 1] = -1,
2042 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2043 * and cpuid_to_apicid[] synchronized.
2045 static int allocate_logical_cpuid(int apicid)
2050 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2051 * check if the kernel has allocated a cpuid for it.
2053 for (i = 0; i < nr_logical_cpuids; i++) {
2054 if (cpuid_to_apicid[i] == apicid)
2058 /* Allocate a new cpuid. */
2059 if (nr_logical_cpuids >= nr_cpu_ids) {
2060 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %i reached. "
2061 "Processor %d/0x%x and the rest are ignored.\n",
2062 nr_cpu_ids, nr_logical_cpuids, apicid);
2066 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2067 return nr_logical_cpuids++;
2070 int generic_processor_info(int apicid, int version)
2072 int cpu, max = nr_cpu_ids;
2073 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2074 phys_cpu_present_map);
2077 * boot_cpu_physical_apicid is designed to have the apicid
2078 * returned by read_apic_id(), i.e, the apicid of the
2079 * currently booting-up processor. However, on some platforms,
2080 * it is temporarily modified by the apicid reported as BSP
2081 * through MP table. Concretely:
2083 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2084 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2086 * This function is executed with the modified
2087 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2088 * parameter doesn't work to disable APs on kdump 2nd kernel.
2090 * Since fixing handling of boot_cpu_physical_apicid requires
2091 * another discussion and tests on each platform, we leave it
2092 * for now and here we use read_apic_id() directly in this
2093 * function, __generic_processor_info().
2095 if (disabled_cpu_apicid != BAD_APICID &&
2096 disabled_cpu_apicid != read_apic_id() &&
2097 disabled_cpu_apicid == apicid) {
2098 int thiscpu = num_processors + disabled_cpus;
2100 pr_warning("APIC: Disabling requested cpu."
2101 " Processor %d/0x%x ignored.\n",
2109 * If boot cpu has not been detected yet, then only allow upto
2110 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2112 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2113 apicid != boot_cpu_physical_apicid) {
2114 int thiscpu = max + disabled_cpus - 1;
2117 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2118 " reached. Keeping one slot for boot cpu."
2119 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2125 if (num_processors >= nr_cpu_ids) {
2126 int thiscpu = max + disabled_cpus;
2128 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2129 "reached. Processor %d/0x%x ignored.\n",
2130 max, thiscpu, apicid);
2136 if (apicid == boot_cpu_physical_apicid) {
2138 * x86_bios_cpu_apicid is required to have processors listed
2139 * in same order as logical cpu numbers. Hence the first
2140 * entry is BSP, and so on.
2141 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2146 /* Logical cpuid 0 is reserved for BSP. */
2147 cpuid_to_apicid[0] = apicid;
2149 cpu = allocate_logical_cpuid(apicid);
2159 if (version == 0x0) {
2160 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2165 if (version != boot_cpu_apic_version) {
2166 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2167 boot_cpu_apic_version, cpu, version);
2170 if (apicid > max_physical_apicid)
2171 max_physical_apicid = apicid;
2173 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2174 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2175 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2177 #ifdef CONFIG_X86_32
2178 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2179 apic->x86_32_early_logical_apicid(cpu);
2181 set_cpu_possible(cpu, true);
2182 physid_set(apicid, phys_cpu_present_map);
2183 set_cpu_present(cpu, true);
2189 int hard_smp_processor_id(void)
2191 return read_apic_id();
2194 void default_init_apic_ldr(void)
2198 apic_write(APIC_DFR, APIC_DFR_VALUE);
2199 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2200 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2201 apic_write(APIC_LDR, val);
2204 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2205 const struct cpumask *andmask,
2206 unsigned int *apicid)
2210 for_each_cpu_and(cpu, cpumask, andmask) {
2211 if (cpumask_test_cpu(cpu, cpu_online_mask))
2215 if (likely(cpu < nr_cpu_ids)) {
2216 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2224 * Override the generic EOI implementation with an optimized version.
2225 * Only called during early boot when only one CPU is active and with
2226 * interrupts disabled, so we know this does not race with actual APIC driver
2229 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2233 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2234 /* Should happen once for each apic */
2235 WARN_ON((*drv)->eoi_write == eoi_write);
2236 (*drv)->native_eoi_write = (*drv)->eoi_write;
2237 (*drv)->eoi_write = eoi_write;
2241 static void __init apic_bsp_up_setup(void)
2243 #ifdef CONFIG_X86_64
2244 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2247 * Hack: In case of kdump, after a crash, kernel might be booting
2248 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2249 * might be zero if read from MP tables. Get it from LAPIC.
2251 # ifdef CONFIG_CRASH_DUMP
2252 boot_cpu_physical_apicid = read_apic_id();
2255 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2259 * apic_bsp_setup - Setup function for local apic and io-apic
2260 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2263 * apic_id of BSP APIC
2265 int __init apic_bsp_setup(bool upmode)
2271 apic_bsp_up_setup();
2275 id = apic_read(APIC_LDR);
2277 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2280 end_local_APIC_setup();
2281 irq_remap_enable_fault_handling();
2283 /* Setup local timer */
2284 x86_init.timers.setup_percpu_clockev();
2289 * This initializes the IO-APIC and APIC hardware if this is
2292 int __init APIC_init_uniprocessor(void)
2295 pr_info("Apic disabled\n");
2298 #ifdef CONFIG_X86_64
2299 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2301 pr_info("Apic disabled by BIOS\n");
2305 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2309 * Complain if the BIOS pretends there is one.
2311 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2312 APIC_INTEGRATED(boot_cpu_apic_version)) {
2313 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2314 boot_cpu_physical_apicid);
2319 if (!smp_found_config)
2320 disable_ioapic_support();
2322 default_setup_apic_routing();
2323 apic_bsp_setup(true);
2327 #ifdef CONFIG_UP_LATE_INIT
2328 void __init up_late_init(void)
2330 APIC_init_uniprocessor();
2341 * 'active' is true if the local APIC was enabled by us and
2342 * not the BIOS; this signifies that we are also responsible
2343 * for disabling it before entering apm/acpi suspend
2346 /* r/w apic fields */
2347 unsigned int apic_id;
2348 unsigned int apic_taskpri;
2349 unsigned int apic_ldr;
2350 unsigned int apic_dfr;
2351 unsigned int apic_spiv;
2352 unsigned int apic_lvtt;
2353 unsigned int apic_lvtpc;
2354 unsigned int apic_lvt0;
2355 unsigned int apic_lvt1;
2356 unsigned int apic_lvterr;
2357 unsigned int apic_tmict;
2358 unsigned int apic_tdcr;
2359 unsigned int apic_thmr;
2360 unsigned int apic_cmci;
2363 static int lapic_suspend(void)
2365 unsigned long flags;
2368 if (!apic_pm_state.active)
2371 maxlvt = lapic_get_maxlvt();
2373 apic_pm_state.apic_id = apic_read(APIC_ID);
2374 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2375 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2376 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2377 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2378 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2380 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2381 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2382 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2383 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2384 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2385 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2386 #ifdef CONFIG_X86_THERMAL_VECTOR
2388 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2390 #ifdef CONFIG_X86_MCE_INTEL
2392 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2395 local_irq_save(flags);
2396 disable_local_APIC();
2398 irq_remapping_disable();
2400 local_irq_restore(flags);
2404 static void lapic_resume(void)
2407 unsigned long flags;
2410 if (!apic_pm_state.active)
2413 local_irq_save(flags);
2416 * IO-APIC and PIC have their own resume routines.
2417 * We just mask them here to make sure the interrupt
2418 * subsystem is completely quiet while we enable x2apic
2419 * and interrupt-remapping.
2421 mask_ioapic_entries();
2422 legacy_pic->mask_all();
2428 * Make sure the APICBASE points to the right address
2430 * FIXME! This will be wrong if we ever support suspend on
2431 * SMP! We'll need to do this as part of the CPU restore!
2433 if (boot_cpu_data.x86 >= 6) {
2434 rdmsr(MSR_IA32_APICBASE, l, h);
2435 l &= ~MSR_IA32_APICBASE_BASE;
2436 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2437 wrmsr(MSR_IA32_APICBASE, l, h);
2441 maxlvt = lapic_get_maxlvt();
2442 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2443 apic_write(APIC_ID, apic_pm_state.apic_id);
2444 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2445 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2446 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2447 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2448 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2449 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2450 #ifdef CONFIG_X86_THERMAL_VECTOR
2452 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2454 #ifdef CONFIG_X86_MCE_INTEL
2456 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2459 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2460 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2461 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2462 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2463 apic_write(APIC_ESR, 0);
2464 apic_read(APIC_ESR);
2465 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2466 apic_write(APIC_ESR, 0);
2467 apic_read(APIC_ESR);
2469 irq_remapping_reenable(x2apic_mode);
2471 local_irq_restore(flags);
2475 * This device has no shutdown method - fully functioning local APICs
2476 * are needed on every CPU up until machine_halt/restart/poweroff.
2479 static struct syscore_ops lapic_syscore_ops = {
2480 .resume = lapic_resume,
2481 .suspend = lapic_suspend,
2484 static void apic_pm_activate(void)
2486 apic_pm_state.active = 1;
2489 static int __init init_lapic_sysfs(void)
2491 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2492 if (boot_cpu_has(X86_FEATURE_APIC))
2493 register_syscore_ops(&lapic_syscore_ops);
2498 /* local apic needs to resume before other devices access its registers. */
2499 core_initcall(init_lapic_sysfs);
2501 #else /* CONFIG_PM */
2503 static void apic_pm_activate(void) { }
2505 #endif /* CONFIG_PM */
2507 #ifdef CONFIG_X86_64
2509 static int multi_checked;
2512 static int set_multi(const struct dmi_system_id *d)
2516 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2521 static const struct dmi_system_id multi_dmi_table[] = {
2523 .callback = set_multi,
2524 .ident = "IBM System Summit2",
2526 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2527 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2533 static void dmi_check_multi(void)
2538 dmi_check_system(multi_dmi_table);
2543 * apic_is_clustered_box() -- Check if we can expect good TSC
2545 * Thus far, the major user of this is IBM's Summit2 series:
2546 * Clustered boxes may have unsynced TSC problems if they are
2548 * Use DMI to check them
2550 int apic_is_clustered_box(void)
2558 * APIC command line parameters
2560 static int __init setup_disableapic(char *arg)
2563 setup_clear_cpu_cap(X86_FEATURE_APIC);
2566 early_param("disableapic", setup_disableapic);
2568 /* same as disableapic, for compatibility */
2569 static int __init setup_nolapic(char *arg)
2571 return setup_disableapic(arg);
2573 early_param("nolapic", setup_nolapic);
2575 static int __init parse_lapic_timer_c2_ok(char *arg)
2577 local_apic_timer_c2_ok = 1;
2580 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2582 static int __init parse_disable_apic_timer(char *arg)
2584 disable_apic_timer = 1;
2587 early_param("noapictimer", parse_disable_apic_timer);
2589 static int __init parse_nolapic_timer(char *arg)
2591 disable_apic_timer = 1;
2594 early_param("nolapic_timer", parse_nolapic_timer);
2596 static int __init apic_set_verbosity(char *arg)
2599 #ifdef CONFIG_X86_64
2600 skip_ioapic_setup = 0;
2606 if (strcmp("debug", arg) == 0)
2607 apic_verbosity = APIC_DEBUG;
2608 else if (strcmp("verbose", arg) == 0)
2609 apic_verbosity = APIC_VERBOSE;
2611 pr_warning("APIC Verbosity level %s not recognised"
2612 " use apic=verbose or apic=debug\n", arg);
2618 early_param("apic", apic_set_verbosity);
2620 static int __init lapic_insert_resource(void)
2625 /* Put local APIC into the resource map. */
2626 lapic_resource.start = apic_phys;
2627 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2628 insert_resource(&iomem_resource, &lapic_resource);
2634 * need call insert after e820__reserve_resources()
2635 * that is using request_resource
2637 late_initcall(lapic_insert_resource);
2639 static int __init apic_set_disabled_cpu_apicid(char *arg)
2641 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2646 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2648 static int __init apic_set_extnmi(char *arg)
2653 if (!strncmp("all", arg, 3))
2654 apic_extnmi = APIC_EXTNMI_ALL;
2655 else if (!strncmp("none", arg, 4))
2656 apic_extnmi = APIC_EXTNMI_NONE;
2657 else if (!strncmp("bsp", arg, 3))
2658 apic_extnmi = APIC_EXTNMI_BSP;
2660 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2666 early_param("apic_extnmi", apic_set_extnmi);