2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/freezer.h>
36 #include <linux/kthread.h>
37 #include <linux/jiffies.h> /* time_after() */
38 #include <linux/slab.h>
39 #include <linux/bootmem.h>
46 #include <asm/proto.h>
49 #include <asm/timer.h>
50 #include <asm/i8259.h>
51 #include <asm/setup.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/hw_irq.h>
57 #define for_each_ioapic(idx) \
58 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
59 #define for_each_ioapic_reverse(idx) \
60 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
61 #define for_each_pin(idx, pin) \
62 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
63 #define for_each_ioapic_pin(idx, pin) \
64 for_each_ioapic((idx)) \
65 for_each_pin((idx), (pin))
67 #define for_each_irq_pin(entry, head) \
68 list_for_each_entry(entry, &head, list)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_MUTEX(ioapic_mutex);
78 static unsigned int ioapic_dynirq_base;
79 static int ioapic_initialized;
82 struct IO_APIC_route_entry entry;
97 static struct ioapic {
99 * # of IRQ routing registers
103 * Saved state during suspend/resume, or while enabling intr-remap.
105 struct IO_APIC_route_entry *saved_registers;
106 /* I/O APIC config */
107 struct mpc_ioapic mp_config;
108 /* IO APIC gsi routing info */
109 struct mp_ioapic_gsi gsi_config;
110 struct ioapic_domain_cfg irqdomain_cfg;
111 struct irq_domain *irqdomain;
112 struct mp_pin_info *pin_info;
113 struct resource *iomem_res;
114 } ioapics[MAX_IO_APICS];
116 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
118 int mpc_ioapic_id(int ioapic_idx)
120 return ioapics[ioapic_idx].mp_config.apicid;
123 unsigned int mpc_ioapic_addr(int ioapic_idx)
125 return ioapics[ioapic_idx].mp_config.apicaddr;
128 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
130 return &ioapics[ioapic_idx].gsi_config;
133 static inline int mp_ioapic_pin_count(int ioapic)
135 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
137 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
140 u32 mp_pin_to_gsi(int ioapic, int pin)
142 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
145 static inline bool mp_is_legacy_irq(int irq)
147 return irq >= 0 && irq < nr_legacy_irqs();
151 * Initialize all legacy IRQs and all pins on the first IOAPIC
152 * if we have legacy interrupt controller. Kernel boot option "pirq="
153 * may rely on non-legacy pins on the first IOAPIC.
155 static inline int mp_init_irq_at_boot(int ioapic, int irq)
157 if (!nr_legacy_irqs())
160 return ioapic == 0 || mp_is_legacy_irq(irq);
163 static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
165 return ioapics[ioapic_idx].pin_info + pin;
168 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
170 return ioapics[ioapic].irqdomain;
175 /* The one past the highest gsi number used */
178 /* MP IRQ source entries */
179 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
181 /* # of MP IRQ source entries */
185 int mp_bus_id_to_type[MAX_MP_BUSSES];
188 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
190 int skip_ioapic_setup;
193 * disable_ioapic_support() - disables ioapic support at runtime
195 void disable_ioapic_support(void)
199 noioapicreroute = -1;
201 skip_ioapic_setup = 1;
204 static int __init parse_noapic(char *str)
206 /* disable IO-APIC */
207 disable_ioapic_support();
210 early_param("noapic", parse_noapic);
212 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213 void mp_save_irq(struct mpc_intsrc *m)
217 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 m->srcbusirq, m->dstapic, m->dstirq);
222 for (i = 0; i < mp_irq_entries; i++) {
223 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
227 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 panic("Max # of irq sources exceeded!!\n");
232 struct irq_pin_list {
233 struct list_head list;
237 static struct irq_pin_list *alloc_irq_pin_list(int node)
239 return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
242 static void alloc_ioapic_saved_registers(int idx)
246 if (ioapics[idx].saved_registers)
249 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
250 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
251 if (!ioapics[idx].saved_registers)
252 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
255 static void free_ioapic_saved_registers(int idx)
257 kfree(ioapics[idx].saved_registers);
258 ioapics[idx].saved_registers = NULL;
261 int __init arch_early_ioapic_init(void)
265 if (!nr_legacy_irqs())
269 alloc_ioapic_saved_registers(i);
276 unsigned int unused[3];
278 unsigned int unused2[11];
282 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
284 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
285 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
288 void io_apic_eoi(unsigned int apic, unsigned int vector)
290 struct io_apic __iomem *io_apic = io_apic_base(apic);
291 writel(vector, &io_apic->eoi);
294 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
296 struct io_apic __iomem *io_apic = io_apic_base(apic);
297 writel(reg, &io_apic->index);
298 return readl(&io_apic->data);
301 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
303 struct io_apic __iomem *io_apic = io_apic_base(apic);
305 writel(reg, &io_apic->index);
306 writel(value, &io_apic->data);
310 * Re-write a value: to be used for read-modify-write
311 * cycles where the read already set up the index register.
313 * Older SiS APIC requires we rewrite the index register
315 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
317 struct io_apic __iomem *io_apic = io_apic_base(apic);
320 writel(reg, &io_apic->index);
321 writel(value, &io_apic->data);
325 struct { u32 w1, w2; };
326 struct IO_APIC_route_entry entry;
329 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
331 union entry_union eu;
333 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
334 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
339 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
341 union entry_union eu;
344 raw_spin_lock_irqsave(&ioapic_lock, flags);
345 eu.entry = __ioapic_read_entry(apic, pin);
346 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
352 * When we write a new IO APIC routing entry, we need to write the high
353 * word first! If the mask bit in the low word is clear, we will enable
354 * the interrupt, and we need to make sure the entry is fully populated
355 * before that happens.
357 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
359 union entry_union eu = {{0, 0}};
362 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
363 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
366 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
370 raw_spin_lock_irqsave(&ioapic_lock, flags);
371 __ioapic_write_entry(apic, pin, e);
372 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
376 * When we mask an IO APIC routing entry, we need to write the low
377 * word first, in order to set the mask bit before we change the
380 static void ioapic_mask_entry(int apic, int pin)
383 union entry_union eu = { .entry.mask = 1 };
385 raw_spin_lock_irqsave(&ioapic_lock, flags);
386 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
387 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
388 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
392 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
393 * shared ISA-space IRQs, so we have to support them. We are super
394 * fast in the common case, and fast for shared ISA-space IRQs.
396 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
398 struct irq_pin_list *entry;
400 /* don't allow duplicates */
401 for_each_irq_pin(entry, cfg->irq_2_pin)
402 if (entry->apic == apic && entry->pin == pin)
405 entry = alloc_irq_pin_list(node);
407 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
414 list_add_tail(&entry->list, &cfg->irq_2_pin);
418 static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
420 struct irq_pin_list *tmp, *entry;
422 list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list)
423 if (entry->apic == apic && entry->pin == pin) {
424 list_del(&entry->list);
430 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
432 if (__add_pin_to_irq_node(cfg, node, apic, pin))
433 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
437 * Reroute an IRQ to a different pin.
439 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
440 int oldapic, int oldpin,
441 int newapic, int newpin)
443 struct irq_pin_list *entry;
445 for_each_irq_pin(entry, cfg->irq_2_pin) {
446 if (entry->apic == oldapic && entry->pin == oldpin) {
447 entry->apic = newapic;
449 /* every one is different, right? */
454 /* old apic/pin didn't exist, so just add new ones */
455 add_pin_to_irq_node(cfg, node, newapic, newpin);
458 static void __io_apic_modify_irq(struct irq_pin_list *entry,
459 int mask_and, int mask_or,
460 void (*final)(struct irq_pin_list *entry))
462 unsigned int reg, pin;
465 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
468 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
473 static void io_apic_modify_irq(struct irq_cfg *cfg,
474 int mask_and, int mask_or,
475 void (*final)(struct irq_pin_list *entry))
477 struct irq_pin_list *entry;
479 for_each_irq_pin(entry, cfg->irq_2_pin)
480 __io_apic_modify_irq(entry, mask_and, mask_or, final);
483 static void io_apic_sync(struct irq_pin_list *entry)
486 * Synchronize the IO-APIC and the CPU by doing
487 * a dummy read from the IO-APIC
489 struct io_apic __iomem *io_apic;
491 io_apic = io_apic_base(entry->apic);
492 readl(&io_apic->data);
495 static void mask_ioapic(struct irq_cfg *cfg)
499 raw_spin_lock_irqsave(&ioapic_lock, flags);
500 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
501 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
504 static void mask_ioapic_irq(struct irq_data *data)
506 mask_ioapic(irqd_cfg(data));
509 static void __unmask_ioapic(struct irq_cfg *cfg)
511 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
514 static void unmask_ioapic(struct irq_cfg *cfg)
518 raw_spin_lock_irqsave(&ioapic_lock, flags);
519 __unmask_ioapic(cfg);
520 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
523 static void unmask_ioapic_irq(struct irq_data *data)
525 unmask_ioapic(irqd_cfg(data));
529 * IO-APIC versions below 0x20 don't support EOI register.
530 * For the record, here is the information about various versions:
532 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
533 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
536 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
537 * version as 0x2. This is an error with documentation and these ICH chips
538 * use io-apic's of version 0x20.
540 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
541 * Otherwise, we simulate the EOI message manually by changing the trigger
542 * mode to edge and then back to level, with RTE being masked during this.
544 void native_eoi_ioapic_pin(int apic, int pin, int vector)
546 if (mpc_ioapic_ver(apic) >= 0x20) {
547 io_apic_eoi(apic, vector);
549 struct IO_APIC_route_entry entry, entry1;
551 entry = entry1 = __ioapic_read_entry(apic, pin);
554 * Mask the entry and change the trigger mode to edge.
557 entry1.trigger = IOAPIC_EDGE;
559 __ioapic_write_entry(apic, pin, entry1);
562 * Restore the previous level triggered entry.
564 __ioapic_write_entry(apic, pin, entry);
568 void eoi_ioapic_pin(int vector, struct irq_cfg *cfg)
571 struct irq_pin_list *entry;
573 raw_spin_lock_irqsave(&ioapic_lock, flags);
574 for_each_irq_pin(entry, cfg->irq_2_pin)
575 native_eoi_ioapic_pin(entry->apic, entry->pin, vector);
576 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
579 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
581 struct irq_pin_list *entry;
584 raw_spin_lock_irqsave(&ioapic_lock, flags);
585 for_each_irq_pin(entry, cfg->irq_2_pin)
586 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
588 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
591 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
593 struct IO_APIC_route_entry entry;
595 /* Check delivery_mode to be sure we're not clearing an SMI pin */
596 entry = ioapic_read_entry(apic, pin);
597 if (entry.delivery_mode == dest_SMI)
601 * Make sure the entry is masked and re-read the contents to check
602 * if it is a level triggered pin and if the remote-IRR is set.
606 ioapic_write_entry(apic, pin, entry);
607 entry = ioapic_read_entry(apic, pin);
614 * Make sure the trigger mode is set to level. Explicit EOI
615 * doesn't clear the remote-IRR if the trigger mode is not
618 if (!entry.trigger) {
619 entry.trigger = IOAPIC_LEVEL;
620 ioapic_write_entry(apic, pin, entry);
622 raw_spin_lock_irqsave(&ioapic_lock, flags);
623 native_eoi_ioapic_pin(apic, pin, entry.vector);
624 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
628 * Clear the rest of the bits in the IO-APIC RTE except for the mask
631 ioapic_mask_entry(apic, pin);
632 entry = ioapic_read_entry(apic, pin);
634 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
635 mpc_ioapic_id(apic), pin);
638 static void clear_IO_APIC (void)
642 for_each_ioapic_pin(apic, pin)
643 clear_IO_APIC_pin(apic, pin);
648 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
649 * specific CPU-side IRQs.
653 static int pirq_entries[MAX_PIRQS] = {
654 [0 ... MAX_PIRQS - 1] = -1
657 static int __init ioapic_pirq_setup(char *str)
660 int ints[MAX_PIRQS+1];
662 get_options(str, ARRAY_SIZE(ints), ints);
664 apic_printk(APIC_VERBOSE, KERN_INFO
665 "PIRQ redirection, working around broken MP-BIOS.\n");
667 if (ints[0] < MAX_PIRQS)
670 for (i = 0; i < max; i++) {
671 apic_printk(APIC_VERBOSE, KERN_DEBUG
672 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
674 * PIRQs are mapped upside down, usually.
676 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
681 __setup("pirq=", ioapic_pirq_setup);
682 #endif /* CONFIG_X86_32 */
685 * Saves all the IO-APIC RTE's
687 int save_ioapic_entries(void)
692 for_each_ioapic(apic) {
693 if (!ioapics[apic].saved_registers) {
698 for_each_pin(apic, pin)
699 ioapics[apic].saved_registers[pin] =
700 ioapic_read_entry(apic, pin);
707 * Mask all IO APIC entries.
709 void mask_ioapic_entries(void)
713 for_each_ioapic(apic) {
714 if (!ioapics[apic].saved_registers)
717 for_each_pin(apic, pin) {
718 struct IO_APIC_route_entry entry;
720 entry = ioapics[apic].saved_registers[pin];
723 ioapic_write_entry(apic, pin, entry);
730 * Restore IO APIC entries which was saved in the ioapic structure.
732 int restore_ioapic_entries(void)
736 for_each_ioapic(apic) {
737 if (!ioapics[apic].saved_registers)
740 for_each_pin(apic, pin)
741 ioapic_write_entry(apic, pin,
742 ioapics[apic].saved_registers[pin]);
748 * Find the IRQ entry number of a certain pin.
750 static int find_irq_entry(int ioapic_idx, int pin, int type)
754 for (i = 0; i < mp_irq_entries; i++)
755 if (mp_irqs[i].irqtype == type &&
756 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
757 mp_irqs[i].dstapic == MP_APIC_ALL) &&
758 mp_irqs[i].dstirq == pin)
765 * Find the pin to which IRQ[irq] (ISA) is connected
767 static int __init find_isa_irq_pin(int irq, int type)
771 for (i = 0; i < mp_irq_entries; i++) {
772 int lbus = mp_irqs[i].srcbus;
774 if (test_bit(lbus, mp_bus_not_pci) &&
775 (mp_irqs[i].irqtype == type) &&
776 (mp_irqs[i].srcbusirq == irq))
778 return mp_irqs[i].dstirq;
783 static int __init find_isa_irq_apic(int irq, int type)
787 for (i = 0; i < mp_irq_entries; i++) {
788 int lbus = mp_irqs[i].srcbus;
790 if (test_bit(lbus, mp_bus_not_pci) &&
791 (mp_irqs[i].irqtype == type) &&
792 (mp_irqs[i].srcbusirq == irq))
796 if (i < mp_irq_entries) {
799 for_each_ioapic(ioapic_idx)
800 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
809 * EISA Edge/Level control register, ELCR
811 static int EISA_ELCR(unsigned int irq)
813 if (irq < nr_legacy_irqs()) {
814 unsigned int port = 0x4d0 + (irq >> 3);
815 return (inb(port) >> (irq & 7)) & 1;
817 apic_printk(APIC_VERBOSE, KERN_INFO
818 "Broken MPtable reports ISA irq %d\n", irq);
824 /* ISA interrupts are always polarity zero edge triggered,
825 * when listed as conforming in the MP table. */
827 #define default_ISA_trigger(idx) (0)
828 #define default_ISA_polarity(idx) (0)
830 /* EISA interrupts are always polarity zero and can be edge or level
831 * trigger depending on the ELCR value. If an interrupt is listed as
832 * EISA conforming in the MP table, that means its trigger type must
833 * be read in from the ELCR */
835 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
836 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
838 /* PCI interrupts are always polarity one level triggered,
839 * when listed as conforming in the MP table. */
841 #define default_PCI_trigger(idx) (1)
842 #define default_PCI_polarity(idx) (1)
844 static int irq_polarity(int idx)
846 int bus = mp_irqs[idx].srcbus;
850 * Determine IRQ line polarity (high active or low active):
852 switch (mp_irqs[idx].irqflag & 3)
854 case 0: /* conforms, ie. bus-type dependent polarity */
855 if (test_bit(bus, mp_bus_not_pci))
856 polarity = default_ISA_polarity(idx);
858 polarity = default_PCI_polarity(idx);
860 case 1: /* high active */
865 case 2: /* reserved */
867 pr_warn("broken BIOS!!\n");
871 case 3: /* low active */
876 default: /* invalid */
878 pr_warn("broken BIOS!!\n");
886 static int irq_trigger(int idx)
888 int bus = mp_irqs[idx].srcbus;
892 * Determine IRQ trigger mode (edge or level sensitive):
894 switch ((mp_irqs[idx].irqflag>>2) & 3)
896 case 0: /* conforms, ie. bus-type dependent */
897 if (test_bit(bus, mp_bus_not_pci))
898 trigger = default_ISA_trigger(idx);
900 trigger = default_PCI_trigger(idx);
902 switch (mp_bus_id_to_type[bus]) {
903 case MP_BUS_ISA: /* ISA pin */
905 /* set before the switch */
908 case MP_BUS_EISA: /* EISA pin */
910 trigger = default_EISA_trigger(idx);
913 case MP_BUS_PCI: /* PCI pin */
915 /* set before the switch */
920 pr_warn("broken BIOS!!\n");
932 case 2: /* reserved */
934 pr_warn("broken BIOS!!\n");
943 default: /* invalid */
945 pr_warn("broken BIOS!!\n");
953 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
954 int trigger, int polarity)
956 init_irq_alloc_info(info, NULL);
957 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
958 info->ioapic_node = node;
959 info->ioapic_trigger = trigger;
960 info->ioapic_polarity = polarity;
961 info->ioapic_valid = 1;
965 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
968 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
969 struct irq_alloc_info *src,
970 u32 gsi, int ioapic_idx, int pin)
972 int trigger, polarity;
974 copy_irq_alloc_info(dst, src);
975 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
976 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
977 dst->ioapic_pin = pin;
978 dst->ioapic_valid = 1;
979 if (src && src->ioapic_valid) {
980 dst->ioapic_node = src->ioapic_node;
981 dst->ioapic_trigger = src->ioapic_trigger;
982 dst->ioapic_polarity = src->ioapic_polarity;
984 dst->ioapic_node = NUMA_NO_NODE;
985 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
986 dst->ioapic_trigger = trigger;
987 dst->ioapic_polarity = polarity;
990 * PCI interrupts are always polarity one level
993 dst->ioapic_trigger = 1;
994 dst->ioapic_polarity = 1;
999 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
1001 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
1004 static void mp_register_handler(unsigned int irq, unsigned long trigger)
1006 irq_flow_handler_t hdl;
1010 irq_set_status_flags(irq, IRQ_LEVEL);
1013 irq_clear_status_flags(irq, IRQ_LEVEL);
1017 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1018 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
1021 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
1023 struct mp_chip_data *data = irq_get_chip_data(irq);
1026 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
1027 * and polarity attirbutes. So allow the first user to reprogram the
1028 * pin with real trigger and polarity attributes.
1030 if (irq < nr_legacy_irqs() && data->count == 1) {
1031 if (info->ioapic_trigger != data->trigger)
1032 mp_register_handler(irq, data->trigger);
1033 data->entry.trigger = data->trigger = info->ioapic_trigger;
1034 data->entry.polarity = data->polarity = info->ioapic_polarity;
1037 return data->trigger == info->ioapic_trigger &&
1038 data->polarity == info->ioapic_polarity;
1041 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
1042 struct irq_alloc_info *info)
1044 bool legacy = false;
1046 int type = ioapics[ioapic].irqdomain_cfg.type;
1049 case IOAPIC_DOMAIN_LEGACY:
1051 * Dynamically allocate IRQ number for non-ISA IRQs in the first
1052 * 16 GSIs on some weird platforms.
1054 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
1056 legacy = mp_is_legacy_irq(irq);
1058 case IOAPIC_DOMAIN_STRICT:
1061 case IOAPIC_DOMAIN_DYNAMIC:
1064 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1068 return __irq_domain_alloc_irqs(domain, irq, 1,
1069 ioapic_alloc_attr_node(info),
1074 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
1075 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
1076 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
1077 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1078 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
1079 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
1080 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
1081 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
1083 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
1084 int irq, int ioapic, int pin,
1085 struct irq_alloc_info *info)
1087 struct mp_chip_data *data;
1088 struct irq_data *irq_data = irq_get_irq_data(irq);
1089 int node = ioapic_alloc_attr_node(info);
1092 * Legacy ISA IRQ has already been allocated, just add pin to
1093 * the pin list assoicated with this IRQ and program the IOAPIC
1094 * entry. The IOAPIC entry
1096 if (irq_data && irq_data->parent_data) {
1097 struct irq_cfg *cfg = irqd_cfg(irq_data);
1099 if (!mp_check_pin_attr(irq, info))
1101 if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin))
1104 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
1106 irq_data = irq_domain_get_irq_data(domain, irq);
1107 data = irq_data->chip_data;
1108 data->isa_irq = true;
1115 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1116 unsigned int flags, struct irq_alloc_info *info)
1119 bool legacy = false;
1120 struct irq_alloc_info tmp;
1121 struct mp_chip_data *data;
1122 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1127 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1128 irq = mp_irqs[idx].srcbusirq;
1129 legacy = mp_is_legacy_irq(irq);
1132 mutex_lock(&ioapic_mutex);
1133 if (!(flags & IOAPIC_MAP_ALLOC)) {
1135 irq = irq_find_mapping(domain, pin);
1140 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1142 irq = alloc_isa_irq_from_domain(domain, irq,
1144 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1145 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1146 else if (!mp_check_pin_attr(irq, &tmp))
1149 data = irq_get_chip_data(irq);
1153 mutex_unlock(&ioapic_mutex);
1158 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1160 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1163 * Debugging check, we are in big trouble if this message pops up!
1165 if (mp_irqs[idx].dstirq != pin)
1166 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1168 #ifdef CONFIG_X86_32
1170 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1172 if ((pin >= 16) && (pin <= 23)) {
1173 if (pirq_entries[pin-16] != -1) {
1174 if (!pirq_entries[pin-16]) {
1175 apic_printk(APIC_VERBOSE, KERN_DEBUG
1176 "disabling PIRQ%d\n", pin-16);
1178 int irq = pirq_entries[pin-16];
1179 apic_printk(APIC_VERBOSE, KERN_DEBUG
1180 "using PIRQ%d -> IRQ %d\n",
1188 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1191 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
1192 struct irq_alloc_info *info)
1194 int ioapic, pin, idx;
1196 ioapic = mp_find_ioapic(gsi);
1200 pin = mp_find_ioapic_pin(ioapic, gsi);
1201 idx = find_irq_entry(ioapic, pin, mp_INT);
1202 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1205 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1208 void mp_unmap_irq(int irq)
1210 struct irq_data *irq_data = irq_get_irq_data(irq);
1211 struct mp_chip_data *data;
1213 if (!irq_data || !irq_data->domain)
1216 data = irq_data->chip_data;
1217 if (!data || data->isa_irq)
1220 mutex_lock(&ioapic_mutex);
1221 if (--data->count == 0)
1222 irq_domain_free_irqs(irq, 1);
1223 mutex_unlock(&ioapic_mutex);
1227 * Find a specific PCI IRQ entry.
1228 * Not an __init, possibly needed by modules
1230 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1232 int irq, i, best_ioapic = -1, best_idx = -1;
1234 apic_printk(APIC_DEBUG,
1235 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1237 if (test_bit(bus, mp_bus_not_pci)) {
1238 apic_printk(APIC_VERBOSE,
1239 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1243 for (i = 0; i < mp_irq_entries; i++) {
1244 int lbus = mp_irqs[i].srcbus;
1245 int ioapic_idx, found = 0;
1247 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1248 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1251 for_each_ioapic(ioapic_idx)
1252 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1253 mp_irqs[i].dstapic == MP_APIC_ALL) {
1261 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1262 if (irq > 0 && !IO_APIC_IRQ(irq))
1265 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1267 best_ioapic = ioapic_idx;
1272 * Use the first all-but-pin matching entry as a
1273 * best-guess fuzzy result for broken mptables.
1277 best_ioapic = ioapic_idx;
1284 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1287 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1289 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1291 #ifdef CONFIG_X86_32
1292 static inline int IO_APIC_irq_trigger(int irq)
1296 for_each_ioapic_pin(apic, pin) {
1297 idx = find_irq_entry(apic, pin, mp_INT);
1298 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1299 return irq_trigger(idx);
1302 * nonexistent IRQs are edge default
1307 static inline int IO_APIC_irq_trigger(int irq)
1313 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1314 unsigned long trigger)
1316 struct irq_chip *chip = &ioapic_chip;
1317 irq_flow_handler_t hdl;
1320 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1321 trigger == IOAPIC_LEVEL) {
1322 irq_set_status_flags(irq, IRQ_LEVEL);
1325 irq_clear_status_flags(irq, IRQ_LEVEL);
1329 if (setup_remapped_irq(irq, cfg, chip))
1330 fasteoi = trigger != 0;
1332 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1333 irq_set_chip_and_handler_name(irq, chip, hdl,
1334 fasteoi ? "fasteoi" : "edge");
1337 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1338 unsigned int destination, int vector,
1339 struct io_apic_irq_attr *attr)
1341 memset(entry, 0, sizeof(*entry));
1343 entry->delivery_mode = apic->irq_delivery_mode;
1344 entry->dest_mode = apic->irq_dest_mode;
1345 entry->dest = destination;
1346 entry->vector = vector;
1347 entry->mask = 0; /* enable IRQ */
1348 entry->trigger = attr->trigger;
1349 entry->polarity = attr->polarity;
1352 * Mask level triggered irqs.
1353 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1361 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1362 struct io_apic_irq_attr *attr)
1364 struct IO_APIC_route_entry entry;
1367 if (!IO_APIC_IRQ(irq))
1370 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1373 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1375 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1376 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1377 clear_irq_vector(irq, cfg);
1382 apic_printk(APIC_VERBOSE,KERN_DEBUG
1383 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1384 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1385 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1386 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1388 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) {
1389 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1390 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1391 clear_irq_vector(irq, cfg);
1396 ioapic_register_intr(irq, cfg, attr->trigger);
1397 if (irq < nr_legacy_irqs())
1398 legacy_pic->mask(irq);
1400 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1403 static void __init setup_IO_APIC_irqs(void)
1405 unsigned int ioapic, pin;
1408 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1410 for_each_ioapic_pin(ioapic, pin) {
1411 idx = find_irq_entry(ioapic, pin, mp_INT);
1413 apic_printk(APIC_VERBOSE,
1414 KERN_DEBUG " apic %d pin %d not connected\n",
1415 mpc_ioapic_id(ioapic), pin);
1417 pin_2_irq(idx, ioapic, pin,
1418 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1423 * Set up the timer pin, possibly with the 8259A-master behind.
1425 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1426 unsigned int pin, int vector)
1428 struct IO_APIC_route_entry entry;
1431 memset(&entry, 0, sizeof(entry));
1434 * We use logical delivery to get the timer IRQ
1437 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1438 apic->target_cpus(), &dest)))
1441 entry.dest_mode = apic->irq_dest_mode;
1442 entry.mask = 0; /* don't mask IRQ for edge */
1444 entry.delivery_mode = apic->irq_delivery_mode;
1447 entry.vector = vector;
1450 * The timer IRQ doesn't have to know that behind the
1451 * scene we may have a 8259A-master in AEOI mode ...
1453 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1457 * Add it to the IO-APIC irq-routing table:
1459 ioapic_write_entry(ioapic_idx, pin, entry);
1462 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1466 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1468 for (i = 0; i <= nr_entries; i++) {
1469 struct IO_APIC_route_entry entry;
1471 entry = ioapic_read_entry(apic, i);
1473 pr_debug(" %02x %02X ", i, entry.dest);
1474 pr_cont("%1d %1d %1d %1d %1d "
1480 entry.delivery_status,
1482 entry.delivery_mode,
1487 void intel_ir_io_apic_print_entries(unsigned int apic,
1488 unsigned int nr_entries)
1492 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1494 for (i = 0; i <= nr_entries; i++) {
1495 struct IR_IO_APIC_route_entry *ir_entry;
1496 struct IO_APIC_route_entry entry;
1498 entry = ioapic_read_entry(apic, i);
1500 ir_entry = (struct IR_IO_APIC_route_entry *)&entry;
1502 pr_debug(" %02x %04X ", i, ir_entry->index);
1503 pr_cont("%1d %1d %1d %1d %1d "
1504 "%1d %1d %X %02X\n",
1510 ir_entry->delivery_status,
1517 void ioapic_zap_locks(void)
1519 raw_spin_lock_init(&ioapic_lock);
1522 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1526 struct IO_APIC_route_entry entry;
1527 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1529 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1530 for (i = 0; i <= nr_entries; i++) {
1531 entry = ioapic_read_entry(apic, i);
1532 snprintf(buf, sizeof(buf),
1533 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1534 i, entry.mask ? "disabled" : "enabled ",
1535 entry.trigger ? "level" : "edge ",
1536 entry.polarity ? "low " : "high",
1537 entry.vector, entry.irr, entry.delivery_status);
1538 if (ir_entry->format)
1539 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1540 buf, (ir_entry->index << 15) | ir_entry->index,
1543 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1544 buf, entry.dest_mode ? "logical " : "physical",
1545 entry.dest, entry.delivery_mode);
1549 static void __init print_IO_APIC(int ioapic_idx)
1551 union IO_APIC_reg_00 reg_00;
1552 union IO_APIC_reg_01 reg_01;
1553 union IO_APIC_reg_02 reg_02;
1554 union IO_APIC_reg_03 reg_03;
1555 unsigned long flags;
1557 raw_spin_lock_irqsave(&ioapic_lock, flags);
1558 reg_00.raw = io_apic_read(ioapic_idx, 0);
1559 reg_01.raw = io_apic_read(ioapic_idx, 1);
1560 if (reg_01.bits.version >= 0x10)
1561 reg_02.raw = io_apic_read(ioapic_idx, 2);
1562 if (reg_01.bits.version >= 0x20)
1563 reg_03.raw = io_apic_read(ioapic_idx, 3);
1564 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1566 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1567 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1568 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1569 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1570 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1572 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1573 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1574 reg_01.bits.entries);
1576 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1577 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1578 reg_01.bits.version);
1581 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1582 * but the value of reg_02 is read as the previous read register
1583 * value, so ignore it if reg_02 == reg_01.
1585 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1586 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1587 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1591 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1592 * or reg_03, but the value of reg_0[23] is read as the previous read
1593 * register value, so ignore it if reg_03 == reg_0[12].
1595 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1596 reg_03.raw != reg_01.raw) {
1597 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1598 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1601 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1602 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1605 void __init print_IO_APICs(void)
1608 struct irq_cfg *cfg;
1610 struct irq_chip *chip;
1612 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1613 for_each_ioapic(ioapic_idx)
1614 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1615 mpc_ioapic_id(ioapic_idx),
1616 ioapics[ioapic_idx].nr_registers);
1619 * We are a bit conservative about what we expect. We have to
1620 * know about every hardware change ASAP.
1622 printk(KERN_INFO "testing the IO APIC.......................\n");
1624 for_each_ioapic(ioapic_idx)
1625 print_IO_APIC(ioapic_idx);
1627 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1628 for_each_active_irq(irq) {
1629 struct irq_pin_list *entry;
1631 chip = irq_get_chip(irq);
1632 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1638 if (list_empty(&cfg->irq_2_pin))
1640 printk(KERN_DEBUG "IRQ%d ", irq);
1641 for_each_irq_pin(entry, cfg->irq_2_pin)
1642 pr_cont("-> %d:%d", entry->apic, entry->pin);
1646 printk(KERN_INFO ".................................... done.\n");
1649 /* Where if anywhere is the i8259 connect in external int mode */
1650 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1652 void __init enable_IO_APIC(void)
1654 int i8259_apic, i8259_pin;
1657 if (skip_ioapic_setup)
1660 if (!nr_legacy_irqs() || !nr_ioapics)
1663 for_each_ioapic_pin(apic, pin) {
1664 /* See if any of the pins is in ExtINT mode */
1665 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1667 /* If the interrupt line is enabled and in ExtInt mode
1668 * I have found the pin where the i8259 is connected.
1670 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1671 ioapic_i8259.apic = apic;
1672 ioapic_i8259.pin = pin;
1677 /* Look to see what if the MP table has reported the ExtINT */
1678 /* If we could not find the appropriate pin by looking at the ioapic
1679 * the i8259 probably is not connected the ioapic but give the
1680 * mptable a chance anyway.
1682 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1683 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1684 /* Trust the MP table if nothing is setup in the hardware */
1685 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1686 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1687 ioapic_i8259.pin = i8259_pin;
1688 ioapic_i8259.apic = i8259_apic;
1690 /* Complain if the MP table and the hardware disagree */
1691 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1692 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1694 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1698 * Do not trust the IO-APIC being empty at bootup
1703 void native_disable_io_apic(void)
1706 * If the i8259 is routed through an IOAPIC
1707 * Put that IOAPIC in virtual wire mode
1708 * so legacy interrupts can be delivered.
1710 if (ioapic_i8259.pin != -1) {
1711 struct IO_APIC_route_entry entry;
1713 memset(&entry, 0, sizeof(entry));
1714 entry.mask = 0; /* Enabled */
1715 entry.trigger = 0; /* Edge */
1717 entry.polarity = 0; /* High */
1718 entry.delivery_status = 0;
1719 entry.dest_mode = 0; /* Physical */
1720 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1722 entry.dest = read_apic_id();
1725 * Add it to the IO-APIC irq-routing table:
1727 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1730 if (cpu_has_apic || apic_from_smp_config())
1731 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1736 * Not an __init, needed by the reboot code
1738 void disable_IO_APIC(void)
1741 * Clear the IO-APIC before rebooting:
1745 if (!nr_legacy_irqs())
1748 x86_io_apic_ops.disable();
1751 #ifdef CONFIG_X86_32
1753 * function to set the IO-APIC physical IDs based on the
1754 * values stored in the MPC table.
1756 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1758 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1760 union IO_APIC_reg_00 reg_00;
1761 physid_mask_t phys_id_present_map;
1764 unsigned char old_id;
1765 unsigned long flags;
1768 * This is broken; anything with a real cpu count has to
1769 * circumvent this idiocy regardless.
1771 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1774 * Set the IOAPIC ID to the value stored in the MPC table.
1776 for_each_ioapic(ioapic_idx) {
1777 /* Read the register 0 value */
1778 raw_spin_lock_irqsave(&ioapic_lock, flags);
1779 reg_00.raw = io_apic_read(ioapic_idx, 0);
1780 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1782 old_id = mpc_ioapic_id(ioapic_idx);
1784 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1785 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1786 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1787 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1789 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1793 * Sanity check, is the ID really free? Every APIC in a
1794 * system must have a unique ID or we get lots of nice
1795 * 'stuck on smp_invalidate_needed IPI wait' messages.
1797 if (apic->check_apicid_used(&phys_id_present_map,
1798 mpc_ioapic_id(ioapic_idx))) {
1799 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1800 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1801 for (i = 0; i < get_physical_broadcast(); i++)
1802 if (!physid_isset(i, phys_id_present_map))
1804 if (i >= get_physical_broadcast())
1805 panic("Max APIC ID exceeded!\n");
1806 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1808 physid_set(i, phys_id_present_map);
1809 ioapics[ioapic_idx].mp_config.apicid = i;
1812 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1814 apic_printk(APIC_VERBOSE, "Setting %d in the "
1815 "phys_id_present_map\n",
1816 mpc_ioapic_id(ioapic_idx));
1817 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1821 * We need to adjust the IRQ routing table
1822 * if the ID changed.
1824 if (old_id != mpc_ioapic_id(ioapic_idx))
1825 for (i = 0; i < mp_irq_entries; i++)
1826 if (mp_irqs[i].dstapic == old_id)
1828 = mpc_ioapic_id(ioapic_idx);
1831 * Update the ID register according to the right value
1832 * from the MPC table if they are different.
1834 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1837 apic_printk(APIC_VERBOSE, KERN_INFO
1838 "...changing IO-APIC physical APIC ID to %d ...",
1839 mpc_ioapic_id(ioapic_idx));
1841 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1842 raw_spin_lock_irqsave(&ioapic_lock, flags);
1843 io_apic_write(ioapic_idx, 0, reg_00.raw);
1844 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1849 raw_spin_lock_irqsave(&ioapic_lock, flags);
1850 reg_00.raw = io_apic_read(ioapic_idx, 0);
1851 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1852 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1853 pr_cont("could not set ID!\n");
1855 apic_printk(APIC_VERBOSE, " ok.\n");
1859 void __init setup_ioapic_ids_from_mpc(void)
1865 * Don't check I/O APIC IDs for xAPIC systems. They have
1866 * no meaning without the serial APIC bus.
1868 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1869 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1871 setup_ioapic_ids_from_mpc_nocheck();
1875 int no_timer_check __initdata;
1877 static int __init notimercheck(char *s)
1882 __setup("no_timer_check", notimercheck);
1885 * There is a nasty bug in some older SMP boards, their mptable lies
1886 * about the timer IRQ. We do the following to work around the situation:
1888 * - timer IRQ defaults to IO-APIC IRQ
1889 * - if this function detects that timer IRQs are defunct, then we fall
1890 * back to ISA timer IRQs
1892 static int __init timer_irq_works(void)
1894 unsigned long t1 = jiffies;
1895 unsigned long flags;
1900 local_save_flags(flags);
1902 /* Let ten ticks pass... */
1903 mdelay((10 * 1000) / HZ);
1904 local_irq_restore(flags);
1907 * Expect a few ticks at least, to be sure some possible
1908 * glue logic does not lock up after one or two first
1909 * ticks in a non-ExtINT mode. Also the local APIC
1910 * might have cached one ExtINT interrupt. Finally, at
1911 * least one tick may be lost due to delays.
1915 if (time_after(jiffies, t1 + 4))
1921 * In the SMP+IOAPIC case it might happen that there are an unspecified
1922 * number of pending IRQ events unhandled. These cases are very rare,
1923 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1924 * better to do it this way as thus we do not have to be aware of
1925 * 'pending' interrupts in the IRQ path, except at this point.
1928 * Edge triggered needs to resend any interrupt
1929 * that was delayed but this is now handled in the device
1934 * Starting up a edge-triggered IO-APIC interrupt is
1935 * nasty - we need to make sure that we get the edge.
1936 * If it is already asserted for some reason, we need
1937 * return 1 to indicate that is was pending.
1939 * This is not complete - we should be able to fake
1940 * an edge even if it isn't on the 8259A...
1943 static unsigned int startup_ioapic_irq(struct irq_data *data)
1945 int was_pending = 0, irq = data->irq;
1946 unsigned long flags;
1948 raw_spin_lock_irqsave(&ioapic_lock, flags);
1949 if (irq < nr_legacy_irqs()) {
1950 legacy_pic->mask(irq);
1951 if (legacy_pic->irq_pending(irq))
1954 __unmask_ioapic(irqd_cfg(data));
1955 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1961 * Level and edge triggered IO-APIC interrupts need different handling,
1962 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1963 * handled with the level-triggered descriptor, but that one has slightly
1964 * more overhead. Level-triggered interrupts cannot be handled with the
1965 * edge-triggered handler, without risking IRQ storms and other ugly
1969 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
1972 struct irq_pin_list *entry;
1973 u8 vector = cfg->vector;
1975 for_each_irq_pin(entry, cfg->irq_2_pin) {
1981 io_apic_write(apic, 0x11 + pin*2, dest);
1982 reg = io_apic_read(apic, 0x10 + pin*2);
1983 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
1985 io_apic_modify(apic, 0x10 + pin*2, reg);
1989 int native_ioapic_set_affinity(struct irq_data *data,
1990 const struct cpumask *mask,
1993 unsigned int dest, irq = data->irq;
1994 unsigned long flags;
1997 if (!config_enabled(CONFIG_SMP))
2000 raw_spin_lock_irqsave(&ioapic_lock, flags);
2001 ret = apic_set_affinity(data, mask, &dest);
2003 /* Only the high 8 bits are valid. */
2004 dest = SET_APIC_LOGICAL_ID(dest);
2005 __target_IO_APIC_irq(irq, dest, irqd_cfg(data));
2006 ret = IRQ_SET_MASK_OK_NOCOPY;
2008 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2012 atomic_t irq_mis_count;
2014 #ifdef CONFIG_GENERIC_PENDING_IRQ
2015 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2017 struct irq_pin_list *entry;
2018 unsigned long flags;
2020 raw_spin_lock_irqsave(&ioapic_lock, flags);
2021 for_each_irq_pin(entry, cfg->irq_2_pin) {
2026 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2027 /* Is the remote IRR bit set? */
2028 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2029 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2033 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2038 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2040 /* If we are moving the irq we need to mask it */
2041 if (unlikely(irqd_is_setaffinity_pending(data))) {
2048 static inline void ioapic_irqd_unmask(struct irq_data *data,
2049 struct irq_cfg *cfg, bool masked)
2051 if (unlikely(masked)) {
2052 /* Only migrate the irq if the ack has been received.
2054 * On rare occasions the broadcast level triggered ack gets
2055 * delayed going to ioapics, and if we reprogram the
2056 * vector while Remote IRR is still set the irq will never
2059 * To prevent this scenario we read the Remote IRR bit
2060 * of the ioapic. This has two effects.
2061 * - On any sane system the read of the ioapic will
2062 * flush writes (and acks) going to the ioapic from
2064 * - We get to see if the ACK has actually been delivered.
2066 * Based on failed experiments of reprogramming the
2067 * ioapic entry from outside of irq context starting
2068 * with masking the ioapic entry and then polling until
2069 * Remote IRR was clear before reprogramming the
2070 * ioapic I don't trust the Remote IRR bit to be
2071 * completey accurate.
2073 * However there appears to be no other way to plug
2074 * this race, so if the Remote IRR bit is not
2075 * accurate and is causing problems then it is a hardware bug
2076 * and you can go talk to the chipset vendor about it.
2078 if (!io_apic_level_ack_pending(cfg))
2079 irq_move_masked_irq(data);
2084 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2088 static inline void ioapic_irqd_unmask(struct irq_data *data,
2089 struct irq_cfg *cfg, bool masked)
2094 static void ioapic_ack_level(struct irq_data *data)
2096 struct irq_cfg *cfg = irqd_cfg(data);
2101 irq_complete_move(cfg);
2102 masked = ioapic_irqd_mask(data, cfg);
2105 * It appears there is an erratum which affects at least version 0x11
2106 * of I/O APIC (that's the 82093AA and cores integrated into various
2107 * chipsets). Under certain conditions a level-triggered interrupt is
2108 * erroneously delivered as edge-triggered one but the respective IRR
2109 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2110 * message but it will never arrive and further interrupts are blocked
2111 * from the source. The exact reason is so far unknown, but the
2112 * phenomenon was observed when two consecutive interrupt requests
2113 * from a given source get delivered to the same CPU and the source is
2114 * temporarily disabled in between.
2116 * A workaround is to simulate an EOI message manually. We achieve it
2117 * by setting the trigger mode to edge and then to level when the edge
2118 * trigger mode gets detected in the TMR of a local APIC for a
2119 * level-triggered interrupt. We mask the source for the time of the
2120 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2121 * The idea is from Manfred Spraul. --macro
2123 * Also in the case when cpu goes offline, fixup_irqs() will forward
2124 * any unhandled interrupt on the offlined cpu to the new cpu
2125 * destination that is handling the corresponding interrupt. This
2126 * interrupt forwarding is done via IPI's. Hence, in this case also
2127 * level-triggered io-apic interrupt will be seen as an edge
2128 * interrupt in the IRR. And we can't rely on the cpu's EOI
2129 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2130 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2131 * supporting EOI register, we do an explicit EOI to clear the
2132 * remote IRR and on IO-APIC's which don't have an EOI register,
2133 * we use the above logic (mask+edge followed by unmask+level) from
2134 * Manfred Spraul to clear the remote IRR.
2137 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2140 * We must acknowledge the irq before we move it or the acknowledge will
2141 * not propagate properly.
2146 * Tail end of clearing remote IRR bit (either by delivering the EOI
2147 * message via io-apic EOI register write or simulating it using
2148 * mask+edge followed by unnask+level logic) manually when the
2149 * level triggered interrupt is seen as the edge triggered interrupt
2152 if (!(v & (1 << (i & 0x1f)))) {
2153 atomic_inc(&irq_mis_count);
2154 eoi_ioapic_pin(cfg->vector, cfg);
2157 ioapic_irqd_unmask(data, cfg, masked);
2160 static void ioapic_ir_ack_level(struct irq_data *irq_data)
2162 struct mp_chip_data *data = irq_data->chip_data;
2165 * Intr-remapping uses pin number as the virtual vector
2166 * in the RTE. Actual vector is programmed in
2167 * intr-remapping table entry. Hence for the io-apic
2168 * EOI we use the pin number.
2171 eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data));
2174 static int ioapic_set_affinity(struct irq_data *irq_data,
2175 const struct cpumask *mask, bool force)
2177 struct irq_data *parent = irq_data->parent_data;
2178 struct mp_chip_data *data = irq_data->chip_data;
2179 unsigned int dest, irq = irq_data->irq;
2180 struct irq_cfg *cfg;
2181 unsigned long flags;
2184 ret = parent->chip->irq_set_affinity(parent, mask, force);
2185 raw_spin_lock_irqsave(&ioapic_lock, flags);
2186 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
2187 cfg = irqd_cfg(irq_data);
2188 data->entry.dest = cfg->dest_apicid;
2189 data->entry.vector = cfg->vector;
2190 /* Only the high 8 bits are valid. */
2191 dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
2192 __target_IO_APIC_irq(irq, dest, cfg);
2194 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2199 static struct irq_chip ioapic_chip __read_mostly = {
2201 .irq_startup = startup_ioapic_irq,
2202 .irq_mask = mask_ioapic_irq,
2203 .irq_unmask = unmask_ioapic_irq,
2204 .irq_ack = irq_chip_ack_parent,
2205 .irq_eoi = ioapic_ack_level,
2206 .irq_set_affinity = ioapic_set_affinity,
2207 .flags = IRQCHIP_SKIP_SET_WAKE,
2210 static struct irq_chip ioapic_ir_chip __read_mostly = {
2211 .name = "IR-IO-APIC",
2212 .irq_startup = startup_ioapic_irq,
2213 .irq_mask = mask_ioapic_irq,
2214 .irq_unmask = unmask_ioapic_irq,
2215 .irq_ack = irq_chip_ack_parent,
2216 .irq_eoi = ioapic_ir_ack_level,
2217 .irq_set_affinity = ioapic_set_affinity,
2218 .flags = IRQCHIP_SKIP_SET_WAKE,
2221 static inline void init_IO_APIC_traps(void)
2223 struct irq_cfg *cfg;
2226 for_each_active_irq(irq) {
2228 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2230 * Hmm.. We don't have an entry for this,
2231 * so default to an old-fashioned 8259
2232 * interrupt if we can..
2234 if (irq < nr_legacy_irqs())
2235 legacy_pic->make_irq(irq);
2237 /* Strange. Oh, well.. */
2238 irq_set_chip(irq, &no_irq_chip);
2244 * The local APIC irq-chip implementation:
2247 static void mask_lapic_irq(struct irq_data *data)
2251 v = apic_read(APIC_LVT0);
2252 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2255 static void unmask_lapic_irq(struct irq_data *data)
2259 v = apic_read(APIC_LVT0);
2260 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2263 static void ack_lapic_irq(struct irq_data *data)
2268 static struct irq_chip lapic_chip __read_mostly = {
2269 .name = "local-APIC",
2270 .irq_mask = mask_lapic_irq,
2271 .irq_unmask = unmask_lapic_irq,
2272 .irq_ack = ack_lapic_irq,
2275 static void lapic_register_intr(int irq)
2277 irq_clear_status_flags(irq, IRQ_LEVEL);
2278 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2283 * This looks a bit hackish but it's about the only one way of sending
2284 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2285 * not support the ExtINT mode, unfortunately. We need to send these
2286 * cycles as some i82489DX-based boards have glue logic that keeps the
2287 * 8259A interrupt line asserted until INTA. --macro
2289 static inline void __init unlock_ExtINT_logic(void)
2292 struct IO_APIC_route_entry entry0, entry1;
2293 unsigned char save_control, save_freq_select;
2295 pin = find_isa_irq_pin(8, mp_INT);
2300 apic = find_isa_irq_apic(8, mp_INT);
2306 entry0 = ioapic_read_entry(apic, pin);
2307 clear_IO_APIC_pin(apic, pin);
2309 memset(&entry1, 0, sizeof(entry1));
2311 entry1.dest_mode = 0; /* physical delivery */
2312 entry1.mask = 0; /* unmask IRQ now */
2313 entry1.dest = hard_smp_processor_id();
2314 entry1.delivery_mode = dest_ExtINT;
2315 entry1.polarity = entry0.polarity;
2319 ioapic_write_entry(apic, pin, entry1);
2321 save_control = CMOS_READ(RTC_CONTROL);
2322 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2323 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2325 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2330 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2334 CMOS_WRITE(save_control, RTC_CONTROL);
2335 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2336 clear_IO_APIC_pin(apic, pin);
2338 ioapic_write_entry(apic, pin, entry0);
2341 static int disable_timer_pin_1 __initdata;
2342 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2343 static int __init disable_timer_pin_setup(char *arg)
2345 disable_timer_pin_1 = 1;
2348 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2350 static int mp_alloc_timer_irq(int ioapic, int pin)
2353 struct irq_alloc_info info;
2354 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2357 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2358 info.ioapic_id = mpc_ioapic_id(ioapic);
2359 info.ioapic_pin = pin;
2360 mutex_lock(&ioapic_mutex);
2361 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2362 mutex_unlock(&ioapic_mutex);
2369 * This code may look a bit paranoid, but it's supposed to cooperate with
2370 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2371 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2372 * fanatically on his truly buggy board.
2374 * FIXME: really need to revamp this for all platforms.
2376 static inline void __init check_timer(void)
2378 struct irq_cfg *cfg = irq_cfg(0);
2379 int node = cpu_to_node(0);
2380 int apic1, pin1, apic2, pin2;
2381 unsigned long flags;
2384 local_irq_save(flags);
2387 * get/set the timer IRQ vector:
2389 legacy_pic->mask(0);
2392 * As IRQ0 is to be enabled in the 8259A, the virtual
2393 * wire has to be disabled in the local APIC. Also
2394 * timer interrupts need to be acknowledged manually in
2395 * the 8259A for the i82489DX when using the NMI
2396 * watchdog as that APIC treats NMIs as level-triggered.
2397 * The AEOI mode will finish them in the 8259A
2400 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2401 legacy_pic->init(1);
2403 pin1 = find_isa_irq_pin(0, mp_INT);
2404 apic1 = find_isa_irq_apic(0, mp_INT);
2405 pin2 = ioapic_i8259.pin;
2406 apic2 = ioapic_i8259.apic;
2408 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2409 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2410 cfg->vector, apic1, pin1, apic2, pin2);
2413 * Some BIOS writers are clueless and report the ExtINTA
2414 * I/O APIC input from the cascaded 8259A as the timer
2415 * interrupt input. So just in case, if only one pin
2416 * was found above, try it both directly and through the
2420 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2424 } else if (pin2 == -1) {
2430 /* Ok, does IRQ0 through the IOAPIC work? */
2432 mp_alloc_timer_irq(apic1, pin1);
2435 * for edge trigger, it's already unmasked,
2436 * so only need to unmask if it is level-trigger
2437 * do we really have level trigger timer?
2440 idx = find_irq_entry(apic1, pin1, mp_INT);
2441 if (idx != -1 && irq_trigger(idx))
2444 irq_domain_activate_irq(irq_get_irq_data(0));
2445 if (timer_irq_works()) {
2446 if (disable_timer_pin_1 > 0)
2447 clear_IO_APIC_pin(0, pin1);
2450 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2451 local_irq_disable();
2452 clear_IO_APIC_pin(apic1, pin1);
2454 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2455 "8254 timer not connected to IO-APIC\n");
2457 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2458 "(IRQ0) through the 8259A ...\n");
2459 apic_printk(APIC_QUIET, KERN_INFO
2460 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2462 * legacy devices should be connected to IO APIC #0
2464 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2465 irq_domain_activate_irq(irq_get_irq_data(0));
2466 legacy_pic->unmask(0);
2467 if (timer_irq_works()) {
2468 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2472 * Cleanup, just in case ...
2474 local_irq_disable();
2475 legacy_pic->mask(0);
2476 clear_IO_APIC_pin(apic2, pin2);
2477 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2480 apic_printk(APIC_QUIET, KERN_INFO
2481 "...trying to set up timer as Virtual Wire IRQ...\n");
2483 lapic_register_intr(0);
2484 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2485 legacy_pic->unmask(0);
2487 if (timer_irq_works()) {
2488 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2491 local_irq_disable();
2492 legacy_pic->mask(0);
2493 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2494 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2496 apic_printk(APIC_QUIET, KERN_INFO
2497 "...trying to set up timer as ExtINT IRQ...\n");
2499 legacy_pic->init(0);
2500 legacy_pic->make_irq(0);
2501 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2503 unlock_ExtINT_logic();
2505 if (timer_irq_works()) {
2506 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2509 local_irq_disable();
2510 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2511 if (apic_is_x2apic_enabled())
2512 apic_printk(APIC_QUIET, KERN_INFO
2513 "Perhaps problem with the pre-enabled x2apic mode\n"
2514 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2515 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2516 "report. Then try booting with the 'noapic' option.\n");
2518 local_irq_restore(flags);
2522 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2523 * to devices. However there may be an I/O APIC pin available for
2524 * this interrupt regardless. The pin may be left unconnected, but
2525 * typically it will be reused as an ExtINT cascade interrupt for
2526 * the master 8259A. In the MPS case such a pin will normally be
2527 * reported as an ExtINT interrupt in the MP table. With ACPI
2528 * there is no provision for ExtINT interrupts, and in the absence
2529 * of an override it would be treated as an ordinary ISA I/O APIC
2530 * interrupt, that is edge-triggered and unmasked by default. We
2531 * used to do this, but it caused problems on some systems because
2532 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2533 * the same ExtINT cascade interrupt to drive the local APIC of the
2534 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2535 * the I/O APIC in all cases now. No actual device should request
2536 * it anyway. --macro
2538 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2540 static int mp_irqdomain_create(int ioapic)
2543 struct irq_alloc_info info;
2544 struct irq_domain *parent;
2545 int hwirqs = mp_ioapic_pin_count(ioapic);
2546 struct ioapic *ip = &ioapics[ioapic];
2547 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2548 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2550 size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
2551 ip->pin_info = kzalloc(size, GFP_KERNEL);
2555 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2558 init_irq_alloc_info(&info, NULL);
2559 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2560 info.ioapic_id = mpc_ioapic_id(ioapic);
2561 parent = irq_remapping_get_ir_irq_domain(&info);
2563 parent = x86_vector_domain;
2565 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2566 (void *)(long)ioapic);
2567 if (ip->irqdomain) {
2568 ip->irqdomain->parent = parent;
2570 kfree(ip->pin_info);
2571 ip->pin_info = NULL;
2575 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2576 cfg->type == IOAPIC_DOMAIN_STRICT)
2577 ioapic_dynirq_base = max(ioapic_dynirq_base,
2578 gsi_cfg->gsi_end + 1);
2583 static void ioapic_destroy_irqdomain(int idx)
2585 if (ioapics[idx].irqdomain) {
2586 irq_domain_remove(ioapics[idx].irqdomain);
2587 ioapics[idx].irqdomain = NULL;
2589 kfree(ioapics[idx].pin_info);
2590 ioapics[idx].pin_info = NULL;
2593 void __init setup_IO_APIC(void)
2597 if (skip_ioapic_setup || !nr_ioapics)
2600 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2602 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2603 for_each_ioapic(ioapic)
2604 BUG_ON(mp_irqdomain_create(ioapic));
2607 * Set up IO-APIC IRQ routing.
2609 x86_init.mpparse.setup_ioapic_ids();
2612 setup_IO_APIC_irqs();
2613 init_IO_APIC_traps();
2614 if (nr_legacy_irqs())
2617 ioapic_initialized = 1;
2621 * Called after all the initialization is done. If we didn't find any
2622 * APIC bugs then we can allow the modify fast path
2625 static int __init io_apic_bug_finalize(void)
2627 if (sis_apic_bug == -1)
2632 late_initcall(io_apic_bug_finalize);
2634 static void resume_ioapic_id(int ioapic_idx)
2636 unsigned long flags;
2637 union IO_APIC_reg_00 reg_00;
2639 raw_spin_lock_irqsave(&ioapic_lock, flags);
2640 reg_00.raw = io_apic_read(ioapic_idx, 0);
2641 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2642 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2643 io_apic_write(ioapic_idx, 0, reg_00.raw);
2645 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2648 static void ioapic_resume(void)
2652 for_each_ioapic_reverse(ioapic_idx)
2653 resume_ioapic_id(ioapic_idx);
2655 restore_ioapic_entries();
2658 static struct syscore_ops ioapic_syscore_ops = {
2659 .suspend = save_ioapic_entries,
2660 .resume = ioapic_resume,
2663 static int __init ioapic_init_ops(void)
2665 register_syscore_ops(&ioapic_syscore_ops);
2670 device_initcall(ioapic_init_ops);
2673 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
2675 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
2680 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
2682 setup_ioapic_irq(irq, cfg, attr);
2686 static int io_apic_get_redir_entries(int ioapic)
2688 union IO_APIC_reg_01 reg_01;
2689 unsigned long flags;
2691 raw_spin_lock_irqsave(&ioapic_lock, flags);
2692 reg_01.raw = io_apic_read(ioapic, 1);
2693 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2695 /* The register returns the maximum index redir index
2696 * supported, which is one less than the total number of redir
2699 return reg_01.bits.entries + 1;
2702 unsigned int arch_dynirq_lower_bound(unsigned int from)
2705 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2706 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2708 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2711 #ifdef CONFIG_X86_32
2712 static int io_apic_get_unique_id(int ioapic, int apic_id)
2714 union IO_APIC_reg_00 reg_00;
2715 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2717 unsigned long flags;
2721 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2722 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2723 * supports up to 16 on one shared APIC bus.
2725 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2726 * advantage of new APIC bus architecture.
2729 if (physids_empty(apic_id_map))
2730 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2732 raw_spin_lock_irqsave(&ioapic_lock, flags);
2733 reg_00.raw = io_apic_read(ioapic, 0);
2734 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2736 if (apic_id >= get_physical_broadcast()) {
2737 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2738 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2739 apic_id = reg_00.bits.ID;
2743 * Every APIC in a system must have a unique ID or we get lots of nice
2744 * 'stuck on smp_invalidate_needed IPI wait' messages.
2746 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2748 for (i = 0; i < get_physical_broadcast(); i++) {
2749 if (!apic->check_apicid_used(&apic_id_map, i))
2753 if (i == get_physical_broadcast())
2754 panic("Max apic_id exceeded!\n");
2756 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2757 "trying %d\n", ioapic, apic_id, i);
2762 apic->apicid_to_cpu_present(apic_id, &tmp);
2763 physids_or(apic_id_map, apic_id_map, tmp);
2765 if (reg_00.bits.ID != apic_id) {
2766 reg_00.bits.ID = apic_id;
2768 raw_spin_lock_irqsave(&ioapic_lock, flags);
2769 io_apic_write(ioapic, 0, reg_00.raw);
2770 reg_00.raw = io_apic_read(ioapic, 0);
2771 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2774 if (reg_00.bits.ID != apic_id) {
2775 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2781 apic_printk(APIC_VERBOSE, KERN_INFO
2782 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2787 static u8 io_apic_unique_id(int idx, u8 id)
2789 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2790 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2791 return io_apic_get_unique_id(idx, id);
2796 static u8 io_apic_unique_id(int idx, u8 id)
2798 union IO_APIC_reg_00 reg_00;
2799 DECLARE_BITMAP(used, 256);
2800 unsigned long flags;
2804 bitmap_zero(used, 256);
2806 __set_bit(mpc_ioapic_id(i), used);
2808 /* Hand out the requested id if available */
2809 if (!test_bit(id, used))
2813 * Read the current id from the ioapic and keep it if
2816 raw_spin_lock_irqsave(&ioapic_lock, flags);
2817 reg_00.raw = io_apic_read(idx, 0);
2818 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2819 new_id = reg_00.bits.ID;
2820 if (!test_bit(new_id, used)) {
2821 apic_printk(APIC_VERBOSE, KERN_INFO
2822 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2828 * Get the next free id and write it to the ioapic.
2830 new_id = find_first_zero_bit(used, 256);
2831 reg_00.bits.ID = new_id;
2832 raw_spin_lock_irqsave(&ioapic_lock, flags);
2833 io_apic_write(idx, 0, reg_00.raw);
2834 reg_00.raw = io_apic_read(idx, 0);
2835 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2837 BUG_ON(reg_00.bits.ID != new_id);
2843 static int io_apic_get_version(int ioapic)
2845 union IO_APIC_reg_01 reg_01;
2846 unsigned long flags;
2848 raw_spin_lock_irqsave(&ioapic_lock, flags);
2849 reg_01.raw = io_apic_read(ioapic, 1);
2850 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2852 return reg_01.bits.version;
2855 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2857 int ioapic, pin, idx;
2859 if (skip_ioapic_setup)
2862 ioapic = mp_find_ioapic(gsi);
2866 pin = mp_find_ioapic_pin(ioapic, gsi);
2870 idx = find_irq_entry(ioapic, pin, mp_INT);
2874 *trigger = irq_trigger(idx);
2875 *polarity = irq_polarity(idx);
2880 * This function currently is only a helper for the i386 smp boot process where
2881 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2882 * so mask in all cases should simply be apic->target_cpus()
2885 void __init setup_ioapic_dest(void)
2887 int pin, ioapic, irq, irq_entry;
2888 const struct cpumask *mask;
2889 struct irq_data *idata;
2891 if (skip_ioapic_setup == 1)
2894 for_each_ioapic_pin(ioapic, pin) {
2895 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2896 if (irq_entry == -1)
2899 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2900 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2903 idata = irq_get_irq_data(irq);
2906 * Honour affinities which have been set in early boot
2908 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2909 mask = idata->affinity;
2911 mask = apic->target_cpus();
2913 x86_io_apic_ops.set_affinity(idata, mask, false);
2919 #define IOAPIC_RESOURCE_NAME_SIZE 11
2921 static struct resource *ioapic_resources;
2923 static struct resource * __init ioapic_setup_resources(void)
2926 struct resource *res;
2935 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2938 mem = alloc_bootmem(n);
2941 mem += sizeof(struct resource) * num;
2944 for_each_ioapic(i) {
2945 res[num].name = mem;
2946 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2947 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2948 mem += IOAPIC_RESOURCE_NAME_SIZE;
2950 ioapics[i].iomem_res = res;
2953 ioapic_resources = res;
2958 void __init native_io_apic_init_mappings(void)
2960 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2961 struct resource *ioapic_res;
2964 ioapic_res = ioapic_setup_resources();
2965 for_each_ioapic(i) {
2966 if (smp_found_config) {
2967 ioapic_phys = mpc_ioapic_addr(i);
2968 #ifdef CONFIG_X86_32
2971 "WARNING: bogus zero IO-APIC "
2972 "address found in MPTABLE, "
2973 "disabling IO/APIC support!\n");
2974 smp_found_config = 0;
2975 skip_ioapic_setup = 1;
2976 goto fake_ioapic_page;
2980 #ifdef CONFIG_X86_32
2983 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2984 ioapic_phys = __pa(ioapic_phys);
2986 set_fixmap_nocache(idx, ioapic_phys);
2987 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2988 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2992 ioapic_res->start = ioapic_phys;
2993 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2998 void __init ioapic_insert_resources(void)
3001 struct resource *r = ioapic_resources;
3006 "IO APIC resources couldn't be allocated.\n");
3010 for_each_ioapic(i) {
3011 insert_resource(&iomem_resource, r);
3016 int mp_find_ioapic(u32 gsi)
3020 if (nr_ioapics == 0)
3023 /* Find the IOAPIC that manages this GSI. */
3024 for_each_ioapic(i) {
3025 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3026 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
3030 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3034 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3036 struct mp_ioapic_gsi *gsi_cfg;
3038 if (WARN_ON(ioapic < 0))
3041 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3042 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3045 return gsi - gsi_cfg->gsi_base;
3048 static int bad_ioapic_register(int idx)
3050 union IO_APIC_reg_00 reg_00;
3051 union IO_APIC_reg_01 reg_01;
3052 union IO_APIC_reg_02 reg_02;
3054 reg_00.raw = io_apic_read(idx, 0);
3055 reg_01.raw = io_apic_read(idx, 1);
3056 reg_02.raw = io_apic_read(idx, 2);
3058 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3059 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3060 mpc_ioapic_addr(idx));
3067 static int find_free_ioapic_entry(void)
3071 for (idx = 0; idx < MAX_IO_APICS; idx++)
3072 if (ioapics[idx].nr_registers == 0)
3075 return MAX_IO_APICS;
3079 * mp_register_ioapic - Register an IOAPIC device
3080 * @id: hardware IOAPIC ID
3081 * @address: physical address of IOAPIC register area
3082 * @gsi_base: base of GSI associated with the IOAPIC
3083 * @cfg: configuration information for the IOAPIC
3085 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
3086 struct ioapic_domain_cfg *cfg)
3088 bool hotplug = !!ioapic_initialized;
3089 struct mp_ioapic_gsi *gsi_cfg;
3090 int idx, ioapic, entries;
3094 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
3097 for_each_ioapic(ioapic)
3098 if (ioapics[ioapic].mp_config.apicaddr == address) {
3099 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
3104 idx = find_free_ioapic_entry();
3105 if (idx >= MAX_IO_APICS) {
3106 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3111 ioapics[idx].mp_config.type = MP_IOAPIC;
3112 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3113 ioapics[idx].mp_config.apicaddr = address;
3115 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3116 if (bad_ioapic_register(idx)) {
3117 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3121 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
3122 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3125 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3126 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3128 entries = io_apic_get_redir_entries(idx);
3129 gsi_end = gsi_base + entries - 1;
3130 for_each_ioapic(ioapic) {
3131 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3132 if ((gsi_base >= gsi_cfg->gsi_base &&
3133 gsi_base <= gsi_cfg->gsi_end) ||
3134 (gsi_end >= gsi_cfg->gsi_base &&
3135 gsi_end <= gsi_cfg->gsi_end)) {
3136 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
3138 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3139 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3143 gsi_cfg = mp_ioapic_gsi_routing(idx);
3144 gsi_cfg->gsi_base = gsi_base;
3145 gsi_cfg->gsi_end = gsi_end;
3147 ioapics[idx].irqdomain = NULL;
3148 ioapics[idx].irqdomain_cfg = *cfg;
3151 * If mp_register_ioapic() is called during early boot stage when
3152 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
3153 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
3156 if (mp_irqdomain_create(idx)) {
3157 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3160 alloc_ioapic_saved_registers(idx);
3163 if (gsi_cfg->gsi_end >= gsi_top)
3164 gsi_top = gsi_cfg->gsi_end + 1;
3165 if (nr_ioapics <= idx)
3166 nr_ioapics = idx + 1;
3168 /* Set nr_registers to mark entry present */
3169 ioapics[idx].nr_registers = entries;
3171 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3172 idx, mpc_ioapic_id(idx),
3173 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3174 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3179 int mp_unregister_ioapic(u32 gsi_base)
3184 for_each_ioapic(ioapic)
3185 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
3190 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
3194 for_each_pin(ioapic, pin) {
3195 u32 gsi = mp_pin_to_gsi(ioapic, pin);
3196 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
3197 struct mp_chip_data *data;
3200 data = irq_get_chip_data(irq);
3201 if (data && data->count) {
3202 pr_warn("pin%d on IOAPIC%d is still in use.\n",
3209 /* Mark entry not present */
3210 ioapics[ioapic].nr_registers = 0;
3211 ioapic_destroy_irqdomain(ioapic);
3212 free_ioapic_saved_registers(ioapic);
3213 if (ioapics[ioapic].iomem_res)
3214 release_resource(ioapics[ioapic].iomem_res);
3215 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
3216 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
3221 int mp_ioapic_registered(u32 gsi_base)
3225 for_each_ioapic(ioapic)
3226 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
3232 static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr,
3233 int ioapic, int ioapic_pin,
3234 int trigger, int polarity)
3236 irq_attr->ioapic = ioapic;
3237 irq_attr->ioapic_pin = ioapic_pin;
3238 irq_attr->trigger = trigger;
3239 irq_attr->polarity = polarity;
3242 int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
3243 irq_hw_number_t hwirq)
3245 int ioapic = mp_irqdomain_ioapic_idx(domain);
3246 struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
3247 struct io_apic_irq_attr attr;
3249 /* Get default attribute if not set by caller yet */
3251 u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
3253 if (acpi_get_override_irq(gsi, &info->trigger,
3254 &info->polarity) < 0) {
3256 * PCI interrupts are always polarity one level
3262 info->node = NUMA_NO_NODE;
3265 * setup_IO_APIC_irqs() programs all legacy IRQs with default
3266 * trigger and polarity attributes. Don't set the flag for that
3267 * case so the first legacy IRQ user could reprogram the pin
3268 * with real trigger and polarity attributes.
3270 if (virq >= nr_legacy_irqs() || info->count)
3273 set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
3276 return io_apic_setup_irq_pin(virq, info->node, &attr);
3279 void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq)
3281 struct irq_data *data = irq_get_irq_data(virq);
3282 struct irq_cfg *cfg = irq_cfg(virq);
3283 int ioapic = mp_irqdomain_ioapic_idx(domain);
3284 int pin = (int)data->hwirq;
3286 ioapic_mask_entry(ioapic, pin);
3287 __remove_pin_from_irq(cfg, ioapic, pin);
3288 WARN_ON(!list_empty(&cfg->irq_2_pin));
3289 arch_teardown_hwirq(virq);
3292 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
3293 struct irq_alloc_info *info)
3295 if (info && info->ioapic_valid) {
3296 data->trigger = info->ioapic_trigger;
3297 data->polarity = info->ioapic_polarity;
3298 } else if (acpi_get_override_irq(gsi, &data->trigger,
3299 &data->polarity) < 0) {
3300 /* PCI interrupts are always polarity one level triggered. */
3306 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
3307 struct IO_APIC_route_entry *entry)
3309 memset(entry, 0, sizeof(*entry));
3310 entry->delivery_mode = apic->irq_delivery_mode;
3311 entry->dest_mode = apic->irq_dest_mode;
3312 entry->dest = cfg->dest_apicid;
3313 entry->vector = cfg->vector;
3314 entry->mask = 0; /* enable IRQ */
3315 entry->trigger = data->trigger;
3316 entry->polarity = data->polarity;
3318 * Mask level triggered irqs.
3319 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
3325 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
3326 unsigned int nr_irqs, void *arg)
3328 int ret, ioapic, pin;
3329 struct irq_cfg *cfg;
3330 struct irq_data *irq_data;
3331 struct mp_chip_data *data;
3332 struct irq_alloc_info *info = arg;
3334 if (!info || nr_irqs > 1)
3336 irq_data = irq_domain_get_irq_data(domain, virq);
3340 ioapic = mp_irqdomain_ioapic_idx(domain);
3341 pin = info->ioapic_pin;
3342 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3345 data = kzalloc(sizeof(*data), GFP_KERNEL);
3349 info->ioapic_entry = &data->entry;
3350 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3356 irq_data->hwirq = info->ioapic_pin;
3357 irq_data->chip = (domain->parent == x86_vector_domain) ?
3358 &ioapic_chip : &ioapic_ir_chip;
3359 irq_data->chip_data = data;
3360 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3362 cfg = irqd_cfg(irq_data);
3363 add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin);
3364 if (info->ioapic_entry)
3365 mp_setup_entry(cfg, data, info->ioapic_entry);
3366 mp_register_handler(virq, data->trigger);
3367 if (virq < nr_legacy_irqs())
3368 legacy_pic->mask(virq);
3370 apic_printk(APIC_VERBOSE, KERN_DEBUG
3371 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3372 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3373 virq, data->trigger, data->polarity, cfg->dest_apicid);
3378 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3379 unsigned int nr_irqs)
3381 struct irq_cfg *cfg = irq_cfg(virq);
3382 struct irq_data *irq_data;
3384 BUG_ON(nr_irqs != 1);
3385 irq_data = irq_domain_get_irq_data(domain, virq);
3386 if (irq_data && irq_data->chip_data) {
3387 __remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain),
3388 (int)irq_data->hwirq);
3389 WARN_ON(!list_empty(&cfg->irq_2_pin));
3390 kfree(irq_data->chip_data);
3392 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3395 void mp_irqdomain_activate(struct irq_domain *domain,
3396 struct irq_data *irq_data)
3398 unsigned long flags;
3399 struct irq_pin_list *entry;
3400 struct mp_chip_data *data = irq_data->chip_data;
3401 struct irq_cfg *cfg = irqd_cfg(irq_data);
3403 raw_spin_lock_irqsave(&ioapic_lock, flags);
3404 for_each_irq_pin(entry, cfg->irq_2_pin)
3405 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
3406 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3409 void mp_irqdomain_deactivate(struct irq_domain *domain,
3410 struct irq_data *irq_data)
3412 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3413 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3414 (int)irq_data->hwirq);
3417 int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
3421 struct mp_pin_info *info;
3423 ioapic = mp_find_ioapic(gsi);
3427 pin = mp_find_ioapic_pin(ioapic, gsi);
3428 info = mp_pin_info(ioapic, pin);
3429 trigger = trigger ? 1 : 0;
3430 polarity = polarity ? 1 : 0;
3432 mutex_lock(&ioapic_mutex);
3434 info->trigger = trigger;
3435 info->polarity = polarity;
3438 } else if (info->trigger != trigger || info->polarity != polarity) {
3441 mutex_unlock(&ioapic_mutex);
3446 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3448 return (int)(long)domain->host_data;