2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/freezer.h>
36 #include <linux/kthread.h>
37 #include <linux/jiffies.h> /* time_after() */
38 #include <linux/slab.h>
39 #include <linux/bootmem.h>
46 #include <asm/proto.h>
49 #include <asm/timer.h>
50 #include <asm/i8259.h>
51 #include <asm/setup.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/hw_irq.h>
57 #define for_each_ioapic(idx) \
58 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
59 #define for_each_ioapic_reverse(idx) \
60 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
61 #define for_each_pin(idx, pin) \
62 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
63 #define for_each_ioapic_pin(idx, pin) \
64 for_each_ioapic((idx)) \
65 for_each_pin((idx), (pin))
67 #define for_each_irq_pin(entry, head) \
68 list_for_each_entry(entry, &head, list)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_MUTEX(ioapic_mutex);
78 static unsigned int ioapic_dynirq_base;
79 static int ioapic_initialized;
82 struct IO_APIC_route_entry entry;
89 static struct ioapic {
91 * # of IRQ routing registers
95 * Saved state during suspend/resume, or while enabling intr-remap.
97 struct IO_APIC_route_entry *saved_registers;
99 struct mpc_ioapic mp_config;
100 /* IO APIC gsi routing info */
101 struct mp_ioapic_gsi gsi_config;
102 struct ioapic_domain_cfg irqdomain_cfg;
103 struct irq_domain *irqdomain;
104 struct resource *iomem_res;
105 } ioapics[MAX_IO_APICS];
107 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
109 int mpc_ioapic_id(int ioapic_idx)
111 return ioapics[ioapic_idx].mp_config.apicid;
114 unsigned int mpc_ioapic_addr(int ioapic_idx)
116 return ioapics[ioapic_idx].mp_config.apicaddr;
119 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
121 return &ioapics[ioapic_idx].gsi_config;
124 static inline int mp_ioapic_pin_count(int ioapic)
126 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
128 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
131 u32 mp_pin_to_gsi(int ioapic, int pin)
133 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
136 static inline bool mp_is_legacy_irq(int irq)
138 return irq >= 0 && irq < nr_legacy_irqs();
142 * Initialize all legacy IRQs and all pins on the first IOAPIC
143 * if we have legacy interrupt controller. Kernel boot option "pirq="
144 * may rely on non-legacy pins on the first IOAPIC.
146 static inline int mp_init_irq_at_boot(int ioapic, int irq)
148 if (!nr_legacy_irqs())
151 return ioapic == 0 || mp_is_legacy_irq(irq);
154 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
156 return ioapics[ioapic].irqdomain;
161 /* The one past the highest gsi number used */
164 /* MP IRQ source entries */
165 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
167 /* # of MP IRQ source entries */
171 int mp_bus_id_to_type[MAX_MP_BUSSES];
174 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
176 int skip_ioapic_setup;
179 * disable_ioapic_support() - disables ioapic support at runtime
181 void disable_ioapic_support(void)
185 noioapicreroute = -1;
187 skip_ioapic_setup = 1;
190 static int __init parse_noapic(char *str)
192 /* disable IO-APIC */
193 disable_ioapic_support();
196 early_param("noapic", parse_noapic);
198 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
199 void mp_save_irq(struct mpc_intsrc *m)
203 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
204 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
206 m->srcbusirq, m->dstapic, m->dstirq);
208 for (i = 0; i < mp_irq_entries; i++) {
209 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
213 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
214 if (++mp_irq_entries == MAX_IRQ_SOURCES)
215 panic("Max # of irq sources exceeded!!\n");
218 struct irq_pin_list {
219 struct list_head list;
223 static struct irq_pin_list *alloc_irq_pin_list(int node)
225 return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
228 static void alloc_ioapic_saved_registers(int idx)
232 if (ioapics[idx].saved_registers)
235 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
236 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
237 if (!ioapics[idx].saved_registers)
238 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
241 static void free_ioapic_saved_registers(int idx)
243 kfree(ioapics[idx].saved_registers);
244 ioapics[idx].saved_registers = NULL;
247 int __init arch_early_ioapic_init(void)
251 if (!nr_legacy_irqs())
255 alloc_ioapic_saved_registers(i);
262 unsigned int unused[3];
264 unsigned int unused2[11];
268 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
270 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
271 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
274 void io_apic_eoi(unsigned int apic, unsigned int vector)
276 struct io_apic __iomem *io_apic = io_apic_base(apic);
277 writel(vector, &io_apic->eoi);
280 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
282 struct io_apic __iomem *io_apic = io_apic_base(apic);
283 writel(reg, &io_apic->index);
284 return readl(&io_apic->data);
287 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
289 struct io_apic __iomem *io_apic = io_apic_base(apic);
291 writel(reg, &io_apic->index);
292 writel(value, &io_apic->data);
296 * Re-write a value: to be used for read-modify-write
297 * cycles where the read already set up the index register.
299 * Older SiS APIC requires we rewrite the index register
301 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
303 struct io_apic __iomem *io_apic = io_apic_base(apic);
306 writel(reg, &io_apic->index);
307 writel(value, &io_apic->data);
311 struct { u32 w1, w2; };
312 struct IO_APIC_route_entry entry;
315 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
317 union entry_union eu;
319 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
320 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
325 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
327 union entry_union eu;
330 raw_spin_lock_irqsave(&ioapic_lock, flags);
331 eu.entry = __ioapic_read_entry(apic, pin);
332 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
338 * When we write a new IO APIC routing entry, we need to write the high
339 * word first! If the mask bit in the low word is clear, we will enable
340 * the interrupt, and we need to make sure the entry is fully populated
341 * before that happens.
343 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
345 union entry_union eu = {{0, 0}};
348 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
349 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
352 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
356 raw_spin_lock_irqsave(&ioapic_lock, flags);
357 __ioapic_write_entry(apic, pin, e);
358 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
362 * When we mask an IO APIC routing entry, we need to write the low
363 * word first, in order to set the mask bit before we change the
366 static void ioapic_mask_entry(int apic, int pin)
369 union entry_union eu = { .entry.mask = 1 };
371 raw_spin_lock_irqsave(&ioapic_lock, flags);
372 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
373 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
374 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
378 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
379 * shared ISA-space IRQs, so we have to support them. We are super
380 * fast in the common case, and fast for shared ISA-space IRQs.
382 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
384 struct irq_pin_list *entry;
386 /* don't allow duplicates */
387 for_each_irq_pin(entry, cfg->irq_2_pin)
388 if (entry->apic == apic && entry->pin == pin)
391 entry = alloc_irq_pin_list(node);
393 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
400 list_add_tail(&entry->list, &cfg->irq_2_pin);
404 static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
406 struct irq_pin_list *tmp, *entry;
408 list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list)
409 if (entry->apic == apic && entry->pin == pin) {
410 list_del(&entry->list);
416 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
418 if (__add_pin_to_irq_node(cfg, node, apic, pin))
419 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
423 * Reroute an IRQ to a different pin.
425 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
426 int oldapic, int oldpin,
427 int newapic, int newpin)
429 struct irq_pin_list *entry;
431 for_each_irq_pin(entry, cfg->irq_2_pin) {
432 if (entry->apic == oldapic && entry->pin == oldpin) {
433 entry->apic = newapic;
435 /* every one is different, right? */
440 /* old apic/pin didn't exist, so just add new ones */
441 add_pin_to_irq_node(cfg, node, newapic, newpin);
444 static void __io_apic_modify_irq(struct irq_pin_list *entry,
445 int mask_and, int mask_or,
446 void (*final)(struct irq_pin_list *entry))
448 unsigned int reg, pin;
451 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
454 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
459 static void io_apic_modify_irq(struct irq_cfg *cfg,
460 int mask_and, int mask_or,
461 void (*final)(struct irq_pin_list *entry))
463 struct irq_pin_list *entry;
465 for_each_irq_pin(entry, cfg->irq_2_pin)
466 __io_apic_modify_irq(entry, mask_and, mask_or, final);
469 static void io_apic_sync(struct irq_pin_list *entry)
472 * Synchronize the IO-APIC and the CPU by doing
473 * a dummy read from the IO-APIC
475 struct io_apic __iomem *io_apic;
477 io_apic = io_apic_base(entry->apic);
478 readl(&io_apic->data);
481 static void mask_ioapic(struct irq_cfg *cfg)
485 raw_spin_lock_irqsave(&ioapic_lock, flags);
486 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
487 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
490 static void mask_ioapic_irq(struct irq_data *data)
492 mask_ioapic(irqd_cfg(data));
495 static void __unmask_ioapic(struct irq_cfg *cfg)
497 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
500 static void unmask_ioapic(struct irq_cfg *cfg)
504 raw_spin_lock_irqsave(&ioapic_lock, flags);
505 __unmask_ioapic(cfg);
506 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
509 static void unmask_ioapic_irq(struct irq_data *data)
511 unmask_ioapic(irqd_cfg(data));
515 * IO-APIC versions below 0x20 don't support EOI register.
516 * For the record, here is the information about various versions:
518 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
519 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
522 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
523 * version as 0x2. This is an error with documentation and these ICH chips
524 * use io-apic's of version 0x20.
526 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
527 * Otherwise, we simulate the EOI message manually by changing the trigger
528 * mode to edge and then back to level, with RTE being masked during this.
530 void native_eoi_ioapic_pin(int apic, int pin, int vector)
532 if (mpc_ioapic_ver(apic) >= 0x20) {
533 io_apic_eoi(apic, vector);
535 struct IO_APIC_route_entry entry, entry1;
537 entry = entry1 = __ioapic_read_entry(apic, pin);
540 * Mask the entry and change the trigger mode to edge.
543 entry1.trigger = IOAPIC_EDGE;
545 __ioapic_write_entry(apic, pin, entry1);
548 * Restore the previous level triggered entry.
550 __ioapic_write_entry(apic, pin, entry);
554 void eoi_ioapic_pin(int vector, struct irq_cfg *cfg)
557 struct irq_pin_list *entry;
559 raw_spin_lock_irqsave(&ioapic_lock, flags);
560 for_each_irq_pin(entry, cfg->irq_2_pin)
561 native_eoi_ioapic_pin(entry->apic, entry->pin, vector);
562 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
565 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
567 struct irq_pin_list *entry;
570 raw_spin_lock_irqsave(&ioapic_lock, flags);
571 for_each_irq_pin(entry, cfg->irq_2_pin)
572 x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin,
574 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
577 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
579 struct IO_APIC_route_entry entry;
581 /* Check delivery_mode to be sure we're not clearing an SMI pin */
582 entry = ioapic_read_entry(apic, pin);
583 if (entry.delivery_mode == dest_SMI)
587 * Make sure the entry is masked and re-read the contents to check
588 * if it is a level triggered pin and if the remote-IRR is set.
592 ioapic_write_entry(apic, pin, entry);
593 entry = ioapic_read_entry(apic, pin);
600 * Make sure the trigger mode is set to level. Explicit EOI
601 * doesn't clear the remote-IRR if the trigger mode is not
604 if (!entry.trigger) {
605 entry.trigger = IOAPIC_LEVEL;
606 ioapic_write_entry(apic, pin, entry);
608 raw_spin_lock_irqsave(&ioapic_lock, flags);
609 native_eoi_ioapic_pin(apic, pin, entry.vector);
610 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
614 * Clear the rest of the bits in the IO-APIC RTE except for the mask
617 ioapic_mask_entry(apic, pin);
618 entry = ioapic_read_entry(apic, pin);
620 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
621 mpc_ioapic_id(apic), pin);
624 static void clear_IO_APIC (void)
628 for_each_ioapic_pin(apic, pin)
629 clear_IO_APIC_pin(apic, pin);
634 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
635 * specific CPU-side IRQs.
639 static int pirq_entries[MAX_PIRQS] = {
640 [0 ... MAX_PIRQS - 1] = -1
643 static int __init ioapic_pirq_setup(char *str)
646 int ints[MAX_PIRQS+1];
648 get_options(str, ARRAY_SIZE(ints), ints);
650 apic_printk(APIC_VERBOSE, KERN_INFO
651 "PIRQ redirection, working around broken MP-BIOS.\n");
653 if (ints[0] < MAX_PIRQS)
656 for (i = 0; i < max; i++) {
657 apic_printk(APIC_VERBOSE, KERN_DEBUG
658 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
660 * PIRQs are mapped upside down, usually.
662 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
667 __setup("pirq=", ioapic_pirq_setup);
668 #endif /* CONFIG_X86_32 */
671 * Saves all the IO-APIC RTE's
673 int save_ioapic_entries(void)
678 for_each_ioapic(apic) {
679 if (!ioapics[apic].saved_registers) {
684 for_each_pin(apic, pin)
685 ioapics[apic].saved_registers[pin] =
686 ioapic_read_entry(apic, pin);
693 * Mask all IO APIC entries.
695 void mask_ioapic_entries(void)
699 for_each_ioapic(apic) {
700 if (!ioapics[apic].saved_registers)
703 for_each_pin(apic, pin) {
704 struct IO_APIC_route_entry entry;
706 entry = ioapics[apic].saved_registers[pin];
709 ioapic_write_entry(apic, pin, entry);
716 * Restore IO APIC entries which was saved in the ioapic structure.
718 int restore_ioapic_entries(void)
722 for_each_ioapic(apic) {
723 if (!ioapics[apic].saved_registers)
726 for_each_pin(apic, pin)
727 ioapic_write_entry(apic, pin,
728 ioapics[apic].saved_registers[pin]);
734 * Find the IRQ entry number of a certain pin.
736 static int find_irq_entry(int ioapic_idx, int pin, int type)
740 for (i = 0; i < mp_irq_entries; i++)
741 if (mp_irqs[i].irqtype == type &&
742 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
743 mp_irqs[i].dstapic == MP_APIC_ALL) &&
744 mp_irqs[i].dstirq == pin)
751 * Find the pin to which IRQ[irq] (ISA) is connected
753 static int __init find_isa_irq_pin(int irq, int type)
757 for (i = 0; i < mp_irq_entries; i++) {
758 int lbus = mp_irqs[i].srcbus;
760 if (test_bit(lbus, mp_bus_not_pci) &&
761 (mp_irqs[i].irqtype == type) &&
762 (mp_irqs[i].srcbusirq == irq))
764 return mp_irqs[i].dstirq;
769 static int __init find_isa_irq_apic(int irq, int type)
773 for (i = 0; i < mp_irq_entries; i++) {
774 int lbus = mp_irqs[i].srcbus;
776 if (test_bit(lbus, mp_bus_not_pci) &&
777 (mp_irqs[i].irqtype == type) &&
778 (mp_irqs[i].srcbusirq == irq))
782 if (i < mp_irq_entries) {
785 for_each_ioapic(ioapic_idx)
786 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
795 * EISA Edge/Level control register, ELCR
797 static int EISA_ELCR(unsigned int irq)
799 if (irq < nr_legacy_irqs()) {
800 unsigned int port = 0x4d0 + (irq >> 3);
801 return (inb(port) >> (irq & 7)) & 1;
803 apic_printk(APIC_VERBOSE, KERN_INFO
804 "Broken MPtable reports ISA irq %d\n", irq);
810 /* ISA interrupts are always polarity zero edge triggered,
811 * when listed as conforming in the MP table. */
813 #define default_ISA_trigger(idx) (0)
814 #define default_ISA_polarity(idx) (0)
816 /* EISA interrupts are always polarity zero and can be edge or level
817 * trigger depending on the ELCR value. If an interrupt is listed as
818 * EISA conforming in the MP table, that means its trigger type must
819 * be read in from the ELCR */
821 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
822 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
824 /* PCI interrupts are always polarity one level triggered,
825 * when listed as conforming in the MP table. */
827 #define default_PCI_trigger(idx) (1)
828 #define default_PCI_polarity(idx) (1)
830 static int irq_polarity(int idx)
832 int bus = mp_irqs[idx].srcbus;
836 * Determine IRQ line polarity (high active or low active):
838 switch (mp_irqs[idx].irqflag & 3)
840 case 0: /* conforms, ie. bus-type dependent polarity */
841 if (test_bit(bus, mp_bus_not_pci))
842 polarity = default_ISA_polarity(idx);
844 polarity = default_PCI_polarity(idx);
846 case 1: /* high active */
851 case 2: /* reserved */
853 pr_warn("broken BIOS!!\n");
857 case 3: /* low active */
862 default: /* invalid */
864 pr_warn("broken BIOS!!\n");
872 static int irq_trigger(int idx)
874 int bus = mp_irqs[idx].srcbus;
878 * Determine IRQ trigger mode (edge or level sensitive):
880 switch ((mp_irqs[idx].irqflag>>2) & 3)
882 case 0: /* conforms, ie. bus-type dependent */
883 if (test_bit(bus, mp_bus_not_pci))
884 trigger = default_ISA_trigger(idx);
886 trigger = default_PCI_trigger(idx);
888 switch (mp_bus_id_to_type[bus]) {
889 case MP_BUS_ISA: /* ISA pin */
891 /* set before the switch */
894 case MP_BUS_EISA: /* EISA pin */
896 trigger = default_EISA_trigger(idx);
899 case MP_BUS_PCI: /* PCI pin */
901 /* set before the switch */
906 pr_warn("broken BIOS!!\n");
918 case 2: /* reserved */
920 pr_warn("broken BIOS!!\n");
929 default: /* invalid */
931 pr_warn("broken BIOS!!\n");
939 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
940 int trigger, int polarity)
942 init_irq_alloc_info(info, NULL);
943 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
944 info->ioapic_node = node;
945 info->ioapic_trigger = trigger;
946 info->ioapic_polarity = polarity;
947 info->ioapic_valid = 1;
951 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
954 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
955 struct irq_alloc_info *src,
956 u32 gsi, int ioapic_idx, int pin)
958 int trigger, polarity;
960 copy_irq_alloc_info(dst, src);
961 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
962 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
963 dst->ioapic_pin = pin;
964 dst->ioapic_valid = 1;
965 if (src && src->ioapic_valid) {
966 dst->ioapic_node = src->ioapic_node;
967 dst->ioapic_trigger = src->ioapic_trigger;
968 dst->ioapic_polarity = src->ioapic_polarity;
970 dst->ioapic_node = NUMA_NO_NODE;
971 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
972 dst->ioapic_trigger = trigger;
973 dst->ioapic_polarity = polarity;
976 * PCI interrupts are always polarity one level
979 dst->ioapic_trigger = 1;
980 dst->ioapic_polarity = 1;
985 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
987 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
990 static void mp_register_handler(unsigned int irq, unsigned long trigger)
992 irq_flow_handler_t hdl;
996 irq_set_status_flags(irq, IRQ_LEVEL);
999 irq_clear_status_flags(irq, IRQ_LEVEL);
1003 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1004 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
1007 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
1009 struct mp_chip_data *data = irq_get_chip_data(irq);
1012 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
1013 * and polarity attirbutes. So allow the first user to reprogram the
1014 * pin with real trigger and polarity attributes.
1016 if (irq < nr_legacy_irqs() && data->count == 1) {
1017 if (info->ioapic_trigger != data->trigger)
1018 mp_register_handler(irq, data->trigger);
1019 data->entry.trigger = data->trigger = info->ioapic_trigger;
1020 data->entry.polarity = data->polarity = info->ioapic_polarity;
1023 return data->trigger == info->ioapic_trigger &&
1024 data->polarity == info->ioapic_polarity;
1027 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
1028 struct irq_alloc_info *info)
1030 bool legacy = false;
1032 int type = ioapics[ioapic].irqdomain_cfg.type;
1035 case IOAPIC_DOMAIN_LEGACY:
1037 * Dynamically allocate IRQ number for non-ISA IRQs in the first
1038 * 16 GSIs on some weird platforms.
1040 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
1042 legacy = mp_is_legacy_irq(irq);
1044 case IOAPIC_DOMAIN_STRICT:
1047 case IOAPIC_DOMAIN_DYNAMIC:
1050 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1054 return __irq_domain_alloc_irqs(domain, irq, 1,
1055 ioapic_alloc_attr_node(info),
1060 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
1061 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
1062 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
1063 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1064 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
1065 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
1066 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
1067 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
1069 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
1070 int irq, int ioapic, int pin,
1071 struct irq_alloc_info *info)
1073 struct mp_chip_data *data;
1074 struct irq_data *irq_data = irq_get_irq_data(irq);
1075 int node = ioapic_alloc_attr_node(info);
1078 * Legacy ISA IRQ has already been allocated, just add pin to
1079 * the pin list assoicated with this IRQ and program the IOAPIC
1080 * entry. The IOAPIC entry
1082 if (irq_data && irq_data->parent_data) {
1083 struct irq_cfg *cfg = irqd_cfg(irq_data);
1085 if (!mp_check_pin_attr(irq, info))
1087 if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin))
1090 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
1092 irq_data = irq_domain_get_irq_data(domain, irq);
1093 data = irq_data->chip_data;
1094 data->isa_irq = true;
1101 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1102 unsigned int flags, struct irq_alloc_info *info)
1105 bool legacy = false;
1106 struct irq_alloc_info tmp;
1107 struct mp_chip_data *data;
1108 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1113 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1114 irq = mp_irqs[idx].srcbusirq;
1115 legacy = mp_is_legacy_irq(irq);
1118 mutex_lock(&ioapic_mutex);
1119 if (!(flags & IOAPIC_MAP_ALLOC)) {
1121 irq = irq_find_mapping(domain, pin);
1126 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1128 irq = alloc_isa_irq_from_domain(domain, irq,
1130 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1131 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1132 else if (!mp_check_pin_attr(irq, &tmp))
1135 data = irq_get_chip_data(irq);
1139 mutex_unlock(&ioapic_mutex);
1144 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1146 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1149 * Debugging check, we are in big trouble if this message pops up!
1151 if (mp_irqs[idx].dstirq != pin)
1152 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1154 #ifdef CONFIG_X86_32
1156 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1158 if ((pin >= 16) && (pin <= 23)) {
1159 if (pirq_entries[pin-16] != -1) {
1160 if (!pirq_entries[pin-16]) {
1161 apic_printk(APIC_VERBOSE, KERN_DEBUG
1162 "disabling PIRQ%d\n", pin-16);
1164 int irq = pirq_entries[pin-16];
1165 apic_printk(APIC_VERBOSE, KERN_DEBUG
1166 "using PIRQ%d -> IRQ %d\n",
1174 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1177 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
1178 struct irq_alloc_info *info)
1180 int ioapic, pin, idx;
1182 ioapic = mp_find_ioapic(gsi);
1186 pin = mp_find_ioapic_pin(ioapic, gsi);
1187 idx = find_irq_entry(ioapic, pin, mp_INT);
1188 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1191 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1194 void mp_unmap_irq(int irq)
1196 struct irq_data *irq_data = irq_get_irq_data(irq);
1197 struct mp_chip_data *data;
1199 if (!irq_data || !irq_data->domain)
1202 data = irq_data->chip_data;
1203 if (!data || data->isa_irq)
1206 mutex_lock(&ioapic_mutex);
1207 if (--data->count == 0)
1208 irq_domain_free_irqs(irq, 1);
1209 mutex_unlock(&ioapic_mutex);
1213 * Find a specific PCI IRQ entry.
1214 * Not an __init, possibly needed by modules
1216 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1218 int irq, i, best_ioapic = -1, best_idx = -1;
1220 apic_printk(APIC_DEBUG,
1221 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1223 if (test_bit(bus, mp_bus_not_pci)) {
1224 apic_printk(APIC_VERBOSE,
1225 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1229 for (i = 0; i < mp_irq_entries; i++) {
1230 int lbus = mp_irqs[i].srcbus;
1231 int ioapic_idx, found = 0;
1233 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1234 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1237 for_each_ioapic(ioapic_idx)
1238 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1239 mp_irqs[i].dstapic == MP_APIC_ALL) {
1247 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1248 if (irq > 0 && !IO_APIC_IRQ(irq))
1251 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1253 best_ioapic = ioapic_idx;
1258 * Use the first all-but-pin matching entry as a
1259 * best-guess fuzzy result for broken mptables.
1263 best_ioapic = ioapic_idx;
1270 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1273 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1275 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1277 #ifdef CONFIG_X86_32
1278 static inline int IO_APIC_irq_trigger(int irq)
1282 for_each_ioapic_pin(apic, pin) {
1283 idx = find_irq_entry(apic, pin, mp_INT);
1284 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1285 return irq_trigger(idx);
1288 * nonexistent IRQs are edge default
1293 static inline int IO_APIC_irq_trigger(int irq)
1299 static void __init setup_IO_APIC_irqs(void)
1301 unsigned int ioapic, pin;
1304 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1306 for_each_ioapic_pin(ioapic, pin) {
1307 idx = find_irq_entry(ioapic, pin, mp_INT);
1309 apic_printk(APIC_VERBOSE,
1310 KERN_DEBUG " apic %d pin %d not connected\n",
1311 mpc_ioapic_id(ioapic), pin);
1313 pin_2_irq(idx, ioapic, pin,
1314 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1318 void ioapic_zap_locks(void)
1320 raw_spin_lock_init(&ioapic_lock);
1323 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1327 struct IO_APIC_route_entry entry;
1328 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1330 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1331 for (i = 0; i <= nr_entries; i++) {
1332 entry = ioapic_read_entry(apic, i);
1333 snprintf(buf, sizeof(buf),
1334 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1335 i, entry.mask ? "disabled" : "enabled ",
1336 entry.trigger ? "level" : "edge ",
1337 entry.polarity ? "low " : "high",
1338 entry.vector, entry.irr, entry.delivery_status);
1339 if (ir_entry->format)
1340 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1341 buf, (ir_entry->index << 15) | ir_entry->index,
1344 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1345 buf, entry.dest_mode ? "logical " : "physical",
1346 entry.dest, entry.delivery_mode);
1350 static void __init print_IO_APIC(int ioapic_idx)
1352 union IO_APIC_reg_00 reg_00;
1353 union IO_APIC_reg_01 reg_01;
1354 union IO_APIC_reg_02 reg_02;
1355 union IO_APIC_reg_03 reg_03;
1356 unsigned long flags;
1358 raw_spin_lock_irqsave(&ioapic_lock, flags);
1359 reg_00.raw = io_apic_read(ioapic_idx, 0);
1360 reg_01.raw = io_apic_read(ioapic_idx, 1);
1361 if (reg_01.bits.version >= 0x10)
1362 reg_02.raw = io_apic_read(ioapic_idx, 2);
1363 if (reg_01.bits.version >= 0x20)
1364 reg_03.raw = io_apic_read(ioapic_idx, 3);
1365 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1367 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1368 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1369 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1370 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1371 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1373 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1374 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1375 reg_01.bits.entries);
1377 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1378 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1379 reg_01.bits.version);
1382 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1383 * but the value of reg_02 is read as the previous read register
1384 * value, so ignore it if reg_02 == reg_01.
1386 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1387 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1388 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1392 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1393 * or reg_03, but the value of reg_0[23] is read as the previous read
1394 * register value, so ignore it if reg_03 == reg_0[12].
1396 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1397 reg_03.raw != reg_01.raw) {
1398 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1399 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1402 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1403 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1406 void __init print_IO_APICs(void)
1409 struct irq_cfg *cfg;
1411 struct irq_chip *chip;
1413 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1414 for_each_ioapic(ioapic_idx)
1415 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1416 mpc_ioapic_id(ioapic_idx),
1417 ioapics[ioapic_idx].nr_registers);
1420 * We are a bit conservative about what we expect. We have to
1421 * know about every hardware change ASAP.
1423 printk(KERN_INFO "testing the IO APIC.......................\n");
1425 for_each_ioapic(ioapic_idx)
1426 print_IO_APIC(ioapic_idx);
1428 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1429 for_each_active_irq(irq) {
1430 struct irq_pin_list *entry;
1432 chip = irq_get_chip(irq);
1433 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1439 if (list_empty(&cfg->irq_2_pin))
1441 printk(KERN_DEBUG "IRQ%d ", irq);
1442 for_each_irq_pin(entry, cfg->irq_2_pin)
1443 pr_cont("-> %d:%d", entry->apic, entry->pin);
1447 printk(KERN_INFO ".................................... done.\n");
1450 /* Where if anywhere is the i8259 connect in external int mode */
1451 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1453 void __init enable_IO_APIC(void)
1455 int i8259_apic, i8259_pin;
1458 if (skip_ioapic_setup)
1461 if (!nr_legacy_irqs() || !nr_ioapics)
1464 for_each_ioapic_pin(apic, pin) {
1465 /* See if any of the pins is in ExtINT mode */
1466 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1468 /* If the interrupt line is enabled and in ExtInt mode
1469 * I have found the pin where the i8259 is connected.
1471 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1472 ioapic_i8259.apic = apic;
1473 ioapic_i8259.pin = pin;
1478 /* Look to see what if the MP table has reported the ExtINT */
1479 /* If we could not find the appropriate pin by looking at the ioapic
1480 * the i8259 probably is not connected the ioapic but give the
1481 * mptable a chance anyway.
1483 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1484 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1485 /* Trust the MP table if nothing is setup in the hardware */
1486 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1487 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1488 ioapic_i8259.pin = i8259_pin;
1489 ioapic_i8259.apic = i8259_apic;
1491 /* Complain if the MP table and the hardware disagree */
1492 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1493 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1495 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1499 * Do not trust the IO-APIC being empty at bootup
1504 void native_disable_io_apic(void)
1507 * If the i8259 is routed through an IOAPIC
1508 * Put that IOAPIC in virtual wire mode
1509 * so legacy interrupts can be delivered.
1511 if (ioapic_i8259.pin != -1) {
1512 struct IO_APIC_route_entry entry;
1514 memset(&entry, 0, sizeof(entry));
1515 entry.mask = 0; /* Enabled */
1516 entry.trigger = 0; /* Edge */
1518 entry.polarity = 0; /* High */
1519 entry.delivery_status = 0;
1520 entry.dest_mode = 0; /* Physical */
1521 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1523 entry.dest = read_apic_id();
1526 * Add it to the IO-APIC irq-routing table:
1528 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1531 if (cpu_has_apic || apic_from_smp_config())
1532 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1537 * Not an __init, needed by the reboot code
1539 void disable_IO_APIC(void)
1542 * Clear the IO-APIC before rebooting:
1546 if (!nr_legacy_irqs())
1549 x86_io_apic_ops.disable();
1552 #ifdef CONFIG_X86_32
1554 * function to set the IO-APIC physical IDs based on the
1555 * values stored in the MPC table.
1557 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1559 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1561 union IO_APIC_reg_00 reg_00;
1562 physid_mask_t phys_id_present_map;
1565 unsigned char old_id;
1566 unsigned long flags;
1569 * This is broken; anything with a real cpu count has to
1570 * circumvent this idiocy regardless.
1572 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1575 * Set the IOAPIC ID to the value stored in the MPC table.
1577 for_each_ioapic(ioapic_idx) {
1578 /* Read the register 0 value */
1579 raw_spin_lock_irqsave(&ioapic_lock, flags);
1580 reg_00.raw = io_apic_read(ioapic_idx, 0);
1581 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1583 old_id = mpc_ioapic_id(ioapic_idx);
1585 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1586 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1587 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1588 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1590 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1594 * Sanity check, is the ID really free? Every APIC in a
1595 * system must have a unique ID or we get lots of nice
1596 * 'stuck on smp_invalidate_needed IPI wait' messages.
1598 if (apic->check_apicid_used(&phys_id_present_map,
1599 mpc_ioapic_id(ioapic_idx))) {
1600 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1601 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1602 for (i = 0; i < get_physical_broadcast(); i++)
1603 if (!physid_isset(i, phys_id_present_map))
1605 if (i >= get_physical_broadcast())
1606 panic("Max APIC ID exceeded!\n");
1607 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1609 physid_set(i, phys_id_present_map);
1610 ioapics[ioapic_idx].mp_config.apicid = i;
1613 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1615 apic_printk(APIC_VERBOSE, "Setting %d in the "
1616 "phys_id_present_map\n",
1617 mpc_ioapic_id(ioapic_idx));
1618 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1622 * We need to adjust the IRQ routing table
1623 * if the ID changed.
1625 if (old_id != mpc_ioapic_id(ioapic_idx))
1626 for (i = 0; i < mp_irq_entries; i++)
1627 if (mp_irqs[i].dstapic == old_id)
1629 = mpc_ioapic_id(ioapic_idx);
1632 * Update the ID register according to the right value
1633 * from the MPC table if they are different.
1635 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1638 apic_printk(APIC_VERBOSE, KERN_INFO
1639 "...changing IO-APIC physical APIC ID to %d ...",
1640 mpc_ioapic_id(ioapic_idx));
1642 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1643 raw_spin_lock_irqsave(&ioapic_lock, flags);
1644 io_apic_write(ioapic_idx, 0, reg_00.raw);
1645 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1650 raw_spin_lock_irqsave(&ioapic_lock, flags);
1651 reg_00.raw = io_apic_read(ioapic_idx, 0);
1652 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1653 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1654 pr_cont("could not set ID!\n");
1656 apic_printk(APIC_VERBOSE, " ok.\n");
1660 void __init setup_ioapic_ids_from_mpc(void)
1666 * Don't check I/O APIC IDs for xAPIC systems. They have
1667 * no meaning without the serial APIC bus.
1669 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1670 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1672 setup_ioapic_ids_from_mpc_nocheck();
1676 int no_timer_check __initdata;
1678 static int __init notimercheck(char *s)
1683 __setup("no_timer_check", notimercheck);
1686 * There is a nasty bug in some older SMP boards, their mptable lies
1687 * about the timer IRQ. We do the following to work around the situation:
1689 * - timer IRQ defaults to IO-APIC IRQ
1690 * - if this function detects that timer IRQs are defunct, then we fall
1691 * back to ISA timer IRQs
1693 static int __init timer_irq_works(void)
1695 unsigned long t1 = jiffies;
1696 unsigned long flags;
1701 local_save_flags(flags);
1703 /* Let ten ticks pass... */
1704 mdelay((10 * 1000) / HZ);
1705 local_irq_restore(flags);
1708 * Expect a few ticks at least, to be sure some possible
1709 * glue logic does not lock up after one or two first
1710 * ticks in a non-ExtINT mode. Also the local APIC
1711 * might have cached one ExtINT interrupt. Finally, at
1712 * least one tick may be lost due to delays.
1716 if (time_after(jiffies, t1 + 4))
1722 * In the SMP+IOAPIC case it might happen that there are an unspecified
1723 * number of pending IRQ events unhandled. These cases are very rare,
1724 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1725 * better to do it this way as thus we do not have to be aware of
1726 * 'pending' interrupts in the IRQ path, except at this point.
1729 * Edge triggered needs to resend any interrupt
1730 * that was delayed but this is now handled in the device
1735 * Starting up a edge-triggered IO-APIC interrupt is
1736 * nasty - we need to make sure that we get the edge.
1737 * If it is already asserted for some reason, we need
1738 * return 1 to indicate that is was pending.
1740 * This is not complete - we should be able to fake
1741 * an edge even if it isn't on the 8259A...
1744 static unsigned int startup_ioapic_irq(struct irq_data *data)
1746 int was_pending = 0, irq = data->irq;
1747 unsigned long flags;
1749 raw_spin_lock_irqsave(&ioapic_lock, flags);
1750 if (irq < nr_legacy_irqs()) {
1751 legacy_pic->mask(irq);
1752 if (legacy_pic->irq_pending(irq))
1755 __unmask_ioapic(irqd_cfg(data));
1756 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1762 * Level and edge triggered IO-APIC interrupts need different handling,
1763 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1764 * handled with the level-triggered descriptor, but that one has slightly
1765 * more overhead. Level-triggered interrupts cannot be handled with the
1766 * edge-triggered handler, without risking IRQ storms and other ugly
1770 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
1773 struct irq_pin_list *entry;
1774 u8 vector = cfg->vector;
1776 for_each_irq_pin(entry, cfg->irq_2_pin) {
1782 io_apic_write(apic, 0x11 + pin*2, dest);
1783 reg = io_apic_read(apic, 0x10 + pin*2);
1784 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
1786 io_apic_modify(apic, 0x10 + pin*2, reg);
1790 int native_ioapic_set_affinity(struct irq_data *data,
1791 const struct cpumask *mask,
1794 unsigned int dest, irq = data->irq;
1795 unsigned long flags;
1798 if (!config_enabled(CONFIG_SMP))
1801 raw_spin_lock_irqsave(&ioapic_lock, flags);
1802 ret = apic_set_affinity(data, mask, &dest);
1804 /* Only the high 8 bits are valid. */
1805 dest = SET_APIC_LOGICAL_ID(dest);
1806 __target_IO_APIC_irq(irq, dest, irqd_cfg(data));
1807 ret = IRQ_SET_MASK_OK_NOCOPY;
1809 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1813 atomic_t irq_mis_count;
1815 #ifdef CONFIG_GENERIC_PENDING_IRQ
1816 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
1818 struct irq_pin_list *entry;
1819 unsigned long flags;
1821 raw_spin_lock_irqsave(&ioapic_lock, flags);
1822 for_each_irq_pin(entry, cfg->irq_2_pin) {
1827 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1828 /* Is the remote IRR bit set? */
1829 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1830 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1834 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1839 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
1841 /* If we are moving the irq we need to mask it */
1842 if (unlikely(irqd_is_setaffinity_pending(data))) {
1849 static inline void ioapic_irqd_unmask(struct irq_data *data,
1850 struct irq_cfg *cfg, bool masked)
1852 if (unlikely(masked)) {
1853 /* Only migrate the irq if the ack has been received.
1855 * On rare occasions the broadcast level triggered ack gets
1856 * delayed going to ioapics, and if we reprogram the
1857 * vector while Remote IRR is still set the irq will never
1860 * To prevent this scenario we read the Remote IRR bit
1861 * of the ioapic. This has two effects.
1862 * - On any sane system the read of the ioapic will
1863 * flush writes (and acks) going to the ioapic from
1865 * - We get to see if the ACK has actually been delivered.
1867 * Based on failed experiments of reprogramming the
1868 * ioapic entry from outside of irq context starting
1869 * with masking the ioapic entry and then polling until
1870 * Remote IRR was clear before reprogramming the
1871 * ioapic I don't trust the Remote IRR bit to be
1872 * completey accurate.
1874 * However there appears to be no other way to plug
1875 * this race, so if the Remote IRR bit is not
1876 * accurate and is causing problems then it is a hardware bug
1877 * and you can go talk to the chipset vendor about it.
1879 if (!io_apic_level_ack_pending(cfg))
1880 irq_move_masked_irq(data);
1885 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
1889 static inline void ioapic_irqd_unmask(struct irq_data *data,
1890 struct irq_cfg *cfg, bool masked)
1895 static void ioapic_ack_level(struct irq_data *data)
1897 struct irq_cfg *cfg = irqd_cfg(data);
1902 irq_complete_move(cfg);
1903 masked = ioapic_irqd_mask(data, cfg);
1906 * It appears there is an erratum which affects at least version 0x11
1907 * of I/O APIC (that's the 82093AA and cores integrated into various
1908 * chipsets). Under certain conditions a level-triggered interrupt is
1909 * erroneously delivered as edge-triggered one but the respective IRR
1910 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1911 * message but it will never arrive and further interrupts are blocked
1912 * from the source. The exact reason is so far unknown, but the
1913 * phenomenon was observed when two consecutive interrupt requests
1914 * from a given source get delivered to the same CPU and the source is
1915 * temporarily disabled in between.
1917 * A workaround is to simulate an EOI message manually. We achieve it
1918 * by setting the trigger mode to edge and then to level when the edge
1919 * trigger mode gets detected in the TMR of a local APIC for a
1920 * level-triggered interrupt. We mask the source for the time of the
1921 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1922 * The idea is from Manfred Spraul. --macro
1924 * Also in the case when cpu goes offline, fixup_irqs() will forward
1925 * any unhandled interrupt on the offlined cpu to the new cpu
1926 * destination that is handling the corresponding interrupt. This
1927 * interrupt forwarding is done via IPI's. Hence, in this case also
1928 * level-triggered io-apic interrupt will be seen as an edge
1929 * interrupt in the IRR. And we can't rely on the cpu's EOI
1930 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1931 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1932 * supporting EOI register, we do an explicit EOI to clear the
1933 * remote IRR and on IO-APIC's which don't have an EOI register,
1934 * we use the above logic (mask+edge followed by unmask+level) from
1935 * Manfred Spraul to clear the remote IRR.
1938 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1941 * We must acknowledge the irq before we move it or the acknowledge will
1942 * not propagate properly.
1947 * Tail end of clearing remote IRR bit (either by delivering the EOI
1948 * message via io-apic EOI register write or simulating it using
1949 * mask+edge followed by unnask+level logic) manually when the
1950 * level triggered interrupt is seen as the edge triggered interrupt
1953 if (!(v & (1 << (i & 0x1f)))) {
1954 atomic_inc(&irq_mis_count);
1955 eoi_ioapic_pin(cfg->vector, cfg);
1958 ioapic_irqd_unmask(data, cfg, masked);
1961 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1963 struct mp_chip_data *data = irq_data->chip_data;
1966 * Intr-remapping uses pin number as the virtual vector
1967 * in the RTE. Actual vector is programmed in
1968 * intr-remapping table entry. Hence for the io-apic
1969 * EOI we use the pin number.
1972 eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data));
1975 static int ioapic_set_affinity(struct irq_data *irq_data,
1976 const struct cpumask *mask, bool force)
1978 struct irq_data *parent = irq_data->parent_data;
1979 struct mp_chip_data *data = irq_data->chip_data;
1980 unsigned int dest, irq = irq_data->irq;
1981 struct irq_cfg *cfg;
1982 unsigned long flags;
1985 ret = parent->chip->irq_set_affinity(parent, mask, force);
1986 raw_spin_lock_irqsave(&ioapic_lock, flags);
1987 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1988 cfg = irqd_cfg(irq_data);
1989 data->entry.dest = cfg->dest_apicid;
1990 data->entry.vector = cfg->vector;
1991 /* Only the high 8 bits are valid. */
1992 dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid);
1993 __target_IO_APIC_irq(irq, dest, cfg);
1995 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2000 static struct irq_chip ioapic_chip __read_mostly = {
2002 .irq_startup = startup_ioapic_irq,
2003 .irq_mask = mask_ioapic_irq,
2004 .irq_unmask = unmask_ioapic_irq,
2005 .irq_ack = irq_chip_ack_parent,
2006 .irq_eoi = ioapic_ack_level,
2007 .irq_set_affinity = ioapic_set_affinity,
2008 .flags = IRQCHIP_SKIP_SET_WAKE,
2011 static struct irq_chip ioapic_ir_chip __read_mostly = {
2012 .name = "IR-IO-APIC",
2013 .irq_startup = startup_ioapic_irq,
2014 .irq_mask = mask_ioapic_irq,
2015 .irq_unmask = unmask_ioapic_irq,
2016 .irq_ack = irq_chip_ack_parent,
2017 .irq_eoi = ioapic_ir_ack_level,
2018 .irq_set_affinity = ioapic_set_affinity,
2019 .flags = IRQCHIP_SKIP_SET_WAKE,
2022 static inline void init_IO_APIC_traps(void)
2024 struct irq_cfg *cfg;
2027 for_each_active_irq(irq) {
2029 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2031 * Hmm.. We don't have an entry for this,
2032 * so default to an old-fashioned 8259
2033 * interrupt if we can..
2035 if (irq < nr_legacy_irqs())
2036 legacy_pic->make_irq(irq);
2038 /* Strange. Oh, well.. */
2039 irq_set_chip(irq, &no_irq_chip);
2045 * The local APIC irq-chip implementation:
2048 static void mask_lapic_irq(struct irq_data *data)
2052 v = apic_read(APIC_LVT0);
2053 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2056 static void unmask_lapic_irq(struct irq_data *data)
2060 v = apic_read(APIC_LVT0);
2061 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2064 static void ack_lapic_irq(struct irq_data *data)
2069 static struct irq_chip lapic_chip __read_mostly = {
2070 .name = "local-APIC",
2071 .irq_mask = mask_lapic_irq,
2072 .irq_unmask = unmask_lapic_irq,
2073 .irq_ack = ack_lapic_irq,
2076 static void lapic_register_intr(int irq)
2078 irq_clear_status_flags(irq, IRQ_LEVEL);
2079 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2084 * This looks a bit hackish but it's about the only one way of sending
2085 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2086 * not support the ExtINT mode, unfortunately. We need to send these
2087 * cycles as some i82489DX-based boards have glue logic that keeps the
2088 * 8259A interrupt line asserted until INTA. --macro
2090 static inline void __init unlock_ExtINT_logic(void)
2093 struct IO_APIC_route_entry entry0, entry1;
2094 unsigned char save_control, save_freq_select;
2096 pin = find_isa_irq_pin(8, mp_INT);
2101 apic = find_isa_irq_apic(8, mp_INT);
2107 entry0 = ioapic_read_entry(apic, pin);
2108 clear_IO_APIC_pin(apic, pin);
2110 memset(&entry1, 0, sizeof(entry1));
2112 entry1.dest_mode = 0; /* physical delivery */
2113 entry1.mask = 0; /* unmask IRQ now */
2114 entry1.dest = hard_smp_processor_id();
2115 entry1.delivery_mode = dest_ExtINT;
2116 entry1.polarity = entry0.polarity;
2120 ioapic_write_entry(apic, pin, entry1);
2122 save_control = CMOS_READ(RTC_CONTROL);
2123 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2124 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2126 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2131 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2135 CMOS_WRITE(save_control, RTC_CONTROL);
2136 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2137 clear_IO_APIC_pin(apic, pin);
2139 ioapic_write_entry(apic, pin, entry0);
2142 static int disable_timer_pin_1 __initdata;
2143 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2144 static int __init disable_timer_pin_setup(char *arg)
2146 disable_timer_pin_1 = 1;
2149 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2151 static int mp_alloc_timer_irq(int ioapic, int pin)
2154 struct irq_alloc_info info;
2155 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2158 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2159 info.ioapic_id = mpc_ioapic_id(ioapic);
2160 info.ioapic_pin = pin;
2161 mutex_lock(&ioapic_mutex);
2162 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2163 mutex_unlock(&ioapic_mutex);
2170 * This code may look a bit paranoid, but it's supposed to cooperate with
2171 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2172 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2173 * fanatically on his truly buggy board.
2175 * FIXME: really need to revamp this for all platforms.
2177 static inline void __init check_timer(void)
2179 struct irq_cfg *cfg = irq_cfg(0);
2180 int node = cpu_to_node(0);
2181 int apic1, pin1, apic2, pin2;
2182 unsigned long flags;
2185 local_irq_save(flags);
2188 * get/set the timer IRQ vector:
2190 legacy_pic->mask(0);
2193 * As IRQ0 is to be enabled in the 8259A, the virtual
2194 * wire has to be disabled in the local APIC. Also
2195 * timer interrupts need to be acknowledged manually in
2196 * the 8259A for the i82489DX when using the NMI
2197 * watchdog as that APIC treats NMIs as level-triggered.
2198 * The AEOI mode will finish them in the 8259A
2201 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2202 legacy_pic->init(1);
2204 pin1 = find_isa_irq_pin(0, mp_INT);
2205 apic1 = find_isa_irq_apic(0, mp_INT);
2206 pin2 = ioapic_i8259.pin;
2207 apic2 = ioapic_i8259.apic;
2209 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2210 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2211 cfg->vector, apic1, pin1, apic2, pin2);
2214 * Some BIOS writers are clueless and report the ExtINTA
2215 * I/O APIC input from the cascaded 8259A as the timer
2216 * interrupt input. So just in case, if only one pin
2217 * was found above, try it both directly and through the
2221 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2225 } else if (pin2 == -1) {
2231 /* Ok, does IRQ0 through the IOAPIC work? */
2233 mp_alloc_timer_irq(apic1, pin1);
2236 * for edge trigger, it's already unmasked,
2237 * so only need to unmask if it is level-trigger
2238 * do we really have level trigger timer?
2241 idx = find_irq_entry(apic1, pin1, mp_INT);
2242 if (idx != -1 && irq_trigger(idx))
2245 irq_domain_activate_irq(irq_get_irq_data(0));
2246 if (timer_irq_works()) {
2247 if (disable_timer_pin_1 > 0)
2248 clear_IO_APIC_pin(0, pin1);
2251 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2252 local_irq_disable();
2253 clear_IO_APIC_pin(apic1, pin1);
2255 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2256 "8254 timer not connected to IO-APIC\n");
2258 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2259 "(IRQ0) through the 8259A ...\n");
2260 apic_printk(APIC_QUIET, KERN_INFO
2261 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2263 * legacy devices should be connected to IO APIC #0
2265 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2266 irq_domain_activate_irq(irq_get_irq_data(0));
2267 legacy_pic->unmask(0);
2268 if (timer_irq_works()) {
2269 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2273 * Cleanup, just in case ...
2275 local_irq_disable();
2276 legacy_pic->mask(0);
2277 clear_IO_APIC_pin(apic2, pin2);
2278 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2281 apic_printk(APIC_QUIET, KERN_INFO
2282 "...trying to set up timer as Virtual Wire IRQ...\n");
2284 lapic_register_intr(0);
2285 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2286 legacy_pic->unmask(0);
2288 if (timer_irq_works()) {
2289 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2292 local_irq_disable();
2293 legacy_pic->mask(0);
2294 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2295 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2297 apic_printk(APIC_QUIET, KERN_INFO
2298 "...trying to set up timer as ExtINT IRQ...\n");
2300 legacy_pic->init(0);
2301 legacy_pic->make_irq(0);
2302 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2304 unlock_ExtINT_logic();
2306 if (timer_irq_works()) {
2307 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2310 local_irq_disable();
2311 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2312 if (apic_is_x2apic_enabled())
2313 apic_printk(APIC_QUIET, KERN_INFO
2314 "Perhaps problem with the pre-enabled x2apic mode\n"
2315 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2316 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2317 "report. Then try booting with the 'noapic' option.\n");
2319 local_irq_restore(flags);
2323 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2324 * to devices. However there may be an I/O APIC pin available for
2325 * this interrupt regardless. The pin may be left unconnected, but
2326 * typically it will be reused as an ExtINT cascade interrupt for
2327 * the master 8259A. In the MPS case such a pin will normally be
2328 * reported as an ExtINT interrupt in the MP table. With ACPI
2329 * there is no provision for ExtINT interrupts, and in the absence
2330 * of an override it would be treated as an ordinary ISA I/O APIC
2331 * interrupt, that is edge-triggered and unmasked by default. We
2332 * used to do this, but it caused problems on some systems because
2333 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2334 * the same ExtINT cascade interrupt to drive the local APIC of the
2335 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2336 * the I/O APIC in all cases now. No actual device should request
2337 * it anyway. --macro
2339 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2341 static int mp_irqdomain_create(int ioapic)
2343 struct irq_alloc_info info;
2344 struct irq_domain *parent;
2345 int hwirqs = mp_ioapic_pin_count(ioapic);
2346 struct ioapic *ip = &ioapics[ioapic];
2347 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2348 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2350 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2353 init_irq_alloc_info(&info, NULL);
2354 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2355 info.ioapic_id = mpc_ioapic_id(ioapic);
2356 parent = irq_remapping_get_ir_irq_domain(&info);
2358 parent = x86_vector_domain;
2360 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2361 (void *)(long)ioapic);
2365 ip->irqdomain->parent = parent;
2367 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2368 cfg->type == IOAPIC_DOMAIN_STRICT)
2369 ioapic_dynirq_base = max(ioapic_dynirq_base,
2370 gsi_cfg->gsi_end + 1);
2375 static void ioapic_destroy_irqdomain(int idx)
2377 if (ioapics[idx].irqdomain) {
2378 irq_domain_remove(ioapics[idx].irqdomain);
2379 ioapics[idx].irqdomain = NULL;
2383 void __init setup_IO_APIC(void)
2387 if (skip_ioapic_setup || !nr_ioapics)
2390 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2392 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2393 for_each_ioapic(ioapic)
2394 BUG_ON(mp_irqdomain_create(ioapic));
2397 * Set up IO-APIC IRQ routing.
2399 x86_init.mpparse.setup_ioapic_ids();
2402 setup_IO_APIC_irqs();
2403 init_IO_APIC_traps();
2404 if (nr_legacy_irqs())
2407 ioapic_initialized = 1;
2411 * Called after all the initialization is done. If we didn't find any
2412 * APIC bugs then we can allow the modify fast path
2415 static int __init io_apic_bug_finalize(void)
2417 if (sis_apic_bug == -1)
2422 late_initcall(io_apic_bug_finalize);
2424 static void resume_ioapic_id(int ioapic_idx)
2426 unsigned long flags;
2427 union IO_APIC_reg_00 reg_00;
2429 raw_spin_lock_irqsave(&ioapic_lock, flags);
2430 reg_00.raw = io_apic_read(ioapic_idx, 0);
2431 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2432 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2433 io_apic_write(ioapic_idx, 0, reg_00.raw);
2435 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2438 static void ioapic_resume(void)
2442 for_each_ioapic_reverse(ioapic_idx)
2443 resume_ioapic_id(ioapic_idx);
2445 restore_ioapic_entries();
2448 static struct syscore_ops ioapic_syscore_ops = {
2449 .suspend = save_ioapic_entries,
2450 .resume = ioapic_resume,
2453 static int __init ioapic_init_ops(void)
2455 register_syscore_ops(&ioapic_syscore_ops);
2460 device_initcall(ioapic_init_ops);
2462 static int io_apic_get_redir_entries(int ioapic)
2464 union IO_APIC_reg_01 reg_01;
2465 unsigned long flags;
2467 raw_spin_lock_irqsave(&ioapic_lock, flags);
2468 reg_01.raw = io_apic_read(ioapic, 1);
2469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2471 /* The register returns the maximum index redir index
2472 * supported, which is one less than the total number of redir
2475 return reg_01.bits.entries + 1;
2478 unsigned int arch_dynirq_lower_bound(unsigned int from)
2481 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2482 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2484 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2487 #ifdef CONFIG_X86_32
2488 static int io_apic_get_unique_id(int ioapic, int apic_id)
2490 union IO_APIC_reg_00 reg_00;
2491 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2493 unsigned long flags;
2497 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2498 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2499 * supports up to 16 on one shared APIC bus.
2501 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2502 * advantage of new APIC bus architecture.
2505 if (physids_empty(apic_id_map))
2506 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2508 raw_spin_lock_irqsave(&ioapic_lock, flags);
2509 reg_00.raw = io_apic_read(ioapic, 0);
2510 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2512 if (apic_id >= get_physical_broadcast()) {
2513 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2514 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2515 apic_id = reg_00.bits.ID;
2519 * Every APIC in a system must have a unique ID or we get lots of nice
2520 * 'stuck on smp_invalidate_needed IPI wait' messages.
2522 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2524 for (i = 0; i < get_physical_broadcast(); i++) {
2525 if (!apic->check_apicid_used(&apic_id_map, i))
2529 if (i == get_physical_broadcast())
2530 panic("Max apic_id exceeded!\n");
2532 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2533 "trying %d\n", ioapic, apic_id, i);
2538 apic->apicid_to_cpu_present(apic_id, &tmp);
2539 physids_or(apic_id_map, apic_id_map, tmp);
2541 if (reg_00.bits.ID != apic_id) {
2542 reg_00.bits.ID = apic_id;
2544 raw_spin_lock_irqsave(&ioapic_lock, flags);
2545 io_apic_write(ioapic, 0, reg_00.raw);
2546 reg_00.raw = io_apic_read(ioapic, 0);
2547 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2550 if (reg_00.bits.ID != apic_id) {
2551 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2557 apic_printk(APIC_VERBOSE, KERN_INFO
2558 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2563 static u8 io_apic_unique_id(int idx, u8 id)
2565 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2566 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2567 return io_apic_get_unique_id(idx, id);
2572 static u8 io_apic_unique_id(int idx, u8 id)
2574 union IO_APIC_reg_00 reg_00;
2575 DECLARE_BITMAP(used, 256);
2576 unsigned long flags;
2580 bitmap_zero(used, 256);
2582 __set_bit(mpc_ioapic_id(i), used);
2584 /* Hand out the requested id if available */
2585 if (!test_bit(id, used))
2589 * Read the current id from the ioapic and keep it if
2592 raw_spin_lock_irqsave(&ioapic_lock, flags);
2593 reg_00.raw = io_apic_read(idx, 0);
2594 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2595 new_id = reg_00.bits.ID;
2596 if (!test_bit(new_id, used)) {
2597 apic_printk(APIC_VERBOSE, KERN_INFO
2598 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2604 * Get the next free id and write it to the ioapic.
2606 new_id = find_first_zero_bit(used, 256);
2607 reg_00.bits.ID = new_id;
2608 raw_spin_lock_irqsave(&ioapic_lock, flags);
2609 io_apic_write(idx, 0, reg_00.raw);
2610 reg_00.raw = io_apic_read(idx, 0);
2611 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2613 BUG_ON(reg_00.bits.ID != new_id);
2619 static int io_apic_get_version(int ioapic)
2621 union IO_APIC_reg_01 reg_01;
2622 unsigned long flags;
2624 raw_spin_lock_irqsave(&ioapic_lock, flags);
2625 reg_01.raw = io_apic_read(ioapic, 1);
2626 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2628 return reg_01.bits.version;
2631 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2633 int ioapic, pin, idx;
2635 if (skip_ioapic_setup)
2638 ioapic = mp_find_ioapic(gsi);
2642 pin = mp_find_ioapic_pin(ioapic, gsi);
2646 idx = find_irq_entry(ioapic, pin, mp_INT);
2650 *trigger = irq_trigger(idx);
2651 *polarity = irq_polarity(idx);
2656 * This function currently is only a helper for the i386 smp boot process where
2657 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2658 * so mask in all cases should simply be apic->target_cpus()
2661 void __init setup_ioapic_dest(void)
2663 int pin, ioapic, irq, irq_entry;
2664 const struct cpumask *mask;
2665 struct irq_data *idata;
2667 if (skip_ioapic_setup == 1)
2670 for_each_ioapic_pin(ioapic, pin) {
2671 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2672 if (irq_entry == -1)
2675 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2676 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2679 idata = irq_get_irq_data(irq);
2682 * Honour affinities which have been set in early boot
2684 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2685 mask = idata->affinity;
2687 mask = apic->target_cpus();
2689 x86_io_apic_ops.set_affinity(idata, mask, false);
2695 #define IOAPIC_RESOURCE_NAME_SIZE 11
2697 static struct resource *ioapic_resources;
2699 static struct resource * __init ioapic_setup_resources(void)
2702 struct resource *res;
2711 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2714 mem = alloc_bootmem(n);
2717 mem += sizeof(struct resource) * num;
2720 for_each_ioapic(i) {
2721 res[num].name = mem;
2722 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2723 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2724 mem += IOAPIC_RESOURCE_NAME_SIZE;
2726 ioapics[i].iomem_res = res;
2729 ioapic_resources = res;
2734 void __init native_io_apic_init_mappings(void)
2736 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2737 struct resource *ioapic_res;
2740 ioapic_res = ioapic_setup_resources();
2741 for_each_ioapic(i) {
2742 if (smp_found_config) {
2743 ioapic_phys = mpc_ioapic_addr(i);
2744 #ifdef CONFIG_X86_32
2747 "WARNING: bogus zero IO-APIC "
2748 "address found in MPTABLE, "
2749 "disabling IO/APIC support!\n");
2750 smp_found_config = 0;
2751 skip_ioapic_setup = 1;
2752 goto fake_ioapic_page;
2756 #ifdef CONFIG_X86_32
2759 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2760 ioapic_phys = __pa(ioapic_phys);
2762 set_fixmap_nocache(idx, ioapic_phys);
2763 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2764 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2768 ioapic_res->start = ioapic_phys;
2769 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2774 void __init ioapic_insert_resources(void)
2777 struct resource *r = ioapic_resources;
2782 "IO APIC resources couldn't be allocated.\n");
2786 for_each_ioapic(i) {
2787 insert_resource(&iomem_resource, r);
2792 int mp_find_ioapic(u32 gsi)
2796 if (nr_ioapics == 0)
2799 /* Find the IOAPIC that manages this GSI. */
2800 for_each_ioapic(i) {
2801 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2802 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2806 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2810 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2812 struct mp_ioapic_gsi *gsi_cfg;
2814 if (WARN_ON(ioapic < 0))
2817 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2818 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2821 return gsi - gsi_cfg->gsi_base;
2824 static int bad_ioapic_register(int idx)
2826 union IO_APIC_reg_00 reg_00;
2827 union IO_APIC_reg_01 reg_01;
2828 union IO_APIC_reg_02 reg_02;
2830 reg_00.raw = io_apic_read(idx, 0);
2831 reg_01.raw = io_apic_read(idx, 1);
2832 reg_02.raw = io_apic_read(idx, 2);
2834 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2835 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2836 mpc_ioapic_addr(idx));
2843 static int find_free_ioapic_entry(void)
2847 for (idx = 0; idx < MAX_IO_APICS; idx++)
2848 if (ioapics[idx].nr_registers == 0)
2851 return MAX_IO_APICS;
2855 * mp_register_ioapic - Register an IOAPIC device
2856 * @id: hardware IOAPIC ID
2857 * @address: physical address of IOAPIC register area
2858 * @gsi_base: base of GSI associated with the IOAPIC
2859 * @cfg: configuration information for the IOAPIC
2861 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2862 struct ioapic_domain_cfg *cfg)
2864 bool hotplug = !!ioapic_initialized;
2865 struct mp_ioapic_gsi *gsi_cfg;
2866 int idx, ioapic, entries;
2870 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2873 for_each_ioapic(ioapic)
2874 if (ioapics[ioapic].mp_config.apicaddr == address) {
2875 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2880 idx = find_free_ioapic_entry();
2881 if (idx >= MAX_IO_APICS) {
2882 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2887 ioapics[idx].mp_config.type = MP_IOAPIC;
2888 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2889 ioapics[idx].mp_config.apicaddr = address;
2891 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2892 if (bad_ioapic_register(idx)) {
2893 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2897 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2898 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2901 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2902 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2904 entries = io_apic_get_redir_entries(idx);
2905 gsi_end = gsi_base + entries - 1;
2906 for_each_ioapic(ioapic) {
2907 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2908 if ((gsi_base >= gsi_cfg->gsi_base &&
2909 gsi_base <= gsi_cfg->gsi_end) ||
2910 (gsi_end >= gsi_cfg->gsi_base &&
2911 gsi_end <= gsi_cfg->gsi_end)) {
2912 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2914 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2915 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2919 gsi_cfg = mp_ioapic_gsi_routing(idx);
2920 gsi_cfg->gsi_base = gsi_base;
2921 gsi_cfg->gsi_end = gsi_end;
2923 ioapics[idx].irqdomain = NULL;
2924 ioapics[idx].irqdomain_cfg = *cfg;
2927 * If mp_register_ioapic() is called during early boot stage when
2928 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2929 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2932 if (mp_irqdomain_create(idx)) {
2933 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2936 alloc_ioapic_saved_registers(idx);
2939 if (gsi_cfg->gsi_end >= gsi_top)
2940 gsi_top = gsi_cfg->gsi_end + 1;
2941 if (nr_ioapics <= idx)
2942 nr_ioapics = idx + 1;
2944 /* Set nr_registers to mark entry present */
2945 ioapics[idx].nr_registers = entries;
2947 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2948 idx, mpc_ioapic_id(idx),
2949 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2950 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2955 int mp_unregister_ioapic(u32 gsi_base)
2960 for_each_ioapic(ioapic)
2961 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2966 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2970 for_each_pin(ioapic, pin) {
2971 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2972 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2973 struct mp_chip_data *data;
2976 data = irq_get_chip_data(irq);
2977 if (data && data->count) {
2978 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2985 /* Mark entry not present */
2986 ioapics[ioapic].nr_registers = 0;
2987 ioapic_destroy_irqdomain(ioapic);
2988 free_ioapic_saved_registers(ioapic);
2989 if (ioapics[ioapic].iomem_res)
2990 release_resource(ioapics[ioapic].iomem_res);
2991 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2992 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2997 int mp_ioapic_registered(u32 gsi_base)
3001 for_each_ioapic(ioapic)
3002 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
3008 static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr,
3009 int ioapic, int ioapic_pin,
3010 int trigger, int polarity)
3012 irq_attr->ioapic = ioapic;
3013 irq_attr->ioapic_pin = ioapic_pin;
3014 irq_attr->trigger = trigger;
3015 irq_attr->polarity = polarity;
3018 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
3019 struct irq_alloc_info *info)
3021 if (info && info->ioapic_valid) {
3022 data->trigger = info->ioapic_trigger;
3023 data->polarity = info->ioapic_polarity;
3024 } else if (acpi_get_override_irq(gsi, &data->trigger,
3025 &data->polarity) < 0) {
3026 /* PCI interrupts are always polarity one level triggered. */
3032 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
3033 struct IO_APIC_route_entry *entry)
3035 memset(entry, 0, sizeof(*entry));
3036 entry->delivery_mode = apic->irq_delivery_mode;
3037 entry->dest_mode = apic->irq_dest_mode;
3038 entry->dest = cfg->dest_apicid;
3039 entry->vector = cfg->vector;
3040 entry->mask = 0; /* enable IRQ */
3041 entry->trigger = data->trigger;
3042 entry->polarity = data->polarity;
3044 * Mask level triggered irqs.
3045 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
3051 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
3052 unsigned int nr_irqs, void *arg)
3054 int ret, ioapic, pin;
3055 struct irq_cfg *cfg;
3056 struct irq_data *irq_data;
3057 struct mp_chip_data *data;
3058 struct irq_alloc_info *info = arg;
3060 if (!info || nr_irqs > 1)
3062 irq_data = irq_domain_get_irq_data(domain, virq);
3066 ioapic = mp_irqdomain_ioapic_idx(domain);
3067 pin = info->ioapic_pin;
3068 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3071 data = kzalloc(sizeof(*data), GFP_KERNEL);
3075 info->ioapic_entry = &data->entry;
3076 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3082 irq_data->hwirq = info->ioapic_pin;
3083 irq_data->chip = (domain->parent == x86_vector_domain) ?
3084 &ioapic_chip : &ioapic_ir_chip;
3085 irq_data->chip_data = data;
3086 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3088 cfg = irqd_cfg(irq_data);
3089 add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin);
3090 if (info->ioapic_entry)
3091 mp_setup_entry(cfg, data, info->ioapic_entry);
3092 mp_register_handler(virq, data->trigger);
3093 if (virq < nr_legacy_irqs())
3094 legacy_pic->mask(virq);
3096 apic_printk(APIC_VERBOSE, KERN_DEBUG
3097 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3098 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3099 virq, data->trigger, data->polarity, cfg->dest_apicid);
3104 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3105 unsigned int nr_irqs)
3107 struct irq_cfg *cfg = irq_cfg(virq);
3108 struct irq_data *irq_data;
3110 BUG_ON(nr_irqs != 1);
3111 irq_data = irq_domain_get_irq_data(domain, virq);
3112 if (irq_data && irq_data->chip_data) {
3113 __remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain),
3114 (int)irq_data->hwirq);
3115 WARN_ON(!list_empty(&cfg->irq_2_pin));
3116 kfree(irq_data->chip_data);
3118 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3121 void mp_irqdomain_activate(struct irq_domain *domain,
3122 struct irq_data *irq_data)
3124 unsigned long flags;
3125 struct irq_pin_list *entry;
3126 struct mp_chip_data *data = irq_data->chip_data;
3127 struct irq_cfg *cfg = irqd_cfg(irq_data);
3129 raw_spin_lock_irqsave(&ioapic_lock, flags);
3130 for_each_irq_pin(entry, cfg->irq_2_pin)
3131 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
3132 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3135 void mp_irqdomain_deactivate(struct irq_domain *domain,
3136 struct irq_data *irq_data)
3138 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3139 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3140 (int)irq_data->hwirq);
3143 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3145 return (int)(long)domain->host_data;