2 * Support of MSI, HPET and DMAR interrupts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/dmar.h>
15 #include <linux/hpet.h>
16 #include <linux/msi.h>
17 #include <linux/irqdomain.h>
18 #include <asm/msidef.h>
20 #include <asm/hw_irq.h>
22 #include <asm/irq_remapping.h>
24 void native_compose_msi_msg(struct pci_dev *pdev,
25 unsigned int irq, unsigned int dest,
26 struct msi_msg *msg, u8 hpet_id)
28 struct irq_cfg *cfg = irq_cfg(irq);
30 msg->address_hi = MSI_ADDR_BASE_HI;
33 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
37 ((apic->irq_dest_mode == 0) ?
38 MSI_ADDR_DEST_MODE_PHYSICAL :
39 MSI_ADDR_DEST_MODE_LOGICAL) |
40 ((apic->irq_delivery_mode != dest_LowestPrio) ?
41 MSI_ADDR_REDIRECTION_CPU :
42 MSI_ADDR_REDIRECTION_LOWPRI) |
43 MSI_ADDR_DEST_ID(dest);
46 MSI_DATA_TRIGGER_EDGE |
47 MSI_DATA_LEVEL_ASSERT |
48 ((apic->irq_delivery_mode != dest_LowestPrio) ?
49 MSI_DATA_DELIVERY_FIXED :
50 MSI_DATA_DELIVERY_LOWPRI) |
51 MSI_DATA_VECTOR(cfg->vector);
54 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
56 struct irq_cfg *cfg = irqd_cfg(data);
58 msg->address_hi = MSI_ADDR_BASE_HI;
61 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
65 ((apic->irq_dest_mode == 0) ?
66 MSI_ADDR_DEST_MODE_PHYSICAL :
67 MSI_ADDR_DEST_MODE_LOGICAL) |
68 ((apic->irq_delivery_mode != dest_LowestPrio) ?
69 MSI_ADDR_REDIRECTION_CPU :
70 MSI_ADDR_REDIRECTION_LOWPRI) |
71 MSI_ADDR_DEST_ID(cfg->dest_apicid);
74 MSI_DATA_TRIGGER_EDGE |
75 MSI_DATA_LEVEL_ASSERT |
76 ((apic->irq_delivery_mode != dest_LowestPrio) ?
77 MSI_DATA_DELIVERY_FIXED :
78 MSI_DATA_DELIVERY_LOWPRI) |
79 MSI_DATA_VECTOR(cfg->vector);
82 static void msi_update_msg(struct msi_msg *msg, struct irq_data *irq_data)
84 struct irq_cfg *cfg = irqd_cfg(irq_data);
86 msg->data &= ~MSI_DATA_VECTOR_MASK;
87 msg->data |= MSI_DATA_VECTOR(cfg->vector);
88 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
89 msg->address_lo |= MSI_ADDR_DEST_ID(cfg->dest_apicid);
92 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
93 struct msi_msg *msg, u8 hpet_id)
103 err = assign_irq_vector(irq, cfg, apic->target_cpus());
107 err = apic->cpu_mask_to_apicid_and(cfg->domain,
108 apic->target_cpus(), &dest);
112 x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
118 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
120 struct irq_cfg *cfg = irqd_cfg(data);
125 ret = apic_set_affinity(data, mask, &dest);
129 __get_cached_msi_msg(data->msi_desc, &msg);
131 msg.data &= ~MSI_DATA_VECTOR_MASK;
132 msg.data |= MSI_DATA_VECTOR(cfg->vector);
133 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
134 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
136 __pci_write_msi_msg(data->msi_desc, &msg);
138 return IRQ_SET_MASK_OK_NOCOPY;
142 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
143 * which implement the MSI or MSI-X Capability Structure.
145 static struct irq_chip msi_chip = {
147 .irq_unmask = pci_msi_unmask_irq,
148 .irq_mask = pci_msi_mask_irq,
149 .irq_ack = apic_ack_edge,
150 .irq_set_affinity = msi_set_affinity,
151 .irq_retrigger = apic_retrigger_irq,
152 .flags = IRQCHIP_SKIP_SET_WAKE,
155 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
156 unsigned int irq_base, unsigned int irq_offset)
158 struct irq_chip *chip = &msi_chip;
160 unsigned int irq = irq_base + irq_offset;
163 ret = msi_compose_msg(dev, irq, &msg, -1);
167 irq_set_msi_desc_off(irq_base, irq_offset, msidesc);
170 * MSI-X message is written per-IRQ, the offset is always 0.
171 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
174 pci_write_msi_msg(irq, &msg);
176 setup_remapped_irq(irq, irq_cfg(irq), chip);
178 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
180 dev_dbg(&dev->dev, "irq %d for MSI/MSI-X\n", irq);
185 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
187 struct msi_desc *msidesc;
190 /* Multiple MSI vectors only supported with interrupt remapping */
191 if (type == PCI_CAP_ID_MSI && nvec > 1)
194 list_for_each_entry(msidesc, &dev->msi_list, list) {
195 irq = irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL);
199 ret = setup_msi_irq(dev, msidesc, irq, 0);
201 irq_domain_free_irqs(irq, 1);
209 void native_teardown_msi_irq(unsigned int irq)
211 irq_domain_free_irqs(irq, 1);
214 #ifdef CONFIG_DMAR_TABLE
216 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
219 struct irq_cfg *cfg = irqd_cfg(data);
220 unsigned int dest, irq = data->irq;
224 ret = apic_set_affinity(data, mask, &dest);
228 dmar_msi_read(irq, &msg);
230 msg.data &= ~MSI_DATA_VECTOR_MASK;
231 msg.data |= MSI_DATA_VECTOR(cfg->vector);
232 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
233 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
234 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
236 dmar_msi_write(irq, &msg);
238 return IRQ_SET_MASK_OK_NOCOPY;
241 static struct irq_chip dmar_msi_type = {
243 .irq_unmask = dmar_msi_unmask,
244 .irq_mask = dmar_msi_mask,
245 .irq_ack = apic_ack_edge,
246 .irq_set_affinity = dmar_msi_set_affinity,
247 .irq_retrigger = apic_retrigger_irq,
248 .flags = IRQCHIP_SKIP_SET_WAKE,
251 int arch_setup_dmar_msi(unsigned int irq)
256 ret = msi_compose_msg(NULL, irq, &msg, -1);
259 dmar_msi_write(irq, &msg);
260 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
265 int dmar_alloc_hwirq(void)
267 return irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL);
270 void dmar_free_hwirq(int irq)
272 irq_domain_free_irqs(irq, 1);
277 * MSI message composition
279 #ifdef CONFIG_HPET_TIMER
280 static inline int hpet_dev_id(struct irq_domain *domain)
282 return (int)(long)domain->host_data;
285 static int hpet_msi_set_affinity(struct irq_data *data,
286 const struct cpumask *mask, bool force)
288 struct irq_data *parent = data->parent_data;
292 ret = parent->chip->irq_set_affinity(parent, mask, force);
293 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
294 hpet_msi_read(data->handler_data, &msg);
295 msi_update_msg(&msg, data);
296 hpet_msi_write(data->handler_data, &msg);
302 static struct irq_chip hpet_msi_controller = {
304 .irq_unmask = hpet_msi_unmask,
305 .irq_mask = hpet_msi_mask,
306 .irq_ack = irq_chip_ack_parent,
307 .irq_set_affinity = hpet_msi_set_affinity,
308 .irq_retrigger = irq_chip_retrigger_hierarchy,
309 .irq_print_chip = irq_remapping_print_chip,
310 .irq_compose_msi_msg = irq_msi_compose_msg,
311 .flags = IRQCHIP_SKIP_SET_WAKE,
314 int default_setup_hpet_msi(unsigned int irq, unsigned int id)
316 struct irq_chip *chip = &hpet_msi_controller;
320 ret = msi_compose_msg(NULL, irq, &msg, id);
324 hpet_msi_write(irq_get_handler_data(irq), &msg);
325 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
326 setup_remapped_irq(irq, irq_cfg(irq), chip);
328 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
332 static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
333 unsigned int nr_irqs, void *arg)
335 struct irq_alloc_info *info = arg;
338 if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_HPET)
340 if (irq_find_mapping(domain, info->hpet_index)) {
341 pr_warn("IRQ for HPET%d already exists.\n", info->hpet_index);
345 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
347 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
348 irq_domain_set_hwirq_and_chip(domain, virq, info->hpet_index,
349 &hpet_msi_controller, NULL);
350 irq_set_handler_data(virq, info->hpet_data);
351 __irq_set_handler(virq, handle_edge_irq, 0, "edge");
357 static void hpet_domain_free(struct irq_domain *domain, unsigned int virq,
358 unsigned int nr_irqs)
361 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
362 irq_domain_free_irqs_top(domain, virq, nr_irqs);
365 static void hpet_domain_activate(struct irq_domain *domain,
366 struct irq_data *irq_data)
370 BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
371 hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
374 static void hpet_domain_deactivate(struct irq_domain *domain,
375 struct irq_data *irq_data)
379 memset(&msg, 0, sizeof(msg));
380 hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
383 static struct irq_domain_ops hpet_domain_ops = {
384 .alloc = hpet_domain_alloc,
385 .free = hpet_domain_free,
386 .activate = hpet_domain_activate,
387 .deactivate = hpet_domain_deactivate,
390 struct irq_domain *hpet_create_irq_domain(int hpet_id)
392 struct irq_domain *parent;
393 struct irq_alloc_info info;
395 if (x86_vector_domain == NULL)
398 init_irq_alloc_info(&info, NULL);
399 info.type = X86_IRQ_ALLOC_TYPE_HPET;
400 info.hpet_id = hpet_id;
401 parent = irq_remapping_get_ir_irq_domain(&info);
403 parent = x86_vector_domain;
405 return irq_domain_add_hierarchy(parent, 0, 0, NULL, &hpet_domain_ops,
406 (void *)(long)hpet_id);
409 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
412 struct irq_alloc_info info;
414 init_irq_alloc_info(&info, NULL);
415 info.type = X86_IRQ_ALLOC_TYPE_HPET;
416 info.hpet_data = dev;
417 info.hpet_id = hpet_dev_id(domain);
418 info.hpet_index = dev_num;
420 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);