2 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/seq_file.h>
15 #include <linux/init.h>
16 #include <linux/compiler.h>
17 #include <linux/slab.h>
18 #include <asm/irqdomain.h>
19 #include <asm/hw_irq.h>
21 #include <asm/i8259.h>
23 #include <asm/irq_remapping.h>
25 #include <asm/trace/irq_vectors.h>
27 struct apic_chip_data {
28 struct irq_cfg hw_irq_cfg;
30 unsigned int prev_vector;
32 unsigned int prev_cpu;
34 struct hlist_node clist;
35 unsigned int move_in_progress : 1,
41 struct irq_domain *x86_vector_domain;
42 EXPORT_SYMBOL_GPL(x86_vector_domain);
43 static DEFINE_RAW_SPINLOCK(vector_lock);
44 static cpumask_var_t vector_searchmask;
45 static struct irq_chip lapic_controller;
46 static struct irq_matrix *vector_matrix;
48 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
51 void lock_vector_lock(void)
53 /* Used to the online set of cpus does not change
54 * during assign_irq_vector.
56 raw_spin_lock(&vector_lock);
59 void unlock_vector_lock(void)
61 raw_spin_unlock(&vector_lock);
64 void init_irq_alloc_info(struct irq_alloc_info *info,
65 const struct cpumask *mask)
67 memset(info, 0, sizeof(*info));
71 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
76 memset(dst, 0, sizeof(*dst));
79 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
84 while (irqd->parent_data)
85 irqd = irqd->parent_data;
87 return irqd->chip_data;
90 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
92 struct apic_chip_data *apicd = apic_chip_data(irqd);
94 return apicd ? &apicd->hw_irq_cfg : NULL;
96 EXPORT_SYMBOL_GPL(irqd_cfg);
98 struct irq_cfg *irq_cfg(unsigned int irq)
100 return irqd_cfg(irq_get_irq_data(irq));
103 static struct apic_chip_data *alloc_apic_chip_data(int node)
105 struct apic_chip_data *apicd;
107 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
109 INIT_HLIST_NODE(&apicd->clist);
113 static void free_apic_chip_data(struct apic_chip_data *apicd)
118 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
121 struct apic_chip_data *apicd = apic_chip_data(irqd);
123 lockdep_assert_held(&vector_lock);
125 apicd->hw_irq_cfg.vector = vector;
126 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
127 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
128 trace_vector_config(irqd->irq, vector, cpu,
129 apicd->hw_irq_cfg.dest_apicid);
132 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
135 struct apic_chip_data *apicd = apic_chip_data(irqd);
136 struct irq_desc *desc = irq_data_to_desc(irqd);
137 bool managed = irqd_affinity_is_managed(irqd);
139 lockdep_assert_held(&vector_lock);
141 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
145 * If there is no vector associated or if the associated vector is
146 * the shutdown vector, which is associated to make PCI/MSI
147 * shutdown mode work, then there is nothing to release. Clear out
148 * prev_vector for this and the offlined target case.
150 apicd->prev_vector = 0;
151 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
154 * If the target CPU of the previous vector is online, then mark
155 * the vector as move in progress and store it for cleanup when the
156 * first interrupt on the new vector arrives. If the target CPU is
157 * offline then the regular release mechanism via the cleanup
158 * vector is not possible and the vector can be immediately freed
159 * in the underlying matrix allocator.
161 if (cpu_online(apicd->cpu)) {
162 apicd->move_in_progress = true;
163 apicd->prev_vector = apicd->vector;
164 apicd->prev_cpu = apicd->cpu;
166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
171 apicd->vector = newvec;
173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
174 per_cpu(vector_irq, newcpu)[newvec] = desc;
177 static void vector_assign_managed_shutdown(struct irq_data *irqd)
179 unsigned int cpu = cpumask_first(cpu_online_mask);
181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
184 static int reserve_managed_vector(struct irq_data *irqd)
186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
187 struct apic_chip_data *apicd = apic_chip_data(irqd);
191 raw_spin_lock_irqsave(&vector_lock, flags);
192 apicd->is_managed = true;
193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
194 raw_spin_unlock_irqrestore(&vector_lock, flags);
195 trace_vector_reserve_managed(irqd->irq, ret);
199 static void reserve_irq_vector_locked(struct irq_data *irqd)
201 struct apic_chip_data *apicd = apic_chip_data(irqd);
203 irq_matrix_reserve(vector_matrix);
204 apicd->can_reserve = true;
205 apicd->has_reserved = true;
206 irqd_set_can_reserve(irqd);
207 trace_vector_reserve(irqd->irq, 0);
208 vector_assign_managed_shutdown(irqd);
211 static int reserve_irq_vector(struct irq_data *irqd)
215 raw_spin_lock_irqsave(&vector_lock, flags);
216 reserve_irq_vector_locked(irqd);
217 raw_spin_unlock_irqrestore(&vector_lock, flags);
221 static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest)
223 struct apic_chip_data *apicd = apic_chip_data(irqd);
224 bool resvd = apicd->has_reserved;
225 unsigned int cpu = apicd->cpu;
226 int vector = apicd->vector;
228 lockdep_assert_held(&vector_lock);
231 * If the current target CPU is online and in the new requested
232 * affinity mask, there is no point in moving the interrupt from
233 * one CPU to another.
235 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
239 * Careful here. @apicd might either have move_in_progress set or
240 * be enqueued for cleanup. Assigning a new vector would either
241 * leave a stale vector on some CPU around or in case of a pending
242 * cleanup corrupt the hlist.
244 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
247 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
249 apic_update_vector(irqd, vector, cpu);
250 trace_vector_alloc(irqd->irq, vector, resvd, vector);
254 static int assign_vector_locked(struct irq_data *irqd,
255 const struct cpumask *dest)
257 struct apic_chip_data *apicd = apic_chip_data(irqd);
258 int vector = allocate_vector(irqd, dest);
263 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
267 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
272 raw_spin_lock_irqsave(&vector_lock, flags);
273 cpumask_and(vector_searchmask, dest, cpu_online_mask);
274 ret = assign_vector_locked(irqd, vector_searchmask);
275 raw_spin_unlock_irqrestore(&vector_lock, flags);
279 static int assign_irq_vector_any_locked(struct irq_data *irqd)
281 /* Get the affinity mask - either irq_default_affinity or (user) set */
282 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
283 int node = irq_data_get_node(irqd);
285 if (node == NUMA_NO_NODE)
287 /* Try the intersection of @affmsk and node mask */
288 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
289 if (!assign_vector_locked(irqd, vector_searchmask))
291 /* Try the node mask */
292 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
295 /* Try the full affinity mask */
296 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
297 if (!assign_vector_locked(irqd, vector_searchmask))
299 /* Try the full online mask */
300 return assign_vector_locked(irqd, cpu_online_mask);
304 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
306 if (irqd_affinity_is_managed(irqd))
307 return reserve_managed_vector(irqd);
309 return assign_irq_vector(irqd, info->mask);
311 * Make only a global reservation with no guarantee. A real vector
312 * is associated at activation time.
314 return reserve_irq_vector(irqd);
318 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
320 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
321 struct apic_chip_data *apicd = apic_chip_data(irqd);
324 cpumask_and(vector_searchmask, vector_searchmask, affmsk);
325 cpu = cpumask_first(vector_searchmask);
326 if (cpu >= nr_cpu_ids)
328 /* set_affinity might call here for nothing */
329 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
331 vector = irq_matrix_alloc_managed(vector_matrix, cpu);
332 trace_vector_alloc_managed(irqd->irq, vector, vector);
335 apic_update_vector(irqd, vector, cpu);
336 apic_update_irq_cfg(irqd, vector, cpu);
340 static void clear_irq_vector(struct irq_data *irqd)
342 struct apic_chip_data *apicd = apic_chip_data(irqd);
343 bool managed = irqd_affinity_is_managed(irqd);
344 unsigned int vector = apicd->vector;
346 lockdep_assert_held(&vector_lock);
351 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
354 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED;
355 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
358 /* Clean up move in progress */
359 vector = apicd->prev_vector;
363 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED;
364 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
365 apicd->prev_vector = 0;
366 apicd->move_in_progress = 0;
367 hlist_del_init(&apicd->clist);
370 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
372 struct apic_chip_data *apicd = apic_chip_data(irqd);
375 trace_vector_deactivate(irqd->irq, apicd->is_managed,
376 apicd->can_reserve, false);
378 /* Regular fixed assigned interrupt */
379 if (!apicd->is_managed && !apicd->can_reserve)
381 /* If the interrupt has a global reservation, nothing to do */
382 if (apicd->has_reserved)
385 raw_spin_lock_irqsave(&vector_lock, flags);
386 clear_irq_vector(irqd);
387 if (apicd->can_reserve)
388 reserve_irq_vector_locked(irqd);
390 vector_assign_managed_shutdown(irqd);
391 raw_spin_unlock_irqrestore(&vector_lock, flags);
394 static int activate_reserved(struct irq_data *irqd)
396 struct apic_chip_data *apicd = apic_chip_data(irqd);
399 ret = assign_irq_vector_any_locked(irqd);
401 apicd->has_reserved = false;
403 * Core might have disabled reservation mode after
404 * allocating the irq descriptor. Ideally this should
405 * happen before allocation time, but that would require
406 * completely convoluted ways of transporting that
409 if (!irqd_can_reserve(irqd))
410 apicd->can_reserve = false;
415 static int activate_managed(struct irq_data *irqd)
417 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
420 cpumask_and(vector_searchmask, dest, cpu_online_mask);
421 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
422 /* Something in the core code broke! Survive gracefully */
423 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
427 ret = assign_managed_vector(irqd, vector_searchmask);
429 * This should not happen. The vector reservation got buggered. Handle
432 if (WARN_ON_ONCE(ret < 0)) {
433 pr_err("Managed startup irq %u, no vector available\n",
439 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
442 struct apic_chip_data *apicd = apic_chip_data(irqd);
446 trace_vector_activate(irqd->irq, apicd->is_managed,
447 apicd->can_reserve, reserve);
449 /* Nothing to do for fixed assigned vectors */
450 if (!apicd->can_reserve && !apicd->is_managed)
453 raw_spin_lock_irqsave(&vector_lock, flags);
454 if (reserve || irqd_is_managed_and_shutdown(irqd))
455 vector_assign_managed_shutdown(irqd);
456 else if (apicd->is_managed)
457 ret = activate_managed(irqd);
458 else if (apicd->has_reserved)
459 ret = activate_reserved(irqd);
460 raw_spin_unlock_irqrestore(&vector_lock, flags);
464 static void vector_free_reserved_and_managed(struct irq_data *irqd)
466 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
467 struct apic_chip_data *apicd = apic_chip_data(irqd);
469 trace_vector_teardown(irqd->irq, apicd->is_managed,
470 apicd->has_reserved);
472 if (apicd->has_reserved)
473 irq_matrix_remove_reserved(vector_matrix);
474 if (apicd->is_managed)
475 irq_matrix_remove_managed(vector_matrix, dest);
478 static void x86_vector_free_irqs(struct irq_domain *domain,
479 unsigned int virq, unsigned int nr_irqs)
481 struct apic_chip_data *apicd;
482 struct irq_data *irqd;
486 for (i = 0; i < nr_irqs; i++) {
487 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
488 if (irqd && irqd->chip_data) {
489 raw_spin_lock_irqsave(&vector_lock, flags);
490 clear_irq_vector(irqd);
491 vector_free_reserved_and_managed(irqd);
492 apicd = irqd->chip_data;
493 irq_domain_reset_irq_data(irqd);
494 raw_spin_unlock_irqrestore(&vector_lock, flags);
495 free_apic_chip_data(apicd);
500 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
501 struct apic_chip_data *apicd)
504 bool realloc = false;
506 apicd->vector = ISA_IRQ_VECTOR(virq);
509 raw_spin_lock_irqsave(&vector_lock, flags);
511 * If the interrupt is activated, then it must stay at this vector
512 * position. That's usually the timer interrupt (0).
514 if (irqd_is_activated(irqd)) {
515 trace_vector_setup(virq, true, 0);
516 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
518 /* Release the vector */
519 apicd->can_reserve = true;
520 irqd_set_can_reserve(irqd);
521 clear_irq_vector(irqd);
524 raw_spin_unlock_irqrestore(&vector_lock, flags);
528 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
529 unsigned int nr_irqs, void *arg)
531 struct irq_alloc_info *info = arg;
532 struct apic_chip_data *apicd;
533 struct irq_data *irqd;
539 /* Currently vector allocator can't guarantee contiguous allocations */
540 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
543 for (i = 0; i < nr_irqs; i++) {
544 irqd = irq_domain_get_irq_data(domain, virq + i);
546 node = irq_data_get_node(irqd);
547 WARN_ON_ONCE(irqd->chip_data);
548 apicd = alloc_apic_chip_data(node);
554 apicd->irq = virq + i;
555 irqd->chip = &lapic_controller;
556 irqd->chip_data = apicd;
557 irqd->hwirq = virq + i;
558 irqd_set_single_target(irqd);
560 * Legacy vectors are already assigned when the IOAPIC
561 * takes them over. They stay on the same vector. This is
562 * required for check_timer() to work correctly as it might
563 * switch back to legacy mode. Only update the hardware
566 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
567 if (!vector_configure_legacy(virq + i, irqd, apicd))
571 err = assign_irq_vector_policy(irqd, info);
572 trace_vector_setup(virq + i, false, err);
574 irqd->chip_data = NULL;
575 free_apic_chip_data(apicd);
583 x86_vector_free_irqs(domain, virq, i);
587 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
588 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
589 struct irq_data *irqd, int ind)
591 unsigned int cpu, vector, prev_cpu, prev_vector;
592 struct apic_chip_data *apicd;
597 irq_matrix_debug_show(m, vector_matrix, ind);
602 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
603 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
604 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
608 apicd = irqd->chip_data;
610 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
614 raw_spin_lock_irqsave(&vector_lock, flags);
616 vector = apicd->vector;
617 prev_cpu = apicd->prev_cpu;
618 prev_vector = apicd->prev_vector;
619 raw_spin_unlock_irqrestore(&vector_lock, flags);
620 seq_printf(m, "%*sVector: %5u\n", ind, "", vector);
621 seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu);
623 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector);
624 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu);
629 static const struct irq_domain_ops x86_vector_domain_ops = {
630 .alloc = x86_vector_alloc_irqs,
631 .free = x86_vector_free_irqs,
632 .activate = x86_vector_activate,
633 .deactivate = x86_vector_deactivate,
634 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
635 .debug_show = x86_vector_debug_show,
639 int __init arch_probe_nr_irqs(void)
643 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
644 nr_irqs = NR_VECTORS * nr_cpu_ids;
646 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
647 #if defined(CONFIG_PCI_MSI)
649 * for MSI and HT dyn irq
651 if (gsi_top <= NR_IRQS_LEGACY)
652 nr += 8 * nr_cpu_ids;
660 * We don't know if PIC is present at this point so we need to do
661 * probe() to get the right number of legacy IRQs.
663 return legacy_pic->probe();
666 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
669 * Use assign system here so it wont get accounted as allocated
670 * and moveable in the cpu hotplug check and it prevents managed
671 * irq reservation from touching it.
673 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
676 void __init lapic_assign_system_vectors(void)
678 unsigned int i, vector = 0;
680 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
681 irq_matrix_assign_system(vector_matrix, vector, false);
683 if (nr_legacy_irqs() > 1)
684 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
686 /* System vectors are reserved, online it */
687 irq_matrix_online(vector_matrix);
689 /* Mark the preallocated legacy interrupts */
690 for (i = 0; i < nr_legacy_irqs(); i++) {
691 if (i != PIC_CASCADE_IR)
692 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
696 int __init arch_early_irq_init(void)
698 struct fwnode_handle *fn;
700 fn = irq_domain_alloc_named_fwnode("VECTOR");
702 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
704 BUG_ON(x86_vector_domain == NULL);
705 irq_domain_free_fwnode(fn);
706 irq_set_default_host(x86_vector_domain);
708 arch_init_msi_domain(x86_vector_domain);
710 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
713 * Allocate the vector matrix allocator data structure and limit the
716 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
717 FIRST_SYSTEM_VECTOR);
718 BUG_ON(!vector_matrix);
720 return arch_early_ioapic_init();
725 static struct irq_desc *__setup_vector_irq(int vector)
727 int isairq = vector - ISA_IRQ_VECTOR(0);
729 /* Check whether the irq is in the legacy space */
730 if (isairq < 0 || isairq >= nr_legacy_irqs())
731 return VECTOR_UNUSED;
732 /* Check whether the irq is handled by the IOAPIC */
733 if (test_bit(isairq, &io_apic_irqs))
734 return VECTOR_UNUSED;
735 return irq_to_desc(isairq);
738 /* Online the local APIC infrastructure and initialize the vectors */
739 void lapic_online(void)
743 lockdep_assert_held(&vector_lock);
745 /* Online the vector matrix array for this CPU */
746 irq_matrix_online(vector_matrix);
749 * The interrupt affinity logic never targets interrupts to offline
750 * CPUs. The exception are the legacy PIC interrupts. In general
751 * they are only targeted to CPU0, but depending on the platform
752 * they can be distributed to any online CPU in hardware. The
753 * kernel has no influence on that. So all active legacy vectors
754 * must be installed on all CPUs. All non legacy interrupts can be
757 for (vector = 0; vector < NR_VECTORS; vector++)
758 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
761 void lapic_offline(void)
764 irq_matrix_offline(vector_matrix);
765 unlock_vector_lock();
768 static int apic_set_affinity(struct irq_data *irqd,
769 const struct cpumask *dest, bool force)
771 struct apic_chip_data *apicd = apic_chip_data(irqd);
775 * Core code can call here for inactive interrupts. For inactive
776 * interrupts which use managed or reservation mode there is no
777 * point in going through the vector assignment right now as the
778 * activation will assign a vector which fits the destination
779 * cpumask. Let the core code store the destination mask and be
782 if (!irqd_is_activated(irqd) &&
783 (apicd->is_managed || apicd->can_reserve))
784 return IRQ_SET_MASK_OK;
786 raw_spin_lock(&vector_lock);
787 cpumask_and(vector_searchmask, dest, cpu_online_mask);
788 if (irqd_affinity_is_managed(irqd))
789 err = assign_managed_vector(irqd, vector_searchmask);
791 err = assign_vector_locked(irqd, vector_searchmask);
792 raw_spin_unlock(&vector_lock);
793 return err ? err : IRQ_SET_MASK_OK;
797 # define apic_set_affinity NULL
800 static int apic_retrigger_irq(struct irq_data *irqd)
802 struct apic_chip_data *apicd = apic_chip_data(irqd);
805 raw_spin_lock_irqsave(&vector_lock, flags);
806 apic->send_IPI(apicd->cpu, apicd->vector);
807 raw_spin_unlock_irqrestore(&vector_lock, flags);
812 void apic_ack_irq(struct irq_data *irqd)
818 void apic_ack_edge(struct irq_data *irqd)
820 irq_complete_move(irqd_cfg(irqd));
824 static struct irq_chip lapic_controller = {
826 .irq_ack = apic_ack_edge,
827 .irq_set_affinity = apic_set_affinity,
828 .irq_retrigger = apic_retrigger_irq,
833 static void free_moved_vector(struct apic_chip_data *apicd)
835 unsigned int vector = apicd->prev_vector;
836 unsigned int cpu = apicd->prev_cpu;
837 bool managed = apicd->is_managed;
840 * This should never happen. Managed interrupts are not
841 * migrated except on CPU down, which does not involve the
842 * cleanup vector. But try to keep the accounting correct
845 WARN_ON_ONCE(managed);
847 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
848 irq_matrix_free(vector_matrix, cpu, vector, managed);
849 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
850 hlist_del_init(&apicd->clist);
851 apicd->prev_vector = 0;
852 apicd->move_in_progress = 0;
855 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
857 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
858 struct apic_chip_data *apicd;
859 struct hlist_node *tmp;
862 /* Prevent vectors vanishing under us */
863 raw_spin_lock(&vector_lock);
865 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
866 unsigned int irr, vector = apicd->prev_vector;
869 * Paranoia: Check if the vector that needs to be cleaned
870 * up is registered at the APICs IRR. If so, then this is
871 * not the best time to clean it up. Clean it up in the
872 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
873 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
874 * priority external vector, so on return from this
875 * interrupt the device interrupt will happen first.
877 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
878 if (irr & (1U << (vector % 32))) {
879 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
882 free_moved_vector(apicd);
885 raw_spin_unlock(&vector_lock);
889 static void __send_cleanup_vector(struct apic_chip_data *apicd)
893 raw_spin_lock(&vector_lock);
894 apicd->move_in_progress = 0;
895 cpu = apicd->prev_cpu;
896 if (cpu_online(cpu)) {
897 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
898 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
900 apicd->prev_vector = 0;
902 raw_spin_unlock(&vector_lock);
905 void send_cleanup_vector(struct irq_cfg *cfg)
907 struct apic_chip_data *apicd;
909 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
910 if (apicd->move_in_progress)
911 __send_cleanup_vector(apicd);
914 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
916 struct apic_chip_data *apicd;
918 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
919 if (likely(!apicd->move_in_progress))
922 if (vector == apicd->vector && apicd->cpu == smp_processor_id())
923 __send_cleanup_vector(apicd);
926 void irq_complete_move(struct irq_cfg *cfg)
928 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
932 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
934 void irq_force_complete_move(struct irq_desc *desc)
936 struct apic_chip_data *apicd;
937 struct irq_data *irqd;
941 * The function is called for all descriptors regardless of which
942 * irqdomain they belong to. For example if an IRQ is provided by
943 * an irq_chip as part of a GPIO driver, the chip data for that
944 * descriptor is specific to the irq_chip in question.
946 * Check first that the chip_data is what we expect
947 * (apic_chip_data) before touching it any further.
949 irqd = irq_domain_get_irq_data(x86_vector_domain,
950 irq_desc_get_irq(desc));
954 raw_spin_lock(&vector_lock);
955 apicd = apic_chip_data(irqd);
960 * If prev_vector is empty, no action required.
962 vector = apicd->prev_vector;
967 * This is tricky. If the cleanup of the old vector has not been
968 * done yet, then the following setaffinity call will fail with
969 * -EBUSY. This can leave the interrupt in a stale state.
971 * All CPUs are stuck in stop machine with interrupts disabled so
972 * calling __irq_complete_move() would be completely pointless.
974 * 1) The interrupt is in move_in_progress state. That means that we
975 * have not seen an interrupt since the io_apic was reprogrammed to
978 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
979 * have not been processed yet.
981 if (apicd->move_in_progress) {
983 * In theory there is a race:
985 * set_ioapic(new_vector) <-- Interrupt is raised before update
986 * is effective, i.e. it's raised on
989 * So if the target cpu cannot handle that interrupt before
990 * the old vector is cleaned up, we get a spurious interrupt
991 * and in the worst case the ioapic irq line becomes stale.
993 * But in case of cpu hotplug this should be a non issue
994 * because if the affinity update happens right before all
995 * cpus rendevouz in stop machine, there is no way that the
996 * interrupt can be blocked on the target cpu because all cpus
997 * loops first with interrupts enabled in stop machine, so the
998 * old vector is not yet cleaned up when the interrupt fires.
1000 * So the only way to run into this issue is if the delivery
1001 * of the interrupt on the apic/system bus would be delayed
1002 * beyond the point where the target cpu disables interrupts
1003 * in stop machine. I doubt that it can happen, but at least
1004 * there is a theroretical chance. Virtualization might be
1005 * able to expose this, but AFAICT the IOAPIC emulation is not
1006 * as stupid as the real hardware.
1008 * Anyway, there is nothing we can do about that at this point
1009 * w/o refactoring the whole fixup_irq() business completely.
1010 * We print at least the irq number and the old vector number,
1011 * so we have the necessary information when a problem in that
1014 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1017 free_moved_vector(apicd);
1019 raw_spin_unlock(&vector_lock);
1022 #ifdef CONFIG_HOTPLUG_CPU
1024 * Note, this is not accurate accounting, but at least good enough to
1025 * prevent that the actual interrupt move will run out of vectors.
1027 int lapic_can_unplug_cpu(void)
1029 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1032 raw_spin_lock(&vector_lock);
1033 tomove = irq_matrix_allocated(vector_matrix);
1034 avl = irq_matrix_available(vector_matrix, true);
1036 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1041 rsvd = irq_matrix_reserved(vector_matrix);
1043 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1047 raw_spin_unlock(&vector_lock);
1050 #endif /* HOTPLUG_CPU */
1053 static void __init print_APIC_field(int base)
1059 for (i = 0; i < 8; i++)
1060 pr_cont("%08x", apic_read(base + i*0x10));
1065 static void __init print_local_APIC(void *dummy)
1067 unsigned int i, v, ver, maxlvt;
1070 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1071 smp_processor_id(), hard_smp_processor_id());
1072 v = apic_read(APIC_ID);
1073 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1074 v = apic_read(APIC_LVR);
1075 pr_info("... APIC VERSION: %08x\n", v);
1076 ver = GET_APIC_VERSION(v);
1077 maxlvt = lapic_get_maxlvt();
1079 v = apic_read(APIC_TASKPRI);
1080 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1083 if (APIC_INTEGRATED(ver)) {
1084 if (!APIC_XAPIC(ver)) {
1085 v = apic_read(APIC_ARBPRI);
1086 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1087 v, v & APIC_ARBPRI_MASK);
1089 v = apic_read(APIC_PROCPRI);
1090 pr_debug("... APIC PROCPRI: %08x\n", v);
1094 * Remote read supported only in the 82489DX and local APIC for
1095 * Pentium processors.
1097 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1098 v = apic_read(APIC_RRR);
1099 pr_debug("... APIC RRR: %08x\n", v);
1102 v = apic_read(APIC_LDR);
1103 pr_debug("... APIC LDR: %08x\n", v);
1104 if (!x2apic_enabled()) {
1105 v = apic_read(APIC_DFR);
1106 pr_debug("... APIC DFR: %08x\n", v);
1108 v = apic_read(APIC_SPIV);
1109 pr_debug("... APIC SPIV: %08x\n", v);
1111 pr_debug("... APIC ISR field:\n");
1112 print_APIC_field(APIC_ISR);
1113 pr_debug("... APIC TMR field:\n");
1114 print_APIC_field(APIC_TMR);
1115 pr_debug("... APIC IRR field:\n");
1116 print_APIC_field(APIC_IRR);
1119 if (APIC_INTEGRATED(ver)) {
1120 /* Due to the Pentium erratum 3AP. */
1122 apic_write(APIC_ESR, 0);
1124 v = apic_read(APIC_ESR);
1125 pr_debug("... APIC ESR: %08x\n", v);
1128 icr = apic_icr_read();
1129 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1130 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1132 v = apic_read(APIC_LVTT);
1133 pr_debug("... APIC LVTT: %08x\n", v);
1137 v = apic_read(APIC_LVTPC);
1138 pr_debug("... APIC LVTPC: %08x\n", v);
1140 v = apic_read(APIC_LVT0);
1141 pr_debug("... APIC LVT0: %08x\n", v);
1142 v = apic_read(APIC_LVT1);
1143 pr_debug("... APIC LVT1: %08x\n", v);
1147 v = apic_read(APIC_LVTERR);
1148 pr_debug("... APIC LVTERR: %08x\n", v);
1151 v = apic_read(APIC_TMICT);
1152 pr_debug("... APIC TMICT: %08x\n", v);
1153 v = apic_read(APIC_TMCCT);
1154 pr_debug("... APIC TMCCT: %08x\n", v);
1155 v = apic_read(APIC_TDCR);
1156 pr_debug("... APIC TDCR: %08x\n", v);
1158 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1159 v = apic_read(APIC_EFEAT);
1160 maxlvt = (v >> 16) & 0xff;
1161 pr_debug("... APIC EFEAT: %08x\n", v);
1162 v = apic_read(APIC_ECTRL);
1163 pr_debug("... APIC ECTRL: %08x\n", v);
1164 for (i = 0; i < maxlvt; i++) {
1165 v = apic_read(APIC_EILVTn(i));
1166 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1172 static void __init print_local_APICs(int maxcpu)
1180 for_each_online_cpu(cpu) {
1183 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1188 static void __init print_PIC(void)
1191 unsigned long flags;
1193 if (!nr_legacy_irqs())
1196 pr_debug("\nprinting PIC contents\n");
1198 raw_spin_lock_irqsave(&i8259A_lock, flags);
1200 v = inb(0xa1) << 8 | inb(0x21);
1201 pr_debug("... PIC IMR: %04x\n", v);
1203 v = inb(0xa0) << 8 | inb(0x20);
1204 pr_debug("... PIC IRR: %04x\n", v);
1208 v = inb(0xa0) << 8 | inb(0x20);
1212 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1214 pr_debug("... PIC ISR: %04x\n", v);
1216 v = inb(0x4d1) << 8 | inb(0x4d0);
1217 pr_debug("... PIC ELCR: %04x\n", v);
1220 static int show_lapic __initdata = 1;
1221 static __init int setup_show_lapic(char *arg)
1225 if (strcmp(arg, "all") == 0) {
1226 show_lapic = CONFIG_NR_CPUS;
1228 get_option(&arg, &num);
1235 __setup("show_lapic=", setup_show_lapic);
1237 static int __init print_ICs(void)
1239 if (apic_verbosity == APIC_QUIET)
1244 /* don't print out if apic is not there */
1245 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1248 print_local_APICs(show_lapic);
1254 late_initcall(print_ICs);