1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
19 #include <asm/spec-ctrl.h>
20 #include <asm/cmdline.h>
22 #include <asm/processor.h>
23 #include <asm/processor-flags.h>
24 #include <asm/fpu/internal.h>
27 #include <asm/paravirt.h>
28 #include <asm/alternative.h>
29 #include <asm/pgtable.h>
30 #include <asm/set_memory.h>
31 #include <asm/intel-family.h>
32 #include <asm/e820/api.h>
33 #include <asm/hypervisor.h>
35 static void __init spectre_v2_select_mitigation(void);
36 static void __init ssb_select_mitigation(void);
37 static void __init l1tf_select_mitigation(void);
39 /* The base value of the SPEC_CTRL MSR that always has to be preserved. */
40 u64 x86_spec_ctrl_base;
41 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
42 static DEFINE_MUTEX(spec_ctrl_mutex);
45 * The vendor and possibly platform specific bits which can be modified in
48 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
51 * AMD specific MSR info for Speculative Store Bypass control.
52 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
54 u64 __ro_after_init x86_amd_ls_cfg_base;
55 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
57 void __init check_bugs(void)
62 * identify_boot_cpu() initialized SMT support information, let the
65 cpu_smt_check_topology_early();
67 if (!IS_ENABLED(CONFIG_SMP)) {
69 print_cpu_info(&boot_cpu_data);
73 * Read the SPEC_CTRL MSR to account for reserved bits which may
74 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
75 * init code as it is not enumerated and depends on the family.
77 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
78 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
80 /* Allow STIBP in MSR_SPEC_CTRL if supported */
81 if (boot_cpu_has(X86_FEATURE_STIBP))
82 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
84 /* Select the proper spectre mitigation before patching alternatives */
85 spectre_v2_select_mitigation();
88 * Select proper mitigation for any exposure to the Speculative Store
89 * Bypass vulnerability.
91 ssb_select_mitigation();
93 l1tf_select_mitigation();
97 * Check whether we are able to run this kernel safely on SMP.
99 * - i386 is no longer supported.
100 * - In order to run on anything without a TSC, we need to be
101 * compiled for a i486.
103 if (boot_cpu_data.x86 < 4)
104 panic("Kernel requires i486+ for 'invlpg' and other features");
106 init_utsname()->machine[1] =
107 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
108 alternative_instructions();
110 fpu__init_check_bugs();
111 #else /* CONFIG_X86_64 */
112 alternative_instructions();
115 * Make sure the first 2MB area is not mapped by huge pages
116 * There are typically fixed size MTRRs in there and overlapping
117 * MTRRs into large pages causes slow downs.
119 * Right now we don't do that with gbpages because there seems
120 * very little benefit for that case.
123 set_memory_4k((unsigned long)__va(0), 1);
128 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
130 u64 msrval, guestval, hostval = x86_spec_ctrl_base;
131 struct thread_info *ti = current_thread_info();
133 /* Is MSR_SPEC_CTRL implemented ? */
134 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
136 * Restrict guest_spec_ctrl to supported values. Clear the
137 * modifiable bits in the host base value and or the
138 * modifiable bits from the guest value.
140 guestval = hostval & ~x86_spec_ctrl_mask;
141 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
143 /* SSBD controlled in MSR_SPEC_CTRL */
144 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
145 static_cpu_has(X86_FEATURE_AMD_SSBD))
146 hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
148 if (hostval != guestval) {
149 msrval = setguest ? guestval : hostval;
150 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
155 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
156 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
158 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
159 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
163 * If the host has SSBD mitigation enabled, force it in the host's
164 * virtual MSR value. If its not permanently enabled, evaluate
165 * current's TIF_SSBD thread flag.
167 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
168 hostval = SPEC_CTRL_SSBD;
170 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
172 /* Sanitize the guest value */
173 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
175 if (hostval != guestval) {
178 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
179 ssbd_spec_ctrl_to_tif(hostval);
181 speculation_ctrl_update(tif);
184 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
186 static void x86_amd_ssb_disable(void)
188 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
190 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
191 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
192 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
193 wrmsrl(MSR_AMD64_LS_CFG, msrval);
197 #define pr_fmt(fmt) "Spectre V2 : " fmt
199 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
203 static bool spectre_v2_bad_module;
205 bool retpoline_module_ok(bool has_retpoline)
207 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
210 pr_err("System may be vulnerable to spectre v2\n");
211 spectre_v2_bad_module = true;
215 static inline const char *spectre_v2_module_string(void)
217 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
220 static inline const char *spectre_v2_module_string(void) { return ""; }
223 static inline bool match_option(const char *arg, int arglen, const char *opt)
225 int len = strlen(opt);
227 return len == arglen && !strncmp(arg, opt, len);
230 /* The kernel command line selection for spectre v2 */
231 enum spectre_v2_mitigation_cmd {
234 SPECTRE_V2_CMD_FORCE,
235 SPECTRE_V2_CMD_RETPOLINE,
236 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
237 SPECTRE_V2_CMD_RETPOLINE_AMD,
240 static const char * const spectre_v2_strings[] = {
241 [SPECTRE_V2_NONE] = "Vulnerable",
242 [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
243 [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
244 [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS",
247 static const struct {
249 enum spectre_v2_mitigation_cmd cmd;
251 } mitigation_options[] __initdata = {
252 { "off", SPECTRE_V2_CMD_NONE, false },
253 { "on", SPECTRE_V2_CMD_FORCE, true },
254 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
255 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
256 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
257 { "auto", SPECTRE_V2_CMD_AUTO, false },
260 static void __init spec_v2_print_cond(const char *reason, bool secure)
262 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
263 pr_info("%s selected on command line.\n", reason);
266 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
268 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
272 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
273 return SPECTRE_V2_CMD_NONE;
275 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
277 return SPECTRE_V2_CMD_AUTO;
279 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
280 if (!match_option(arg, ret, mitigation_options[i].option))
282 cmd = mitigation_options[i].cmd;
286 if (i >= ARRAY_SIZE(mitigation_options)) {
287 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
288 return SPECTRE_V2_CMD_AUTO;
291 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
292 cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
293 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
294 !IS_ENABLED(CONFIG_RETPOLINE)) {
295 pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
296 return SPECTRE_V2_CMD_AUTO;
299 if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
300 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
301 boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
302 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
303 return SPECTRE_V2_CMD_AUTO;
306 spec_v2_print_cond(mitigation_options[i].option,
307 mitigation_options[i].secure);
311 static void __init spectre_v2_select_mitigation(void)
313 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
314 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
317 * If the CPU is not affected and the command line mode is NONE or AUTO
318 * then nothing to do.
320 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
321 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
325 case SPECTRE_V2_CMD_NONE:
328 case SPECTRE_V2_CMD_FORCE:
329 case SPECTRE_V2_CMD_AUTO:
330 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
331 mode = SPECTRE_V2_IBRS_ENHANCED;
332 /* Force it so VMEXIT will restore correctly */
333 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
334 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
335 goto specv2_set_mode;
337 if (IS_ENABLED(CONFIG_RETPOLINE))
340 case SPECTRE_V2_CMD_RETPOLINE_AMD:
341 if (IS_ENABLED(CONFIG_RETPOLINE))
344 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
345 if (IS_ENABLED(CONFIG_RETPOLINE))
346 goto retpoline_generic;
348 case SPECTRE_V2_CMD_RETPOLINE:
349 if (IS_ENABLED(CONFIG_RETPOLINE))
353 pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
357 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
358 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
360 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
361 pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
362 goto retpoline_generic;
364 mode = SPECTRE_V2_RETPOLINE_AMD;
365 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
366 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
369 mode = SPECTRE_V2_RETPOLINE_GENERIC;
370 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
374 spectre_v2_enabled = mode;
375 pr_info("%s\n", spectre_v2_strings[mode]);
378 * If spectre v2 protection has been enabled, unconditionally fill
379 * RSB during a context switch; this protects against two independent
382 * - RSB underflow (and switch to BTB) on Skylake+
383 * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
385 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
386 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
388 /* Initialize Indirect Branch Prediction Barrier if supported */
389 if (boot_cpu_has(X86_FEATURE_IBPB)) {
390 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
391 pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
395 * Retpoline means the kernel is safe because it has no indirect
396 * branches. Enhanced IBRS protects firmware too, so, enable restricted
397 * speculation around firmware calls only when Enhanced IBRS isn't
400 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
401 * the user might select retpoline on the kernel command line and if
402 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
403 * enable IBRS around firmware calls.
405 if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
406 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
407 pr_info("Enabling Restricted Speculation for firmware calls\n");
410 /* Enable STIBP if appropriate */
414 static bool stibp_needed(void)
416 if (spectre_v2_enabled == SPECTRE_V2_NONE)
419 /* Enhanced IBRS makes using STIBP unnecessary. */
420 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
423 if (!boot_cpu_has(X86_FEATURE_STIBP))
429 static void update_stibp_msr(void *info)
431 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
434 void arch_smt_update(void)
441 mutex_lock(&spec_ctrl_mutex);
443 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
444 if (sched_smt_active())
445 mask |= SPEC_CTRL_STIBP;
447 if (mask != x86_spec_ctrl_base) {
448 pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
449 mask & SPEC_CTRL_STIBP ? "Enabling" : "Disabling");
450 x86_spec_ctrl_base = mask;
451 on_each_cpu(update_stibp_msr, NULL, 1);
453 mutex_unlock(&spec_ctrl_mutex);
457 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
459 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
461 /* The kernel command line selection */
462 enum ssb_mitigation_cmd {
463 SPEC_STORE_BYPASS_CMD_NONE,
464 SPEC_STORE_BYPASS_CMD_AUTO,
465 SPEC_STORE_BYPASS_CMD_ON,
466 SPEC_STORE_BYPASS_CMD_PRCTL,
467 SPEC_STORE_BYPASS_CMD_SECCOMP,
470 static const char * const ssb_strings[] = {
471 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
472 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
473 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
474 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
477 static const struct {
479 enum ssb_mitigation_cmd cmd;
480 } ssb_mitigation_options[] __initdata = {
481 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
482 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
483 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
484 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
485 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
488 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
490 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
494 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
495 return SPEC_STORE_BYPASS_CMD_NONE;
497 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
500 return SPEC_STORE_BYPASS_CMD_AUTO;
502 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
503 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
506 cmd = ssb_mitigation_options[i].cmd;
510 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
511 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
512 return SPEC_STORE_BYPASS_CMD_AUTO;
519 static enum ssb_mitigation __init __ssb_select_mitigation(void)
521 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
522 enum ssb_mitigation_cmd cmd;
524 if (!boot_cpu_has(X86_FEATURE_SSBD))
527 cmd = ssb_parse_cmdline();
528 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
529 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
530 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
534 case SPEC_STORE_BYPASS_CMD_AUTO:
535 case SPEC_STORE_BYPASS_CMD_SECCOMP:
537 * Choose prctl+seccomp as the default mode if seccomp is
540 if (IS_ENABLED(CONFIG_SECCOMP))
541 mode = SPEC_STORE_BYPASS_SECCOMP;
543 mode = SPEC_STORE_BYPASS_PRCTL;
545 case SPEC_STORE_BYPASS_CMD_ON:
546 mode = SPEC_STORE_BYPASS_DISABLE;
548 case SPEC_STORE_BYPASS_CMD_PRCTL:
549 mode = SPEC_STORE_BYPASS_PRCTL;
551 case SPEC_STORE_BYPASS_CMD_NONE:
556 * We have three CPU feature flags that are in play here:
557 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
558 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
559 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
561 if (mode == SPEC_STORE_BYPASS_DISABLE) {
562 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
564 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
565 * use a completely different MSR and bit dependent on family.
567 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
568 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
569 x86_amd_ssb_disable();
571 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
572 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
573 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
580 static void ssb_select_mitigation(void)
582 ssb_mode = __ssb_select_mitigation();
584 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
585 pr_info("%s\n", ssb_strings[ssb_mode]);
589 #define pr_fmt(fmt) "Speculation prctl: " fmt
591 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
595 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
596 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
601 /* If speculation is force disabled, enable is not allowed */
602 if (task_spec_ssb_force_disable(task))
604 task_clear_spec_ssb_disable(task);
605 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
607 case PR_SPEC_DISABLE:
608 task_set_spec_ssb_disable(task);
609 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
611 case PR_SPEC_FORCE_DISABLE:
612 task_set_spec_ssb_disable(task);
613 task_set_spec_ssb_force_disable(task);
614 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
621 * If being set on non-current task, delay setting the CPU
622 * mitigation until it is next scheduled.
624 if (task == current && update)
625 speculation_ctrl_update_current();
630 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
634 case PR_SPEC_STORE_BYPASS:
635 return ssb_prctl_set(task, ctrl);
641 #ifdef CONFIG_SECCOMP
642 void arch_seccomp_spec_mitigate(struct task_struct *task)
644 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
645 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
649 static int ssb_prctl_get(struct task_struct *task)
652 case SPEC_STORE_BYPASS_DISABLE:
653 return PR_SPEC_DISABLE;
654 case SPEC_STORE_BYPASS_SECCOMP:
655 case SPEC_STORE_BYPASS_PRCTL:
656 if (task_spec_ssb_force_disable(task))
657 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
658 if (task_spec_ssb_disable(task))
659 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
660 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
662 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
663 return PR_SPEC_ENABLE;
664 return PR_SPEC_NOT_AFFECTED;
668 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
671 case PR_SPEC_STORE_BYPASS:
672 return ssb_prctl_get(task);
678 void x86_spec_ctrl_setup_ap(void)
680 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
681 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
683 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
684 x86_amd_ssb_disable();
688 #define pr_fmt(fmt) "L1TF: " fmt
690 /* Default mitigation for L1TF-affected CPUs */
691 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
692 #if IS_ENABLED(CONFIG_KVM_INTEL)
693 EXPORT_SYMBOL_GPL(l1tf_mitigation);
695 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
696 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
699 * These CPUs all support 44bits physical address space internally in the
700 * cache but CPUID can report a smaller number of physical address bits.
702 * The L1TF mitigation uses the top most address bit for the inversion of
703 * non present PTEs. When the installed memory reaches into the top most
704 * address bit due to memory holes, which has been observed on machines
705 * which report 36bits physical address bits and have 32G RAM installed,
706 * then the mitigation range check in l1tf_select_mitigation() triggers.
707 * This is a false positive because the mitigation is still possible due to
708 * the fact that the cache uses 44bit internally. Use the cache bits
709 * instead of the reported physical bits and adjust them on the affected
710 * machines to 44bit if the reported bits are less than 44.
712 static void override_cache_bits(struct cpuinfo_x86 *c)
717 switch (c->x86_model) {
718 case INTEL_FAM6_NEHALEM:
719 case INTEL_FAM6_WESTMERE:
720 case INTEL_FAM6_SANDYBRIDGE:
721 case INTEL_FAM6_IVYBRIDGE:
722 case INTEL_FAM6_HASWELL_CORE:
723 case INTEL_FAM6_HASWELL_ULT:
724 case INTEL_FAM6_HASWELL_GT3E:
725 case INTEL_FAM6_BROADWELL_CORE:
726 case INTEL_FAM6_BROADWELL_GT3E:
727 case INTEL_FAM6_SKYLAKE_MOBILE:
728 case INTEL_FAM6_SKYLAKE_DESKTOP:
729 case INTEL_FAM6_KABYLAKE_MOBILE:
730 case INTEL_FAM6_KABYLAKE_DESKTOP:
731 if (c->x86_cache_bits < 44)
732 c->x86_cache_bits = 44;
737 static void __init l1tf_select_mitigation(void)
741 if (!boot_cpu_has_bug(X86_BUG_L1TF))
744 override_cache_bits(&boot_cpu_data);
746 switch (l1tf_mitigation) {
747 case L1TF_MITIGATION_OFF:
748 case L1TF_MITIGATION_FLUSH_NOWARN:
749 case L1TF_MITIGATION_FLUSH:
751 case L1TF_MITIGATION_FLUSH_NOSMT:
752 case L1TF_MITIGATION_FULL:
753 cpu_smt_disable(false);
755 case L1TF_MITIGATION_FULL_FORCE:
756 cpu_smt_disable(true);
760 #if CONFIG_PGTABLE_LEVELS == 2
761 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
765 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
766 if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
767 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
768 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
770 pr_info("However, doing so will make a part of your RAM unusable.\n");
771 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
775 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
778 static int __init l1tf_cmdline(char *str)
780 if (!boot_cpu_has_bug(X86_BUG_L1TF))
786 if (!strcmp(str, "off"))
787 l1tf_mitigation = L1TF_MITIGATION_OFF;
788 else if (!strcmp(str, "flush,nowarn"))
789 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
790 else if (!strcmp(str, "flush"))
791 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
792 else if (!strcmp(str, "flush,nosmt"))
793 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
794 else if (!strcmp(str, "full"))
795 l1tf_mitigation = L1TF_MITIGATION_FULL;
796 else if (!strcmp(str, "full,force"))
797 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
801 early_param("l1tf", l1tf_cmdline);
807 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
809 #if IS_ENABLED(CONFIG_KVM_INTEL)
810 static const char * const l1tf_vmx_states[] = {
811 [VMENTER_L1D_FLUSH_AUTO] = "auto",
812 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
813 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
814 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
815 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
816 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
819 static ssize_t l1tf_show_state(char *buf)
821 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
822 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
824 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
825 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
826 sched_smt_active())) {
827 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
828 l1tf_vmx_states[l1tf_vmx_mitigation]);
831 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
832 l1tf_vmx_states[l1tf_vmx_mitigation],
833 sched_smt_active() ? "vulnerable" : "disabled");
836 static ssize_t l1tf_show_state(char *buf)
838 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
842 static char *stibp_state(void)
844 if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
847 if (x86_spec_ctrl_base & SPEC_CTRL_STIBP)
853 static char *ibpb_state(void)
855 if (boot_cpu_has(X86_FEATURE_USE_IBPB))
861 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
862 char *buf, unsigned int bug)
864 if (!boot_cpu_has_bug(bug))
865 return sprintf(buf, "Not affected\n");
868 case X86_BUG_CPU_MELTDOWN:
869 if (boot_cpu_has(X86_FEATURE_PTI))
870 return sprintf(buf, "Mitigation: PTI\n");
872 if (hypervisor_is_type(X86_HYPER_XEN_PV))
873 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
877 case X86_BUG_SPECTRE_V1:
878 return sprintf(buf, "Mitigation: __user pointer sanitization\n");
880 case X86_BUG_SPECTRE_V2:
881 return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
883 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
885 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
886 spectre_v2_module_string());
888 case X86_BUG_SPEC_STORE_BYPASS:
889 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
892 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
893 return l1tf_show_state(buf);
899 return sprintf(buf, "Vulnerable\n");
902 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
904 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
907 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
909 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
912 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
914 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
917 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
919 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
922 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
924 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);