1 /* cpu_feature_enabled() cannot be used this early */
2 #define USE_EARLY_PGTABLE_L5
4 #include <linux/bootmem.h>
5 #include <linux/linkage.h>
6 #include <linux/bitops.h>
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/percpu.h>
10 #include <linux/string.h>
11 #include <linux/ctype.h>
12 #include <linux/delay.h>
13 #include <linux/sched/mm.h>
14 #include <linux/sched/clock.h>
15 #include <linux/sched/task.h>
16 #include <linux/init.h>
17 #include <linux/kprobes.h>
18 #include <linux/kgdb.h>
19 #include <linux/smp.h>
21 #include <linux/syscore_ops.h>
23 #include <asm/stackprotector.h>
24 #include <asm/perf_event.h>
25 #include <asm/mmu_context.h>
26 #include <asm/archrandom.h>
27 #include <asm/hypervisor.h>
28 #include <asm/processor.h>
29 #include <asm/tlbflush.h>
30 #include <asm/debugreg.h>
31 #include <asm/sections.h>
32 #include <asm/vsyscall.h>
33 #include <linux/topology.h>
34 #include <linux/cpumask.h>
35 #include <asm/pgtable.h>
36 #include <linux/atomic.h>
37 #include <asm/proto.h>
38 #include <asm/setup.h>
41 #include <asm/fpu/internal.h>
43 #include <asm/hwcap2.h>
44 #include <linux/numa.h>
51 #include <asm/microcode.h>
52 #include <asm/microcode_intel.h>
53 #include <asm/intel-family.h>
54 #include <asm/cpu_device_id.h>
56 #ifdef CONFIG_X86_LOCAL_APIC
57 #include <asm/uv/uv.h>
62 u32 elf_hwcap2 __read_mostly;
64 /* all of these masks are initialized in setup_cpu_local_masks() */
65 cpumask_var_t cpu_initialized_mask;
66 cpumask_var_t cpu_callout_mask;
67 cpumask_var_t cpu_callin_mask;
69 /* representing cpus for which sibling maps can be computed */
70 cpumask_var_t cpu_sibling_setup_mask;
72 /* Number of siblings per CPU package */
73 int smp_num_siblings = 1;
74 EXPORT_SYMBOL(smp_num_siblings);
76 /* Last level cache ID of each logical CPU */
77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
79 /* correctly size the local cpu masks */
80 void __init setup_cpu_local_masks(void)
82 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
83 alloc_bootmem_cpumask_var(&cpu_callin_mask);
84 alloc_bootmem_cpumask_var(&cpu_callout_mask);
85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
88 static void default_init(struct cpuinfo_x86 *c)
91 cpu_detect_cache_sizes(c);
93 /* Not much we can do here... */
94 /* Check if at least it has cpuid */
95 if (c->cpuid_level == -1) {
96 /* No cpuid. It must be an ancient CPU */
98 strcpy(c->x86_model_id, "486");
100 strcpy(c->x86_model_id, "386");
105 static const struct cpu_dev default_cpu = {
106 .c_init = default_init,
107 .c_vendor = "Unknown",
108 .c_x86_vendor = X86_VENDOR_UNKNOWN,
111 static const struct cpu_dev *this_cpu = &default_cpu;
113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
116 * We need valid kernel segments for data and code in long mode too
117 * IRET will check the segment types kkeil 2000/10/28
118 * Also sysret mandates a special GDT layout
120 * TLS descriptors are currently at a different place compared to i386.
121 * Hopefully nobody expects them at a fixed place (Wine?)
123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 * Segments used for calling PnP BIOS have byte granularity.
136 * They code segments and data segments have fixed 64k limits,
137 * the transfer segment sizes are set at run time.
140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 * The APM segments have byte granularity and their bases
151 * are set at run time. All have 64k limits.
154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 GDT_STACK_CANARY_INIT
165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
167 static int __init x86_mpx_setup(char *s)
169 /* require an exact match without trailing characters */
173 /* do not emit a message if the feature is not present */
174 if (!boot_cpu_has(X86_FEATURE_MPX))
177 setup_clear_cpu_cap(X86_FEATURE_MPX);
178 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
181 __setup("nompx", x86_mpx_setup);
184 static int __init x86_nopcid_setup(char *s)
186 /* nopcid doesn't accept parameters */
190 /* do not emit a message if the feature is not present */
191 if (!boot_cpu_has(X86_FEATURE_PCID))
194 setup_clear_cpu_cap(X86_FEATURE_PCID);
195 pr_info("nopcid: PCID feature disabled\n");
198 early_param("nopcid", x86_nopcid_setup);
201 static int __init x86_noinvpcid_setup(char *s)
203 /* noinvpcid doesn't accept parameters */
207 /* do not emit a message if the feature is not present */
208 if (!boot_cpu_has(X86_FEATURE_INVPCID))
211 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
212 pr_info("noinvpcid: INVPCID feature disabled\n");
215 early_param("noinvpcid", x86_noinvpcid_setup);
218 static int cachesize_override = -1;
219 static int disable_x86_serial_nr = 1;
221 static int __init cachesize_setup(char *str)
223 get_option(&str, &cachesize_override);
226 __setup("cachesize=", cachesize_setup);
228 static int __init x86_sep_setup(char *s)
230 setup_clear_cpu_cap(X86_FEATURE_SEP);
233 __setup("nosep", x86_sep_setup);
235 /* Standard macro to see if a specific flag is changeable */
236 static inline int flag_is_changeable_p(u32 flag)
241 * Cyrix and IDT cpus allow disabling of CPUID
242 * so the code below may return different results
243 * when it is executed before and after enabling
244 * the CPUID. Add "volatile" to not allow gcc to
245 * optimize the subsequent calls to this function.
247 asm volatile ("pushfl \n\t"
258 : "=&r" (f1), "=&r" (f2)
261 return ((f1^f2) & flag) != 0;
264 /* Probe for the CPUID instruction */
265 int have_cpuid_p(void)
267 return flag_is_changeable_p(X86_EFLAGS_ID);
270 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
272 unsigned long lo, hi;
274 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
277 /* Disable processor serial number: */
279 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
281 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
283 pr_notice("CPU serial number disabled.\n");
284 clear_cpu_cap(c, X86_FEATURE_PN);
286 /* Disabling the serial number may affect the cpuid level */
287 c->cpuid_level = cpuid_eax(0);
290 static int __init x86_serial_nr_setup(char *s)
292 disable_x86_serial_nr = 0;
295 __setup("serialnumber", x86_serial_nr_setup);
297 static inline int flag_is_changeable_p(u32 flag)
301 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
306 static __init int setup_disable_smep(char *arg)
308 setup_clear_cpu_cap(X86_FEATURE_SMEP);
309 /* Check for things that depend on SMEP being enabled: */
310 check_mpx_erratum(&boot_cpu_data);
313 __setup("nosmep", setup_disable_smep);
315 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
317 if (cpu_has(c, X86_FEATURE_SMEP))
318 cr4_set_bits(X86_CR4_SMEP);
321 static __init int setup_disable_smap(char *arg)
323 setup_clear_cpu_cap(X86_FEATURE_SMAP);
326 __setup("nosmap", setup_disable_smap);
328 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
330 unsigned long eflags = native_save_fl();
332 /* This should have been cleared long ago */
333 BUG_ON(eflags & X86_EFLAGS_AC);
335 if (cpu_has(c, X86_FEATURE_SMAP)) {
336 #ifdef CONFIG_X86_SMAP
337 cr4_set_bits(X86_CR4_SMAP);
339 cr4_clear_bits(X86_CR4_SMAP);
344 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
346 /* Check the boot processor, plus build option for UMIP. */
347 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
350 /* Check the current processor's cpuid bits. */
351 if (!cpu_has(c, X86_FEATURE_UMIP))
354 cr4_set_bits(X86_CR4_UMIP);
356 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
362 * Make sure UMIP is disabled in case it was enabled in a
363 * previous boot (e.g., via kexec).
365 cr4_clear_bits(X86_CR4_UMIP);
369 * Protection Keys are not available in 32-bit mode.
371 static bool pku_disabled;
373 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
375 /* check the boot processor, plus compile options for PKU: */
376 if (!cpu_feature_enabled(X86_FEATURE_PKU))
378 /* checks the actual processor's cpuid bits: */
379 if (!cpu_has(c, X86_FEATURE_PKU))
384 cr4_set_bits(X86_CR4_PKE);
386 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
387 * cpuid bit to be set. We need to ensure that we
388 * update that bit in this CPU's "cpu_info".
393 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
394 static __init int setup_disable_pku(char *arg)
397 * Do not clear the X86_FEATURE_PKU bit. All of the
398 * runtime checks are against OSPKE so clearing the
401 * This way, we will see "pku" in cpuinfo, but not
402 * "ospke", which is exactly what we want. It shows
403 * that the CPU has PKU, but the OS has not enabled it.
404 * This happens to be exactly how a system would look
405 * if we disabled the config option.
407 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
411 __setup("nopku", setup_disable_pku);
412 #endif /* CONFIG_X86_64 */
415 * Some CPU features depend on higher CPUID levels, which may not always
416 * be available due to CPUID level capping or broken virtualization
417 * software. Add those features to this table to auto-disable them.
419 struct cpuid_dependent_feature {
424 static const struct cpuid_dependent_feature
425 cpuid_dependent_features[] = {
426 { X86_FEATURE_MWAIT, 0x00000005 },
427 { X86_FEATURE_DCA, 0x00000009 },
428 { X86_FEATURE_XSAVE, 0x0000000d },
432 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
434 const struct cpuid_dependent_feature *df;
436 for (df = cpuid_dependent_features; df->feature; df++) {
438 if (!cpu_has(c, df->feature))
441 * Note: cpuid_level is set to -1 if unavailable, but
442 * extended_extended_level is set to 0 if unavailable
443 * and the legitimate extended levels are all negative
444 * when signed; hence the weird messing around with
447 if (!((s32)df->level < 0 ?
448 (u32)df->level > (u32)c->extended_cpuid_level :
449 (s32)df->level > (s32)c->cpuid_level))
452 clear_cpu_cap(c, df->feature);
456 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
457 x86_cap_flag(df->feature), df->level);
462 * Naming convention should be: <Name> [(<Codename>)]
463 * This table only is used unless init_<vendor>() below doesn't set it;
464 * in particular, if CPUID levels 0x80000002..4 are supported, this
468 /* Look up CPU names by table lookup. */
469 static const char *table_lookup_model(struct cpuinfo_x86 *c)
472 const struct legacy_cpu_model_info *info;
474 if (c->x86_model >= 16)
475 return NULL; /* Range check */
480 info = this_cpu->legacy_models;
482 while (info->family) {
483 if (info->family == c->x86)
484 return info->model_names[c->x86_model];
488 return NULL; /* Not found */
491 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
492 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
494 void load_percpu_segment(int cpu)
497 loadsegment(fs, __KERNEL_PERCPU);
499 __loadsegment_simple(gs, 0);
500 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
502 load_stack_canary_segment();
506 /* The 32-bit entry code needs to find cpu_entry_area. */
507 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
512 * Special IST stacks which the CPU switches to when it calls
513 * an IST-marked descriptor entry. Up to 7 stacks (hardware
514 * limit), all of them are 4K, except the debug stack which
517 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
518 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
519 [DEBUG_STACK - 1] = DEBUG_STKSZ
523 /* Load the original GDT from the per-cpu structure */
524 void load_direct_gdt(int cpu)
526 struct desc_ptr gdt_descr;
528 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
529 gdt_descr.size = GDT_SIZE - 1;
530 load_gdt(&gdt_descr);
532 EXPORT_SYMBOL_GPL(load_direct_gdt);
534 /* Load a fixmap remapping of the per-cpu GDT */
535 void load_fixmap_gdt(int cpu)
537 struct desc_ptr gdt_descr;
539 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
540 gdt_descr.size = GDT_SIZE - 1;
541 load_gdt(&gdt_descr);
543 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
546 * Current gdt points %fs at the "master" per-cpu area: after this,
547 * it's on the real one.
549 void switch_to_new_gdt(int cpu)
551 /* Load the original GDT */
552 load_direct_gdt(cpu);
553 /* Reload the per-cpu base */
554 load_percpu_segment(cpu);
557 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
559 static void get_model_name(struct cpuinfo_x86 *c)
564 if (c->extended_cpuid_level < 0x80000004)
567 v = (unsigned int *)c->x86_model_id;
568 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
569 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
570 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
571 c->x86_model_id[48] = 0;
573 /* Trim whitespace */
574 p = q = s = &c->x86_model_id[0];
580 /* Note the last non-whitespace index */
590 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
592 unsigned int eax, ebx, ecx, edx;
594 c->x86_max_cores = 1;
595 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
598 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
600 c->x86_max_cores = (eax >> 26) + 1;
603 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
605 unsigned int n, dummy, ebx, ecx, edx, l2size;
607 n = c->extended_cpuid_level;
609 if (n >= 0x80000005) {
610 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
611 c->x86_cache_size = (ecx>>24) + (edx>>24);
613 /* On K8 L1 TLB is inclusive, so don't count it */
618 if (n < 0x80000006) /* Some chips just has a large L1. */
621 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
625 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
627 /* do processor-specific cache resizing */
628 if (this_cpu->legacy_cache_size)
629 l2size = this_cpu->legacy_cache_size(c, l2size);
631 /* Allow user to override all this if necessary. */
632 if (cachesize_override != -1)
633 l2size = cachesize_override;
636 return; /* Again, no L2 cache is possible */
639 c->x86_cache_size = l2size;
642 u16 __read_mostly tlb_lli_4k[NR_INFO];
643 u16 __read_mostly tlb_lli_2m[NR_INFO];
644 u16 __read_mostly tlb_lli_4m[NR_INFO];
645 u16 __read_mostly tlb_lld_4k[NR_INFO];
646 u16 __read_mostly tlb_lld_2m[NR_INFO];
647 u16 __read_mostly tlb_lld_4m[NR_INFO];
648 u16 __read_mostly tlb_lld_1g[NR_INFO];
650 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
652 if (this_cpu->c_detect_tlb)
653 this_cpu->c_detect_tlb(c);
655 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
656 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
657 tlb_lli_4m[ENTRIES]);
659 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
660 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
661 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
664 int detect_ht_early(struct cpuinfo_x86 *c)
667 u32 eax, ebx, ecx, edx;
669 if (!cpu_has(c, X86_FEATURE_HT))
672 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
675 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
678 cpuid(1, &eax, &ebx, &ecx, &edx);
680 smp_num_siblings = (ebx & 0xff0000) >> 16;
681 if (smp_num_siblings == 1)
682 pr_info_once("CPU0: Hyper-Threading is disabled\n");
687 void detect_ht(struct cpuinfo_x86 *c)
690 int index_msb, core_bits;
692 if (detect_ht_early(c) < 0)
695 index_msb = get_count_order(smp_num_siblings);
696 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
698 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
700 index_msb = get_count_order(smp_num_siblings);
702 core_bits = get_count_order(c->x86_max_cores);
704 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
705 ((1 << core_bits) - 1);
709 static void get_cpu_vendor(struct cpuinfo_x86 *c)
711 char *v = c->x86_vendor_id;
714 for (i = 0; i < X86_VENDOR_NUM; i++) {
718 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
719 (cpu_devs[i]->c_ident[1] &&
720 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
722 this_cpu = cpu_devs[i];
723 c->x86_vendor = this_cpu->c_x86_vendor;
728 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
729 "CPU: Your system may be unstable.\n", v);
731 c->x86_vendor = X86_VENDOR_UNKNOWN;
732 this_cpu = &default_cpu;
735 void cpu_detect(struct cpuinfo_x86 *c)
737 /* Get vendor name */
738 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
739 (unsigned int *)&c->x86_vendor_id[0],
740 (unsigned int *)&c->x86_vendor_id[8],
741 (unsigned int *)&c->x86_vendor_id[4]);
744 /* Intel-defined flags: level 0x00000001 */
745 if (c->cpuid_level >= 0x00000001) {
746 u32 junk, tfms, cap0, misc;
748 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
749 c->x86 = x86_family(tfms);
750 c->x86_model = x86_model(tfms);
751 c->x86_stepping = x86_stepping(tfms);
753 if (cap0 & (1<<19)) {
754 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
755 c->x86_cache_alignment = c->x86_clflush_size;
760 static void apply_forced_caps(struct cpuinfo_x86 *c)
764 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
765 c->x86_capability[i] &= ~cpu_caps_cleared[i];
766 c->x86_capability[i] |= cpu_caps_set[i];
770 static void init_speculation_control(struct cpuinfo_x86 *c)
773 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
774 * and they also have a different bit for STIBP support. Also,
775 * a hypervisor might have set the individual AMD bits even on
776 * Intel CPUs, for finer-grained selection of what's available.
778 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
779 set_cpu_cap(c, X86_FEATURE_IBRS);
780 set_cpu_cap(c, X86_FEATURE_IBPB);
781 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
784 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
785 set_cpu_cap(c, X86_FEATURE_STIBP);
787 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
788 cpu_has(c, X86_FEATURE_VIRT_SSBD))
789 set_cpu_cap(c, X86_FEATURE_SSBD);
791 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
792 set_cpu_cap(c, X86_FEATURE_IBRS);
793 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
796 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
797 set_cpu_cap(c, X86_FEATURE_IBPB);
799 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
800 set_cpu_cap(c, X86_FEATURE_STIBP);
801 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
804 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
805 set_cpu_cap(c, X86_FEATURE_SSBD);
806 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
807 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
811 static void init_cqm(struct cpuinfo_x86 *c)
813 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
814 c->x86_cache_max_rmid = -1;
815 c->x86_cache_occ_scale = -1;
819 /* will be overridden if occupancy monitoring exists */
820 c->x86_cache_max_rmid = cpuid_ebx(0xf);
822 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
823 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
824 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
825 u32 eax, ebx, ecx, edx;
827 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
828 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
830 c->x86_cache_max_rmid = ecx;
831 c->x86_cache_occ_scale = ebx;
835 void get_cpu_cap(struct cpuinfo_x86 *c)
837 u32 eax, ebx, ecx, edx;
839 /* Intel-defined flags: level 0x00000001 */
840 if (c->cpuid_level >= 0x00000001) {
841 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
843 c->x86_capability[CPUID_1_ECX] = ecx;
844 c->x86_capability[CPUID_1_EDX] = edx;
847 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
848 if (c->cpuid_level >= 0x00000006)
849 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
851 /* Additional Intel-defined flags: level 0x00000007 */
852 if (c->cpuid_level >= 0x00000007) {
853 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
854 c->x86_capability[CPUID_7_0_EBX] = ebx;
855 c->x86_capability[CPUID_7_ECX] = ecx;
856 c->x86_capability[CPUID_7_EDX] = edx;
859 /* Extended state features: level 0x0000000d */
860 if (c->cpuid_level >= 0x0000000d) {
861 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
863 c->x86_capability[CPUID_D_1_EAX] = eax;
866 /* AMD-defined flags: level 0x80000001 */
867 eax = cpuid_eax(0x80000000);
868 c->extended_cpuid_level = eax;
870 if ((eax & 0xffff0000) == 0x80000000) {
871 if (eax >= 0x80000001) {
872 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
874 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
875 c->x86_capability[CPUID_8000_0001_EDX] = edx;
879 if (c->extended_cpuid_level >= 0x80000007) {
880 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
882 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
886 if (c->extended_cpuid_level >= 0x80000008) {
887 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
888 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
891 if (c->extended_cpuid_level >= 0x8000000a)
892 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
894 init_scattered_cpuid_features(c);
895 init_speculation_control(c);
899 * Clear/Set all flags overridden by options, after probe.
900 * This needs to happen each time we re-probe, which may happen
901 * several times during CPU initialization.
903 apply_forced_caps(c);
906 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
908 u32 eax, ebx, ecx, edx;
910 if (c->extended_cpuid_level >= 0x80000008) {
911 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
913 c->x86_virt_bits = (eax >> 8) & 0xff;
914 c->x86_phys_bits = eax & 0xff;
917 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
918 c->x86_phys_bits = 36;
920 c->x86_cache_bits = c->x86_phys_bits;
923 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
929 * First of all, decide if this is a 486 or higher
930 * It's a 486 if we can modify the AC flag
932 if (flag_is_changeable_p(X86_EFLAGS_AC))
937 for (i = 0; i < X86_VENDOR_NUM; i++)
938 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
939 c->x86_vendor_id[0] = 0;
940 cpu_devs[i]->c_identify(c);
941 if (c->x86_vendor_id[0]) {
949 #define NO_SPECULATION BIT(0)
950 #define NO_MELTDOWN BIT(1)
951 #define NO_SSB BIT(2)
952 #define NO_L1TF BIT(3)
953 #define NO_MDS BIT(4)
954 #define MSBDS_ONLY BIT(5)
955 #define NO_SWAPGS BIT(6)
956 #define NO_ITLB_MULTIHIT BIT(7)
958 #define VULNWL(_vendor, _family, _model, _whitelist) \
959 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
961 #define VULNWL_INTEL(model, whitelist) \
962 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
964 #define VULNWL_AMD(family, whitelist) \
965 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
967 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
968 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
969 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
970 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
971 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
974 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
975 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
976 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
977 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
978 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
980 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
981 VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
982 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
983 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
984 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
985 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
987 VULNWL_INTEL(CORE_YONAH, NO_SSB),
989 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
991 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
992 VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
993 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
996 * Technically, swapgs isn't serializing on AMD (despite it previously
997 * being documented as such in the APM). But according to AMD, %gs is
998 * updated non-speculatively, and the issuing of %gs-relative memory
999 * operands will be blocked until the %gs update completes, which is
1000 * good enough for our purposes.
1003 VULNWL_INTEL(ATOM_TREMONT_X, NO_ITLB_MULTIHIT),
1005 /* AMD Family 0xf - 0x12 */
1006 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1007 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1008 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1009 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1011 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1012 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1016 static bool __init cpu_matches(unsigned long which)
1018 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
1020 return m && !!(m->driver_data & which);
1023 u64 x86_read_arch_cap_msr(void)
1027 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1028 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1033 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1035 u64 ia32_cap = x86_read_arch_cap_msr();
1037 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1038 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1039 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1041 if (cpu_matches(NO_SPECULATION))
1044 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1045 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1047 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
1048 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1049 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1051 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1052 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1054 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
1055 setup_force_cpu_bug(X86_BUG_MDS);
1056 if (cpu_matches(MSBDS_ONLY))
1057 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1060 if (!cpu_matches(NO_SWAPGS))
1061 setup_force_cpu_bug(X86_BUG_SWAPGS);
1064 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1065 * - TSX is supported or
1066 * - TSX_CTRL is present
1068 * TSX_CTRL check is needed for cases when TSX could be disabled before
1069 * the kernel boot e.g. kexec.
1070 * TSX_CTRL check alone is not sufficient for cases when the microcode
1071 * update is not present or running as guest that don't get TSX_CTRL.
1073 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1074 (cpu_has(c, X86_FEATURE_RTM) ||
1075 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1076 setup_force_cpu_bug(X86_BUG_TAA);
1078 if (cpu_matches(NO_MELTDOWN))
1081 /* Rogue Data Cache Load? No! */
1082 if (ia32_cap & ARCH_CAP_RDCL_NO)
1085 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1087 if (cpu_matches(NO_L1TF))
1090 setup_force_cpu_bug(X86_BUG_L1TF);
1094 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1095 * unfortunately, that's not true in practice because of early VIA
1096 * chips and (more importantly) broken virtualizers that are not easy
1097 * to detect. In the latter case it doesn't even *fail* reliably, so
1098 * probing for it doesn't even work. Disable it completely on 32-bit
1099 * unless we can find a reliable way to detect all the broken cases.
1100 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1102 static void detect_nopl(void)
1104 #ifdef CONFIG_X86_32
1105 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1107 setup_force_cpu_cap(X86_FEATURE_NOPL);
1112 * Do minimum CPU detection early.
1113 * Fields really needed: vendor, cpuid_level, family, model, mask,
1115 * The others are not touched to avoid unwanted side effects.
1117 * WARNING: this function is only called on the boot CPU. Don't add code
1118 * here that is supposed to run on all CPUs.
1120 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1122 #ifdef CONFIG_X86_64
1123 c->x86_clflush_size = 64;
1124 c->x86_phys_bits = 36;
1125 c->x86_virt_bits = 48;
1127 c->x86_clflush_size = 32;
1128 c->x86_phys_bits = 32;
1129 c->x86_virt_bits = 32;
1131 c->x86_cache_alignment = c->x86_clflush_size;
1133 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1134 c->extended_cpuid_level = 0;
1136 if (!have_cpuid_p())
1137 identify_cpu_without_cpuid(c);
1139 /* cyrix could have cpuid enabled via c_identify()*/
1140 if (have_cpuid_p()) {
1144 get_cpu_address_sizes(c);
1145 setup_force_cpu_cap(X86_FEATURE_CPUID);
1147 if (this_cpu->c_early_init)
1148 this_cpu->c_early_init(c);
1151 filter_cpuid_features(c, false);
1153 if (this_cpu->c_bsp_init)
1154 this_cpu->c_bsp_init(c);
1156 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1159 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1161 cpu_set_bug_bits(c);
1163 fpu__init_system(c);
1165 #ifdef CONFIG_X86_32
1167 * Regardless of whether PCID is enumerated, the SDM says
1168 * that it can't be enabled in 32-bit mode.
1170 setup_clear_cpu_cap(X86_FEATURE_PCID);
1174 * Later in the boot process pgtable_l5_enabled() relies on
1175 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1176 * enabled by this point we need to clear the feature bit to avoid
1177 * false-positives at the later stage.
1179 * pgtable_l5_enabled() can be false here for several reasons:
1180 * - 5-level paging is disabled compile-time;
1181 * - it's 32-bit kernel;
1182 * - machine doesn't support 5-level paging;
1183 * - user specified 'no5lvl' in kernel command line.
1185 if (!pgtable_l5_enabled())
1186 setup_clear_cpu_cap(X86_FEATURE_LA57);
1191 void __init early_cpu_init(void)
1193 const struct cpu_dev *const *cdev;
1196 #ifdef CONFIG_PROCESSOR_SELECT
1197 pr_info("KERNEL supported cpus:\n");
1200 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1201 const struct cpu_dev *cpudev = *cdev;
1203 if (count >= X86_VENDOR_NUM)
1205 cpu_devs[count] = cpudev;
1208 #ifdef CONFIG_PROCESSOR_SELECT
1212 for (j = 0; j < 2; j++) {
1213 if (!cpudev->c_ident[j])
1215 pr_info(" %s %s\n", cpudev->c_vendor,
1216 cpudev->c_ident[j]);
1221 early_identify_cpu(&boot_cpu_data);
1224 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1226 #ifdef CONFIG_X86_64
1228 * Empirically, writing zero to a segment selector on AMD does
1229 * not clear the base, whereas writing zero to a segment
1230 * selector on Intel does clear the base. Intel's behavior
1231 * allows slightly faster context switches in the common case
1232 * where GS is unused by the prev and next threads.
1234 * Since neither vendor documents this anywhere that I can see,
1235 * detect it directly instead of hardcoding the choice by
1238 * I've designated AMD's behavior as the "bug" because it's
1239 * counterintuitive and less friendly.
1242 unsigned long old_base, tmp;
1243 rdmsrl(MSR_FS_BASE, old_base);
1244 wrmsrl(MSR_FS_BASE, 1);
1246 rdmsrl(MSR_FS_BASE, tmp);
1248 set_cpu_bug(c, X86_BUG_NULL_SEG);
1249 wrmsrl(MSR_FS_BASE, old_base);
1253 static void generic_identify(struct cpuinfo_x86 *c)
1255 c->extended_cpuid_level = 0;
1257 if (!have_cpuid_p())
1258 identify_cpu_without_cpuid(c);
1260 /* cyrix could have cpuid enabled via c_identify()*/
1261 if (!have_cpuid_p())
1270 get_cpu_address_sizes(c);
1272 if (c->cpuid_level >= 0x00000001) {
1273 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1274 #ifdef CONFIG_X86_32
1276 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1278 c->apicid = c->initial_apicid;
1281 c->phys_proc_id = c->initial_apicid;
1284 get_model_name(c); /* Default name */
1286 detect_null_seg_behavior(c);
1289 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1290 * systems that run Linux at CPL > 0 may or may not have the
1291 * issue, but, even if they have the issue, there's absolutely
1292 * nothing we can do about it because we can't use the real IRET
1295 * NB: For the time being, only 32-bit kernels support
1296 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1297 * whether to apply espfix using paravirt hooks. If any
1298 * non-paravirt system ever shows up that does *not* have the
1299 * ESPFIX issue, we can change this.
1301 #ifdef CONFIG_X86_32
1302 # ifdef CONFIG_PARAVIRT
1304 extern void native_iret(void);
1305 if (pv_cpu_ops.iret == native_iret)
1306 set_cpu_bug(c, X86_BUG_ESPFIX);
1309 set_cpu_bug(c, X86_BUG_ESPFIX);
1314 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1317 * The heavy lifting of max_rmid and cache_occ_scale are handled
1318 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1319 * in case CQM bits really aren't there in this CPU.
1321 if (c != &boot_cpu_data) {
1322 boot_cpu_data.x86_cache_max_rmid =
1323 min(boot_cpu_data.x86_cache_max_rmid,
1324 c->x86_cache_max_rmid);
1329 * Validate that ACPI/mptables have the same information about the
1330 * effective APIC id and update the package map.
1332 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1335 unsigned int apicid, cpu = smp_processor_id();
1337 apicid = apic->cpu_present_to_apicid(cpu);
1339 if (apicid != c->apicid) {
1340 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1341 cpu, apicid, c->initial_apicid);
1343 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1345 c->logical_proc_id = 0;
1350 * This does the hard work of actually picking apart the CPU stuff...
1352 static void identify_cpu(struct cpuinfo_x86 *c)
1356 c->loops_per_jiffy = loops_per_jiffy;
1357 c->x86_cache_size = 0;
1358 c->x86_vendor = X86_VENDOR_UNKNOWN;
1359 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1360 c->x86_vendor_id[0] = '\0'; /* Unset */
1361 c->x86_model_id[0] = '\0'; /* Unset */
1362 c->x86_max_cores = 1;
1363 c->x86_coreid_bits = 0;
1365 #ifdef CONFIG_X86_64
1366 c->x86_clflush_size = 64;
1367 c->x86_phys_bits = 36;
1368 c->x86_virt_bits = 48;
1370 c->cpuid_level = -1; /* CPUID not detected */
1371 c->x86_clflush_size = 32;
1372 c->x86_phys_bits = 32;
1373 c->x86_virt_bits = 32;
1375 c->x86_cache_alignment = c->x86_clflush_size;
1376 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1378 generic_identify(c);
1380 if (this_cpu->c_identify)
1381 this_cpu->c_identify(c);
1383 /* Clear/Set all flags overridden by options, after probe */
1384 apply_forced_caps(c);
1386 #ifdef CONFIG_X86_64
1387 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1391 * Vendor-specific initialization. In this section we
1392 * canonicalize the feature flags, meaning if there are
1393 * features a certain CPU supports which CPUID doesn't
1394 * tell us, CPUID claiming incorrect flags, or other bugs,
1395 * we handle them here.
1397 * At the end of this section, c->x86_capability better
1398 * indicate the features this CPU genuinely supports!
1400 if (this_cpu->c_init)
1401 this_cpu->c_init(c);
1403 /* Disable the PN if appropriate */
1404 squash_the_stupid_serial_number(c);
1406 /* Set up SMEP/SMAP/UMIP */
1412 * The vendor-specific functions might have changed features.
1413 * Now we do "generic changes."
1416 /* Filter out anything that depends on CPUID levels we don't have */
1417 filter_cpuid_features(c, true);
1419 /* If the model name is still unset, do table lookup. */
1420 if (!c->x86_model_id[0]) {
1422 p = table_lookup_model(c);
1424 strcpy(c->x86_model_id, p);
1426 /* Last resort... */
1427 sprintf(c->x86_model_id, "%02x/%02x",
1428 c->x86, c->x86_model);
1431 #ifdef CONFIG_X86_64
1436 x86_init_cache_qos(c);
1440 * Clear/Set all flags overridden by options, need do it
1441 * before following smp all cpus cap AND.
1443 apply_forced_caps(c);
1446 * On SMP, boot_cpu_data holds the common feature set between
1447 * all CPUs; so make sure that we indicate which features are
1448 * common between the CPUs. The first time this routine gets
1449 * executed, c == &boot_cpu_data.
1451 if (c != &boot_cpu_data) {
1452 /* AND the already accumulated flags with these */
1453 for (i = 0; i < NCAPINTS; i++)
1454 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1456 /* OR, i.e. replicate the bug flags */
1457 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1458 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1461 /* Init Machine Check Exception if available. */
1464 select_idle_routine(c);
1467 numa_add_cpu(smp_processor_id());
1472 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1473 * on 32-bit kernels:
1475 #ifdef CONFIG_X86_32
1476 void enable_sep_cpu(void)
1478 struct tss_struct *tss;
1481 if (!boot_cpu_has(X86_FEATURE_SEP))
1485 tss = &per_cpu(cpu_tss_rw, cpu);
1488 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1489 * see the big comment in struct x86_hw_tss's definition.
1492 tss->x86_tss.ss1 = __KERNEL_CS;
1493 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1494 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1495 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1501 void __init identify_boot_cpu(void)
1503 identify_cpu(&boot_cpu_data);
1504 #ifdef CONFIG_X86_32
1508 cpu_detect_tlb(&boot_cpu_data);
1512 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1514 BUG_ON(c == &boot_cpu_data);
1516 #ifdef CONFIG_X86_32
1520 validate_apic_and_package_id(c);
1521 x86_spec_ctrl_setup_ap();
1524 static __init int setup_noclflush(char *arg)
1526 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1527 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1530 __setup("noclflush", setup_noclflush);
1532 void print_cpu_info(struct cpuinfo_x86 *c)
1534 const char *vendor = NULL;
1536 if (c->x86_vendor < X86_VENDOR_NUM) {
1537 vendor = this_cpu->c_vendor;
1539 if (c->cpuid_level >= 0)
1540 vendor = c->x86_vendor_id;
1543 if (vendor && !strstr(c->x86_model_id, vendor))
1544 pr_cont("%s ", vendor);
1546 if (c->x86_model_id[0])
1547 pr_cont("%s", c->x86_model_id);
1549 pr_cont("%d86", c->x86);
1551 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1553 if (c->x86_stepping || c->cpuid_level >= 0)
1554 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1560 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1561 * But we need to keep a dummy __setup around otherwise it would
1562 * show up as an environment variable for init.
1564 static __init int setup_clearcpuid(char *arg)
1568 __setup("clearcpuid=", setup_clearcpuid);
1570 #ifdef CONFIG_X86_64
1571 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1572 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1573 EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union);
1576 * The following percpu variables are hot. Align current_task to
1577 * cacheline size such that they fall in the same cacheline.
1579 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1581 EXPORT_PER_CPU_SYMBOL(current_task);
1583 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1584 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1586 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1588 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1589 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1591 /* May not be marked __init: used by software suspend */
1592 void syscall_init(void)
1594 extern char _entry_trampoline[];
1595 extern char entry_SYSCALL_64_trampoline[];
1597 int cpu = smp_processor_id();
1598 unsigned long SYSCALL64_entry_trampoline =
1599 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1600 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1602 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1603 if (static_cpu_has(X86_FEATURE_PTI))
1604 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1606 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1608 #ifdef CONFIG_IA32_EMULATION
1609 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1611 * This only works on Intel CPUs.
1612 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1613 * This does not cause SYSENTER to jump to the wrong location, because
1614 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1616 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1617 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
1618 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1620 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1621 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1622 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1623 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1626 /* Flags to clear on syscall */
1627 wrmsrl(MSR_SYSCALL_MASK,
1628 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1629 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1633 * Copies of the original ist values from the tss are only accessed during
1634 * debugging, no special alignment required.
1636 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1638 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1639 DEFINE_PER_CPU(int, debug_stack_usage);
1641 int is_debug_stack(unsigned long addr)
1643 return __this_cpu_read(debug_stack_usage) ||
1644 (addr <= __this_cpu_read(debug_stack_addr) &&
1645 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1647 NOKPROBE_SYMBOL(is_debug_stack);
1649 DEFINE_PER_CPU(u32, debug_idt_ctr);
1651 void debug_stack_set_zero(void)
1653 this_cpu_inc(debug_idt_ctr);
1656 NOKPROBE_SYMBOL(debug_stack_set_zero);
1658 void debug_stack_reset(void)
1660 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1662 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1665 NOKPROBE_SYMBOL(debug_stack_reset);
1667 #else /* CONFIG_X86_64 */
1669 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1670 EXPORT_PER_CPU_SYMBOL(current_task);
1671 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1672 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1675 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1676 * the top of the kernel stack. Use an extra percpu variable to track the
1677 * top of the kernel stack directly.
1679 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1680 (unsigned long)&init_thread_union + THREAD_SIZE;
1681 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1683 #ifdef CONFIG_STACKPROTECTOR
1684 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1687 #endif /* CONFIG_X86_64 */
1690 * Clear all 6 debug registers:
1692 static void clear_all_debug_regs(void)
1696 for (i = 0; i < 8; i++) {
1697 /* Ignore db4, db5 */
1698 if ((i == 4) || (i == 5))
1707 * Restore debug regs if using kgdbwait and you have a kernel debugger
1708 * connection established.
1710 static void dbg_restore_debug_regs(void)
1712 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1713 arch_kgdb_ops.correct_hw_break();
1715 #else /* ! CONFIG_KGDB */
1716 #define dbg_restore_debug_regs()
1717 #endif /* ! CONFIG_KGDB */
1719 static void wait_for_master_cpu(int cpu)
1723 * wait for ACK from master CPU before continuing
1724 * with AP initialization
1726 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1727 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1733 * cpu_init() initializes state that is per-CPU. Some data is already
1734 * initialized (naturally) in the bootstrap process, such as the GDT
1735 * and IDT. We reload them nevertheless, this function acts as a
1736 * 'CPU state barrier', nothing should get across.
1737 * A lot of state is already set up in PDA init for 64 bit
1739 #ifdef CONFIG_X86_64
1743 struct orig_ist *oist;
1744 struct task_struct *me;
1745 struct tss_struct *t;
1747 int cpu = raw_smp_processor_id();
1750 wait_for_master_cpu(cpu);
1753 * Initialize the CR4 shadow before doing anything that could
1761 t = &per_cpu(cpu_tss_rw, cpu);
1762 oist = &per_cpu(orig_ist, cpu);
1765 if (this_cpu_read(numa_node) == 0 &&
1766 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1767 set_numa_node(early_cpu_to_node(cpu));
1772 pr_debug("Initializing CPU#%d\n", cpu);
1774 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1777 * Initialize the per-CPU GDT with the boot GDT,
1778 * and set up the GDT descriptor:
1781 switch_to_new_gdt(cpu);
1786 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1789 wrmsrl(MSR_FS_BASE, 0);
1790 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1797 * set up and load the per-CPU TSS
1799 if (!oist->ist[0]) {
1800 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1802 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1803 estacks += exception_stack_sizes[v];
1804 oist->ist[v] = t->x86_tss.ist[v] =
1805 (unsigned long)estacks;
1806 if (v == DEBUG_STACK-1)
1807 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1811 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1814 * <= is required because the CPU will access up to
1815 * 8 bits beyond the end of the IO permission bitmap.
1817 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1818 t->io_bitmap[i] = ~0UL;
1821 me->active_mm = &init_mm;
1823 initialize_tlbstate_and_flush();
1824 enter_lazy_tlb(&init_mm, me);
1827 * Initialize the TSS. sp0 points to the entry trampoline stack
1828 * regardless of what task is running.
1830 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1832 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1834 load_mm_ldt(&init_mm);
1836 clear_all_debug_regs();
1837 dbg_restore_debug_regs();
1844 load_fixmap_gdt(cpu);
1851 int cpu = smp_processor_id();
1852 struct task_struct *curr = current;
1853 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1855 wait_for_master_cpu(cpu);
1858 * Initialize the CR4 shadow before doing anything that could
1863 show_ucode_info_early();
1865 pr_info("Initializing CPU#%d\n", cpu);
1867 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1868 boot_cpu_has(X86_FEATURE_TSC) ||
1869 boot_cpu_has(X86_FEATURE_DE))
1870 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1873 switch_to_new_gdt(cpu);
1876 * Set up and load the per-CPU TSS and LDT
1879 curr->active_mm = &init_mm;
1881 initialize_tlbstate_and_flush();
1882 enter_lazy_tlb(&init_mm, curr);
1885 * Initialize the TSS. sp0 points to the entry trampoline stack
1886 * regardless of what task is running.
1888 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1890 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1892 load_mm_ldt(&init_mm);
1894 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1896 #ifdef CONFIG_DOUBLEFAULT
1897 /* Set up doublefault TSS pointer in the GDT */
1898 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1901 clear_all_debug_regs();
1902 dbg_restore_debug_regs();
1906 load_fixmap_gdt(cpu);
1910 static void bsp_resume(void)
1912 if (this_cpu->c_bsp_resume)
1913 this_cpu->c_bsp_resume(&boot_cpu_data);
1916 static struct syscore_ops cpu_syscore_ops = {
1917 .resume = bsp_resume,
1920 static int __init init_cpu_syscore(void)
1922 register_syscore_ops(&cpu_syscore_ops);
1925 core_initcall(init_cpu_syscore);
1928 * The microcode loader calls this upon late microcode load to recheck features,
1929 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1932 void microcode_check(void)
1934 struct cpuinfo_x86 info;
1936 perf_check_microcode();
1938 /* Reload CPUID max function as it might've changed. */
1939 info.cpuid_level = cpuid_eax(0);
1942 * Copy all capability leafs to pick up the synthetic ones so that
1943 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1944 * get overwritten in get_cpu_cap().
1946 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1950 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1953 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1954 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");