1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/export.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/ctype.h>
9 #include <linux/delay.h>
10 #include <linux/sched/mm.h>
11 #include <linux/sched/clock.h>
12 #include <linux/sched/task.h>
13 #include <linux/init.h>
14 #include <linux/kprobes.h>
15 #include <linux/kgdb.h>
16 #include <linux/smp.h>
18 #include <linux/syscore_ops.h>
20 #include <asm/stackprotector.h>
21 #include <asm/perf_event.h>
22 #include <asm/mmu_context.h>
23 #include <asm/archrandom.h>
24 #include <asm/hypervisor.h>
25 #include <asm/processor.h>
26 #include <asm/tlbflush.h>
27 #include <asm/debugreg.h>
28 #include <asm/sections.h>
29 #include <asm/vsyscall.h>
30 #include <linux/topology.h>
31 #include <linux/cpumask.h>
32 #include <asm/pgtable.h>
33 #include <linux/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/setup.h>
38 #include <asm/fpu/internal.h>
40 #include <asm/hwcap2.h>
41 #include <linux/numa.h>
48 #include <asm/microcode.h>
49 #include <asm/microcode_intel.h>
51 #ifdef CONFIG_X86_LOCAL_APIC
52 #include <asm/uv/uv.h>
57 u32 elf_hwcap2 __read_mostly;
59 /* all of these masks are initialized in setup_cpu_local_masks() */
60 cpumask_var_t cpu_initialized_mask;
61 cpumask_var_t cpu_callout_mask;
62 cpumask_var_t cpu_callin_mask;
64 /* representing cpus for which sibling maps can be computed */
65 cpumask_var_t cpu_sibling_setup_mask;
67 /* correctly size the local cpu masks */
68 void __init setup_cpu_local_masks(void)
70 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
71 alloc_bootmem_cpumask_var(&cpu_callin_mask);
72 alloc_bootmem_cpumask_var(&cpu_callout_mask);
73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
76 static void default_init(struct cpuinfo_x86 *c)
79 cpu_detect_cache_sizes(c);
81 /* Not much we can do here... */
82 /* Check if at least it has cpuid */
83 if (c->cpuid_level == -1) {
84 /* No cpuid. It must be an ancient CPU */
86 strcpy(c->x86_model_id, "486");
88 strcpy(c->x86_model_id, "386");
93 static const struct cpu_dev default_cpu = {
94 .c_init = default_init,
95 .c_vendor = "Unknown",
96 .c_x86_vendor = X86_VENDOR_UNKNOWN,
99 static const struct cpu_dev *this_cpu = &default_cpu;
101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
104 * We need valid kernel segments for data and code in long mode too
105 * IRET will check the segment types kkeil 2000/10/28
106 * Also sysret mandates a special GDT layout
108 * TLS descriptors are currently at a different place compared to i386.
109 * Hopefully nobody expects them at a fixed place (Wine?)
111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
123 * Segments used for calling PnP BIOS have byte granularity.
124 * They code segments and data segments have fixed 64k limits,
125 * the transfer segment sizes are set at run time.
128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
138 * The APM segments have byte granularity and their bases
139 * are set at run time. All have 64k limits.
142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
150 GDT_STACK_CANARY_INIT
153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
155 static int __init x86_mpx_setup(char *s)
157 /* require an exact match without trailing characters */
161 /* do not emit a message if the feature is not present */
162 if (!boot_cpu_has(X86_FEATURE_MPX))
165 setup_clear_cpu_cap(X86_FEATURE_MPX);
166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
169 __setup("nompx", x86_mpx_setup);
172 static int __init x86_nopcid_setup(char *s)
174 /* nopcid doesn't accept parameters */
178 /* do not emit a message if the feature is not present */
179 if (!boot_cpu_has(X86_FEATURE_PCID))
182 setup_clear_cpu_cap(X86_FEATURE_PCID);
183 pr_info("nopcid: PCID feature disabled\n");
186 early_param("nopcid", x86_nopcid_setup);
189 static int __init x86_noinvpcid_setup(char *s)
191 /* noinvpcid doesn't accept parameters */
195 /* do not emit a message if the feature is not present */
196 if (!boot_cpu_has(X86_FEATURE_INVPCID))
199 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
200 pr_info("noinvpcid: INVPCID feature disabled\n");
203 early_param("noinvpcid", x86_noinvpcid_setup);
206 static int cachesize_override = -1;
207 static int disable_x86_serial_nr = 1;
209 static int __init cachesize_setup(char *str)
211 get_option(&str, &cachesize_override);
214 __setup("cachesize=", cachesize_setup);
216 static int __init x86_sep_setup(char *s)
218 setup_clear_cpu_cap(X86_FEATURE_SEP);
221 __setup("nosep", x86_sep_setup);
223 /* Standard macro to see if a specific flag is changeable */
224 static inline int flag_is_changeable_p(u32 flag)
229 * Cyrix and IDT cpus allow disabling of CPUID
230 * so the code below may return different results
231 * when it is executed before and after enabling
232 * the CPUID. Add "volatile" to not allow gcc to
233 * optimize the subsequent calls to this function.
235 asm volatile ("pushfl \n\t"
246 : "=&r" (f1), "=&r" (f2)
249 return ((f1^f2) & flag) != 0;
252 /* Probe for the CPUID instruction */
253 int have_cpuid_p(void)
255 return flag_is_changeable_p(X86_EFLAGS_ID);
258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
260 unsigned long lo, hi;
262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
265 /* Disable processor serial number: */
267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
271 pr_notice("CPU serial number disabled.\n");
272 clear_cpu_cap(c, X86_FEATURE_PN);
274 /* Disabling the serial number may affect the cpuid level */
275 c->cpuid_level = cpuid_eax(0);
278 static int __init x86_serial_nr_setup(char *s)
280 disable_x86_serial_nr = 0;
283 __setup("serialnumber", x86_serial_nr_setup);
285 static inline int flag_is_changeable_p(u32 flag)
289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
294 static __init int setup_disable_smep(char *arg)
296 setup_clear_cpu_cap(X86_FEATURE_SMEP);
297 /* Check for things that depend on SMEP being enabled: */
298 check_mpx_erratum(&boot_cpu_data);
301 __setup("nosmep", setup_disable_smep);
303 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
305 if (cpu_has(c, X86_FEATURE_SMEP))
306 cr4_set_bits(X86_CR4_SMEP);
309 static __init int setup_disable_smap(char *arg)
311 setup_clear_cpu_cap(X86_FEATURE_SMAP);
314 __setup("nosmap", setup_disable_smap);
316 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
318 unsigned long eflags = native_save_fl();
320 /* This should have been cleared long ago */
321 BUG_ON(eflags & X86_EFLAGS_AC);
323 if (cpu_has(c, X86_FEATURE_SMAP)) {
324 #ifdef CONFIG_X86_SMAP
325 cr4_set_bits(X86_CR4_SMAP);
327 cr4_clear_bits(X86_CR4_SMAP);
333 * Protection Keys are not available in 32-bit mode.
335 static bool pku_disabled;
337 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
339 /* check the boot processor, plus compile options for PKU: */
340 if (!cpu_feature_enabled(X86_FEATURE_PKU))
342 /* checks the actual processor's cpuid bits: */
343 if (!cpu_has(c, X86_FEATURE_PKU))
348 cr4_set_bits(X86_CR4_PKE);
350 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
351 * cpuid bit to be set. We need to ensure that we
352 * update that bit in this CPU's "cpu_info".
357 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
358 static __init int setup_disable_pku(char *arg)
361 * Do not clear the X86_FEATURE_PKU bit. All of the
362 * runtime checks are against OSPKE so clearing the
365 * This way, we will see "pku" in cpuinfo, but not
366 * "ospke", which is exactly what we want. It shows
367 * that the CPU has PKU, but the OS has not enabled it.
368 * This happens to be exactly how a system would look
369 * if we disabled the config option.
371 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
375 __setup("nopku", setup_disable_pku);
376 #endif /* CONFIG_X86_64 */
379 * Some CPU features depend on higher CPUID levels, which may not always
380 * be available due to CPUID level capping or broken virtualization
381 * software. Add those features to this table to auto-disable them.
383 struct cpuid_dependent_feature {
388 static const struct cpuid_dependent_feature
389 cpuid_dependent_features[] = {
390 { X86_FEATURE_MWAIT, 0x00000005 },
391 { X86_FEATURE_DCA, 0x00000009 },
392 { X86_FEATURE_XSAVE, 0x0000000d },
396 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
398 const struct cpuid_dependent_feature *df;
400 for (df = cpuid_dependent_features; df->feature; df++) {
402 if (!cpu_has(c, df->feature))
405 * Note: cpuid_level is set to -1 if unavailable, but
406 * extended_extended_level is set to 0 if unavailable
407 * and the legitimate extended levels are all negative
408 * when signed; hence the weird messing around with
411 if (!((s32)df->level < 0 ?
412 (u32)df->level > (u32)c->extended_cpuid_level :
413 (s32)df->level > (s32)c->cpuid_level))
416 clear_cpu_cap(c, df->feature);
420 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
421 x86_cap_flag(df->feature), df->level);
426 * Naming convention should be: <Name> [(<Codename>)]
427 * This table only is used unless init_<vendor>() below doesn't set it;
428 * in particular, if CPUID levels 0x80000002..4 are supported, this
432 /* Look up CPU names by table lookup. */
433 static const char *table_lookup_model(struct cpuinfo_x86 *c)
436 const struct legacy_cpu_model_info *info;
438 if (c->x86_model >= 16)
439 return NULL; /* Range check */
444 info = this_cpu->legacy_models;
446 while (info->family) {
447 if (info->family == c->x86)
448 return info->model_names[c->x86_model];
452 return NULL; /* Not found */
455 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
456 __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
458 void load_percpu_segment(int cpu)
461 loadsegment(fs, __KERNEL_PERCPU);
463 __loadsegment_simple(gs, 0);
464 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
466 load_stack_canary_segment();
470 /* The 32-bit entry code needs to find cpu_entry_area. */
471 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
476 * Special IST stacks which the CPU switches to when it calls
477 * an IST-marked descriptor entry. Up to 7 stacks (hardware
478 * limit), all of them are 4K, except the debug stack which
481 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
482 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
483 [DEBUG_STACK - 1] = DEBUG_STKSZ
487 /* Load the original GDT from the per-cpu structure */
488 void load_direct_gdt(int cpu)
490 struct desc_ptr gdt_descr;
492 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
493 gdt_descr.size = GDT_SIZE - 1;
494 load_gdt(&gdt_descr);
496 EXPORT_SYMBOL_GPL(load_direct_gdt);
498 /* Load a fixmap remapping of the per-cpu GDT */
499 void load_fixmap_gdt(int cpu)
501 struct desc_ptr gdt_descr;
503 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
504 gdt_descr.size = GDT_SIZE - 1;
505 load_gdt(&gdt_descr);
507 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
510 * Current gdt points %fs at the "master" per-cpu area: after this,
511 * it's on the real one.
513 void switch_to_new_gdt(int cpu)
515 /* Load the original GDT */
516 load_direct_gdt(cpu);
517 /* Reload the per-cpu base */
518 load_percpu_segment(cpu);
521 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
523 static void get_model_name(struct cpuinfo_x86 *c)
528 if (c->extended_cpuid_level < 0x80000004)
531 v = (unsigned int *)c->x86_model_id;
532 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
533 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
534 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
535 c->x86_model_id[48] = 0;
537 /* Trim whitespace */
538 p = q = s = &c->x86_model_id[0];
544 /* Note the last non-whitespace index */
554 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
556 unsigned int n, dummy, ebx, ecx, edx, l2size;
558 n = c->extended_cpuid_level;
560 if (n >= 0x80000005) {
561 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
562 c->x86_cache_size = (ecx>>24) + (edx>>24);
564 /* On K8 L1 TLB is inclusive, so don't count it */
569 if (n < 0x80000006) /* Some chips just has a large L1. */
572 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
576 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
578 /* do processor-specific cache resizing */
579 if (this_cpu->legacy_cache_size)
580 l2size = this_cpu->legacy_cache_size(c, l2size);
582 /* Allow user to override all this if necessary. */
583 if (cachesize_override != -1)
584 l2size = cachesize_override;
587 return; /* Again, no L2 cache is possible */
590 c->x86_cache_size = l2size;
593 u16 __read_mostly tlb_lli_4k[NR_INFO];
594 u16 __read_mostly tlb_lli_2m[NR_INFO];
595 u16 __read_mostly tlb_lli_4m[NR_INFO];
596 u16 __read_mostly tlb_lld_4k[NR_INFO];
597 u16 __read_mostly tlb_lld_2m[NR_INFO];
598 u16 __read_mostly tlb_lld_4m[NR_INFO];
599 u16 __read_mostly tlb_lld_1g[NR_INFO];
601 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
603 if (this_cpu->c_detect_tlb)
604 this_cpu->c_detect_tlb(c);
606 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
607 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
608 tlb_lli_4m[ENTRIES]);
610 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
611 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
612 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
615 void detect_ht(struct cpuinfo_x86 *c)
618 u32 eax, ebx, ecx, edx;
619 int index_msb, core_bits;
622 if (!cpu_has(c, X86_FEATURE_HT))
625 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
628 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
631 cpuid(1, &eax, &ebx, &ecx, &edx);
633 smp_num_siblings = (ebx & 0xff0000) >> 16;
635 if (smp_num_siblings == 1) {
636 pr_info_once("CPU0: Hyper-Threading is disabled\n");
640 if (smp_num_siblings <= 1)
643 index_msb = get_count_order(smp_num_siblings);
644 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
646 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
648 index_msb = get_count_order(smp_num_siblings);
650 core_bits = get_count_order(c->x86_max_cores);
652 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
653 ((1 << core_bits) - 1);
656 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
657 pr_info("CPU: Physical Processor ID: %d\n",
659 pr_info("CPU: Processor Core ID: %d\n",
666 static void get_cpu_vendor(struct cpuinfo_x86 *c)
668 char *v = c->x86_vendor_id;
671 for (i = 0; i < X86_VENDOR_NUM; i++) {
675 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
676 (cpu_devs[i]->c_ident[1] &&
677 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
679 this_cpu = cpu_devs[i];
680 c->x86_vendor = this_cpu->c_x86_vendor;
685 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
686 "CPU: Your system may be unstable.\n", v);
688 c->x86_vendor = X86_VENDOR_UNKNOWN;
689 this_cpu = &default_cpu;
692 void cpu_detect(struct cpuinfo_x86 *c)
694 /* Get vendor name */
695 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
696 (unsigned int *)&c->x86_vendor_id[0],
697 (unsigned int *)&c->x86_vendor_id[8],
698 (unsigned int *)&c->x86_vendor_id[4]);
701 /* Intel-defined flags: level 0x00000001 */
702 if (c->cpuid_level >= 0x00000001) {
703 u32 junk, tfms, cap0, misc;
705 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
706 c->x86 = x86_family(tfms);
707 c->x86_model = x86_model(tfms);
708 c->x86_mask = x86_stepping(tfms);
710 if (cap0 & (1<<19)) {
711 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
712 c->x86_cache_alignment = c->x86_clflush_size;
717 static void apply_forced_caps(struct cpuinfo_x86 *c)
721 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
722 c->x86_capability[i] &= ~cpu_caps_cleared[i];
723 c->x86_capability[i] |= cpu_caps_set[i];
727 void get_cpu_cap(struct cpuinfo_x86 *c)
729 u32 eax, ebx, ecx, edx;
731 /* Intel-defined flags: level 0x00000001 */
732 if (c->cpuid_level >= 0x00000001) {
733 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
735 c->x86_capability[CPUID_1_ECX] = ecx;
736 c->x86_capability[CPUID_1_EDX] = edx;
739 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
740 if (c->cpuid_level >= 0x00000006)
741 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
743 /* Additional Intel-defined flags: level 0x00000007 */
744 if (c->cpuid_level >= 0x00000007) {
745 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
746 c->x86_capability[CPUID_7_0_EBX] = ebx;
747 c->x86_capability[CPUID_7_ECX] = ecx;
750 /* Extended state features: level 0x0000000d */
751 if (c->cpuid_level >= 0x0000000d) {
752 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
754 c->x86_capability[CPUID_D_1_EAX] = eax;
757 /* Additional Intel-defined flags: level 0x0000000F */
758 if (c->cpuid_level >= 0x0000000F) {
760 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
761 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
762 c->x86_capability[CPUID_F_0_EDX] = edx;
764 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
765 /* will be overridden if occupancy monitoring exists */
766 c->x86_cache_max_rmid = ebx;
768 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
769 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
770 c->x86_capability[CPUID_F_1_EDX] = edx;
772 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
773 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
774 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
775 c->x86_cache_max_rmid = ecx;
776 c->x86_cache_occ_scale = ebx;
779 c->x86_cache_max_rmid = -1;
780 c->x86_cache_occ_scale = -1;
784 /* AMD-defined flags: level 0x80000001 */
785 eax = cpuid_eax(0x80000000);
786 c->extended_cpuid_level = eax;
788 if ((eax & 0xffff0000) == 0x80000000) {
789 if (eax >= 0x80000001) {
790 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
792 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
793 c->x86_capability[CPUID_8000_0001_EDX] = edx;
797 if (c->extended_cpuid_level >= 0x80000007) {
798 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
800 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
804 if (c->extended_cpuid_level >= 0x80000008) {
805 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
807 c->x86_virt_bits = (eax >> 8) & 0xff;
808 c->x86_phys_bits = eax & 0xff;
809 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
812 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
813 c->x86_phys_bits = 36;
816 if (c->extended_cpuid_level >= 0x8000000a)
817 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
819 init_scattered_cpuid_features(c);
822 * Clear/Set all flags overridden by options, after probe.
823 * This needs to happen each time we re-probe, which may happen
824 * several times during CPU initialization.
826 apply_forced_caps(c);
829 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
835 * First of all, decide if this is a 486 or higher
836 * It's a 486 if we can modify the AC flag
838 if (flag_is_changeable_p(X86_EFLAGS_AC))
843 for (i = 0; i < X86_VENDOR_NUM; i++)
844 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
845 c->x86_vendor_id[0] = 0;
846 cpu_devs[i]->c_identify(c);
847 if (c->x86_vendor_id[0]) {
856 * Do minimum CPU detection early.
857 * Fields really needed: vendor, cpuid_level, family, model, mask,
859 * The others are not touched to avoid unwanted side effects.
861 * WARNING: this function is only called on the BP. Don't add code here
862 * that is supposed to run on all CPUs.
864 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
867 c->x86_clflush_size = 64;
868 c->x86_phys_bits = 36;
869 c->x86_virt_bits = 48;
871 c->x86_clflush_size = 32;
872 c->x86_phys_bits = 32;
873 c->x86_virt_bits = 32;
875 c->x86_cache_alignment = c->x86_clflush_size;
877 memset(&c->x86_capability, 0, sizeof c->x86_capability);
878 c->extended_cpuid_level = 0;
880 /* cyrix could have cpuid enabled via c_identify()*/
881 if (have_cpuid_p()) {
885 setup_force_cpu_cap(X86_FEATURE_CPUID);
887 if (this_cpu->c_early_init)
888 this_cpu->c_early_init(c);
891 filter_cpuid_features(c, false);
893 if (this_cpu->c_bsp_init)
894 this_cpu->c_bsp_init(c);
896 identify_cpu_without_cpuid(c);
897 setup_clear_cpu_cap(X86_FEATURE_CPUID);
900 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
902 if (c->x86_vendor != X86_VENDOR_AMD)
903 setup_force_cpu_bug(X86_BUG_CPU_INSECURE);
909 * Regardless of whether PCID is enumerated, the SDM says
910 * that it can't be enabled in 32-bit mode.
912 setup_clear_cpu_cap(X86_FEATURE_PCID);
916 void __init early_cpu_init(void)
918 const struct cpu_dev *const *cdev;
921 #ifdef CONFIG_PROCESSOR_SELECT
922 pr_info("KERNEL supported cpus:\n");
925 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
926 const struct cpu_dev *cpudev = *cdev;
928 if (count >= X86_VENDOR_NUM)
930 cpu_devs[count] = cpudev;
933 #ifdef CONFIG_PROCESSOR_SELECT
937 for (j = 0; j < 2; j++) {
938 if (!cpudev->c_ident[j])
940 pr_info(" %s %s\n", cpudev->c_vendor,
946 early_identify_cpu(&boot_cpu_data);
950 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
951 * unfortunately, that's not true in practice because of early VIA
952 * chips and (more importantly) broken virtualizers that are not easy
953 * to detect. In the latter case it doesn't even *fail* reliably, so
954 * probing for it doesn't even work. Disable it completely on 32-bit
955 * unless we can find a reliable way to detect all the broken cases.
956 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
958 static void detect_nopl(struct cpuinfo_x86 *c)
961 clear_cpu_cap(c, X86_FEATURE_NOPL);
963 set_cpu_cap(c, X86_FEATURE_NOPL);
967 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
971 * Empirically, writing zero to a segment selector on AMD does
972 * not clear the base, whereas writing zero to a segment
973 * selector on Intel does clear the base. Intel's behavior
974 * allows slightly faster context switches in the common case
975 * where GS is unused by the prev and next threads.
977 * Since neither vendor documents this anywhere that I can see,
978 * detect it directly instead of hardcoding the choice by
981 * I've designated AMD's behavior as the "bug" because it's
982 * counterintuitive and less friendly.
985 unsigned long old_base, tmp;
986 rdmsrl(MSR_FS_BASE, old_base);
987 wrmsrl(MSR_FS_BASE, 1);
989 rdmsrl(MSR_FS_BASE, tmp);
991 set_cpu_bug(c, X86_BUG_NULL_SEG);
992 wrmsrl(MSR_FS_BASE, old_base);
996 static void generic_identify(struct cpuinfo_x86 *c)
998 c->extended_cpuid_level = 0;
1000 if (!have_cpuid_p())
1001 identify_cpu_without_cpuid(c);
1003 /* cyrix could have cpuid enabled via c_identify()*/
1004 if (!have_cpuid_p())
1013 if (c->cpuid_level >= 0x00000001) {
1014 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1015 #ifdef CONFIG_X86_32
1017 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1019 c->apicid = c->initial_apicid;
1022 c->phys_proc_id = c->initial_apicid;
1025 get_model_name(c); /* Default name */
1029 detect_null_seg_behavior(c);
1032 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1033 * systems that run Linux at CPL > 0 may or may not have the
1034 * issue, but, even if they have the issue, there's absolutely
1035 * nothing we can do about it because we can't use the real IRET
1038 * NB: For the time being, only 32-bit kernels support
1039 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1040 * whether to apply espfix using paravirt hooks. If any
1041 * non-paravirt system ever shows up that does *not* have the
1042 * ESPFIX issue, we can change this.
1044 #ifdef CONFIG_X86_32
1045 # ifdef CONFIG_PARAVIRT
1047 extern void native_iret(void);
1048 if (pv_cpu_ops.iret == native_iret)
1049 set_cpu_bug(c, X86_BUG_ESPFIX);
1052 set_cpu_bug(c, X86_BUG_ESPFIX);
1057 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1060 * The heavy lifting of max_rmid and cache_occ_scale are handled
1061 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1062 * in case CQM bits really aren't there in this CPU.
1064 if (c != &boot_cpu_data) {
1065 boot_cpu_data.x86_cache_max_rmid =
1066 min(boot_cpu_data.x86_cache_max_rmid,
1067 c->x86_cache_max_rmid);
1072 * Validate that ACPI/mptables have the same information about the
1073 * effective APIC id and update the package map.
1075 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1078 unsigned int apicid, cpu = smp_processor_id();
1080 apicid = apic->cpu_present_to_apicid(cpu);
1082 if (apicid != c->apicid) {
1083 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1084 cpu, apicid, c->initial_apicid);
1086 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1088 c->logical_proc_id = 0;
1093 * This does the hard work of actually picking apart the CPU stuff...
1095 static void identify_cpu(struct cpuinfo_x86 *c)
1099 c->loops_per_jiffy = loops_per_jiffy;
1100 c->x86_cache_size = -1;
1101 c->x86_vendor = X86_VENDOR_UNKNOWN;
1102 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1103 c->x86_vendor_id[0] = '\0'; /* Unset */
1104 c->x86_model_id[0] = '\0'; /* Unset */
1105 c->x86_max_cores = 1;
1106 c->x86_coreid_bits = 0;
1108 #ifdef CONFIG_X86_64
1109 c->x86_clflush_size = 64;
1110 c->x86_phys_bits = 36;
1111 c->x86_virt_bits = 48;
1113 c->cpuid_level = -1; /* CPUID not detected */
1114 c->x86_clflush_size = 32;
1115 c->x86_phys_bits = 32;
1116 c->x86_virt_bits = 32;
1118 c->x86_cache_alignment = c->x86_clflush_size;
1119 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1121 generic_identify(c);
1123 if (this_cpu->c_identify)
1124 this_cpu->c_identify(c);
1126 /* Clear/Set all flags overridden by options, after probe */
1127 apply_forced_caps(c);
1129 #ifdef CONFIG_X86_64
1130 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1134 * Vendor-specific initialization. In this section we
1135 * canonicalize the feature flags, meaning if there are
1136 * features a certain CPU supports which CPUID doesn't
1137 * tell us, CPUID claiming incorrect flags, or other bugs,
1138 * we handle them here.
1140 * At the end of this section, c->x86_capability better
1141 * indicate the features this CPU genuinely supports!
1143 if (this_cpu->c_init)
1144 this_cpu->c_init(c);
1146 /* Disable the PN if appropriate */
1147 squash_the_stupid_serial_number(c);
1149 /* Set up SMEP/SMAP */
1154 * The vendor-specific functions might have changed features.
1155 * Now we do "generic changes."
1158 /* Filter out anything that depends on CPUID levels we don't have */
1159 filter_cpuid_features(c, true);
1161 /* If the model name is still unset, do table lookup. */
1162 if (!c->x86_model_id[0]) {
1164 p = table_lookup_model(c);
1166 strcpy(c->x86_model_id, p);
1168 /* Last resort... */
1169 sprintf(c->x86_model_id, "%02x/%02x",
1170 c->x86, c->x86_model);
1173 #ifdef CONFIG_X86_64
1178 x86_init_cache_qos(c);
1182 * Clear/Set all flags overridden by options, need do it
1183 * before following smp all cpus cap AND.
1185 apply_forced_caps(c);
1188 * On SMP, boot_cpu_data holds the common feature set between
1189 * all CPUs; so make sure that we indicate which features are
1190 * common between the CPUs. The first time this routine gets
1191 * executed, c == &boot_cpu_data.
1193 if (c != &boot_cpu_data) {
1194 /* AND the already accumulated flags with these */
1195 for (i = 0; i < NCAPINTS; i++)
1196 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1198 /* OR, i.e. replicate the bug flags */
1199 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1200 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1203 /* Init Machine Check Exception if available. */
1206 select_idle_routine(c);
1209 numa_add_cpu(smp_processor_id());
1214 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1215 * on 32-bit kernels:
1217 #ifdef CONFIG_X86_32
1218 void enable_sep_cpu(void)
1220 struct tss_struct *tss;
1223 if (!boot_cpu_has(X86_FEATURE_SEP))
1227 tss = &per_cpu(cpu_tss_rw, cpu);
1230 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1231 * see the big comment in struct x86_hw_tss's definition.
1234 tss->x86_tss.ss1 = __KERNEL_CS;
1235 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1236 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1237 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1243 void __init identify_boot_cpu(void)
1245 identify_cpu(&boot_cpu_data);
1246 #ifdef CONFIG_X86_32
1250 cpu_detect_tlb(&boot_cpu_data);
1253 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1255 BUG_ON(c == &boot_cpu_data);
1257 #ifdef CONFIG_X86_32
1261 validate_apic_and_package_id(c);
1264 static __init int setup_noclflush(char *arg)
1266 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1267 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1270 __setup("noclflush", setup_noclflush);
1272 void print_cpu_info(struct cpuinfo_x86 *c)
1274 const char *vendor = NULL;
1276 if (c->x86_vendor < X86_VENDOR_NUM) {
1277 vendor = this_cpu->c_vendor;
1279 if (c->cpuid_level >= 0)
1280 vendor = c->x86_vendor_id;
1283 if (vendor && !strstr(c->x86_model_id, vendor))
1284 pr_cont("%s ", vendor);
1286 if (c->x86_model_id[0])
1287 pr_cont("%s", c->x86_model_id);
1289 pr_cont("%d86", c->x86);
1291 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1293 if (c->x86_mask || c->cpuid_level >= 0)
1294 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1300 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1301 * But we need to keep a dummy __setup around otherwise it would
1302 * show up as an environment variable for init.
1304 static __init int setup_clearcpuid(char *arg)
1308 __setup("clearcpuid=", setup_clearcpuid);
1310 #ifdef CONFIG_X86_64
1311 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1312 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1315 * The following percpu variables are hot. Align current_task to
1316 * cacheline size such that they fall in the same cacheline.
1318 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1320 EXPORT_PER_CPU_SYMBOL(current_task);
1322 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1323 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1325 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1327 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1328 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1330 /* May not be marked __init: used by software suspend */
1331 void syscall_init(void)
1333 extern char _entry_trampoline[];
1334 extern char entry_SYSCALL_64_trampoline[];
1336 int cpu = smp_processor_id();
1337 unsigned long SYSCALL64_entry_trampoline =
1338 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1339 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1341 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1342 if (static_cpu_has(X86_FEATURE_PTI))
1343 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1345 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1347 #ifdef CONFIG_IA32_EMULATION
1348 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1350 * This only works on Intel CPUs.
1351 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1352 * This does not cause SYSENTER to jump to the wrong location, because
1353 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1355 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1356 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
1357 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1359 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1360 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1361 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1362 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1365 /* Flags to clear on syscall */
1366 wrmsrl(MSR_SYSCALL_MASK,
1367 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1368 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1372 * Copies of the original ist values from the tss are only accessed during
1373 * debugging, no special alignment required.
1375 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1377 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1378 DEFINE_PER_CPU(int, debug_stack_usage);
1380 int is_debug_stack(unsigned long addr)
1382 return __this_cpu_read(debug_stack_usage) ||
1383 (addr <= __this_cpu_read(debug_stack_addr) &&
1384 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1386 NOKPROBE_SYMBOL(is_debug_stack);
1388 DEFINE_PER_CPU(u32, debug_idt_ctr);
1390 void debug_stack_set_zero(void)
1392 this_cpu_inc(debug_idt_ctr);
1395 NOKPROBE_SYMBOL(debug_stack_set_zero);
1397 void debug_stack_reset(void)
1399 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1401 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1404 NOKPROBE_SYMBOL(debug_stack_reset);
1406 #else /* CONFIG_X86_64 */
1408 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1409 EXPORT_PER_CPU_SYMBOL(current_task);
1410 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1411 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1414 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1415 * the top of the kernel stack. Use an extra percpu variable to track the
1416 * top of the kernel stack directly.
1418 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1419 (unsigned long)&init_thread_union + THREAD_SIZE;
1420 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1422 #ifdef CONFIG_CC_STACKPROTECTOR
1423 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1426 #endif /* CONFIG_X86_64 */
1429 * Clear all 6 debug registers:
1431 static void clear_all_debug_regs(void)
1435 for (i = 0; i < 8; i++) {
1436 /* Ignore db4, db5 */
1437 if ((i == 4) || (i == 5))
1446 * Restore debug regs if using kgdbwait and you have a kernel debugger
1447 * connection established.
1449 static void dbg_restore_debug_regs(void)
1451 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1452 arch_kgdb_ops.correct_hw_break();
1454 #else /* ! CONFIG_KGDB */
1455 #define dbg_restore_debug_regs()
1456 #endif /* ! CONFIG_KGDB */
1458 static void wait_for_master_cpu(int cpu)
1462 * wait for ACK from master CPU before continuing
1463 * with AP initialization
1465 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1466 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1472 * cpu_init() initializes state that is per-CPU. Some data is already
1473 * initialized (naturally) in the bootstrap process, such as the GDT
1474 * and IDT. We reload them nevertheless, this function acts as a
1475 * 'CPU state barrier', nothing should get across.
1476 * A lot of state is already set up in PDA init for 64 bit
1478 #ifdef CONFIG_X86_64
1482 struct orig_ist *oist;
1483 struct task_struct *me;
1484 struct tss_struct *t;
1486 int cpu = raw_smp_processor_id();
1489 wait_for_master_cpu(cpu);
1492 * Initialize the CR4 shadow before doing anything that could
1500 t = &per_cpu(cpu_tss_rw, cpu);
1501 oist = &per_cpu(orig_ist, cpu);
1504 if (this_cpu_read(numa_node) == 0 &&
1505 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1506 set_numa_node(early_cpu_to_node(cpu));
1511 pr_debug("Initializing CPU#%d\n", cpu);
1513 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1516 * Initialize the per-CPU GDT with the boot GDT,
1517 * and set up the GDT descriptor:
1520 switch_to_new_gdt(cpu);
1525 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1528 wrmsrl(MSR_FS_BASE, 0);
1529 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1536 * set up and load the per-CPU TSS
1538 if (!oist->ist[0]) {
1539 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1541 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1542 estacks += exception_stack_sizes[v];
1543 oist->ist[v] = t->x86_tss.ist[v] =
1544 (unsigned long)estacks;
1545 if (v == DEBUG_STACK-1)
1546 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1550 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1553 * <= is required because the CPU will access up to
1554 * 8 bits beyond the end of the IO permission bitmap.
1556 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1557 t->io_bitmap[i] = ~0UL;
1560 me->active_mm = &init_mm;
1562 initialize_tlbstate_and_flush();
1563 enter_lazy_tlb(&init_mm, me);
1566 * Initialize the TSS. sp0 points to the entry trampoline stack
1567 * regardless of what task is running.
1569 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1571 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1573 load_mm_ldt(&init_mm);
1575 clear_all_debug_regs();
1576 dbg_restore_debug_regs();
1583 load_fixmap_gdt(cpu);
1590 int cpu = smp_processor_id();
1591 struct task_struct *curr = current;
1592 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1594 wait_for_master_cpu(cpu);
1597 * Initialize the CR4 shadow before doing anything that could
1602 show_ucode_info_early();
1604 pr_info("Initializing CPU#%d\n", cpu);
1606 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1607 boot_cpu_has(X86_FEATURE_TSC) ||
1608 boot_cpu_has(X86_FEATURE_DE))
1609 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1612 switch_to_new_gdt(cpu);
1615 * Set up and load the per-CPU TSS and LDT
1618 curr->active_mm = &init_mm;
1620 initialize_tlbstate_and_flush();
1621 enter_lazy_tlb(&init_mm, curr);
1624 * Initialize the TSS. Don't bother initializing sp0, as the initial
1625 * task never enters user mode.
1627 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1630 load_mm_ldt(&init_mm);
1632 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1634 #ifdef CONFIG_DOUBLEFAULT
1635 /* Set up doublefault TSS pointer in the GDT */
1636 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1639 clear_all_debug_regs();
1640 dbg_restore_debug_regs();
1644 load_fixmap_gdt(cpu);
1648 static void bsp_resume(void)
1650 if (this_cpu->c_bsp_resume)
1651 this_cpu->c_bsp_resume(&boot_cpu_data);
1654 static struct syscore_ops cpu_syscore_ops = {
1655 .resume = bsp_resume,
1658 static int __init init_cpu_syscore(void)
1660 register_syscore_ops(&cpu_syscore_ops);
1663 core_initcall(init_cpu_syscore);