2 * Thermal throttle event support code (such as syslog messaging and rate
3 * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
5 * This allows consistent reporting of CPU thermal throttle events.
7 * Maintains a counter in /sys that keeps track of the number of thermal
8 * events, such that the user knows how bad the thermal problem might be
9 * (since the logging to syslog is rate limited).
11 * Author: Dmitriy Zavin (dmitriyz@google.com)
13 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
14 * Inspired by Ross Biro's and Al Borchers' counter code.
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/jiffies.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/export.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/smp.h>
25 #include <linux/cpu.h>
27 #include <asm/processor.h>
28 #include <asm/traps.h>
32 #include <asm/trace/irq_vectors.h>
36 /* How long to wait between reporting thermal events */
37 #define CHECK_INTERVAL (300 * HZ)
39 #define THERMAL_THROTTLING_EVENT 0
40 #define POWER_LIMIT_EVENT 1
43 * Current thermal event state:
45 struct _thermal_state {
50 unsigned long last_count;
53 struct thermal_state {
54 struct _thermal_state core_throttle;
55 struct _thermal_state core_power_limit;
56 struct _thermal_state package_throttle;
57 struct _thermal_state package_power_limit;
58 struct _thermal_state core_thresh0;
59 struct _thermal_state core_thresh1;
60 struct _thermal_state pkg_thresh0;
61 struct _thermal_state pkg_thresh1;
64 /* Callback to handle core threshold interrupts */
65 int (*platform_thermal_notify)(__u64 msr_val);
66 EXPORT_SYMBOL(platform_thermal_notify);
68 /* Callback to handle core package threshold_interrupts */
69 int (*platform_thermal_package_notify)(__u64 msr_val);
70 EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
72 /* Callback support of rate control, return true, if
73 * callback has rate control */
74 bool (*platform_thermal_package_rate_control)(void);
75 EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
78 static DEFINE_PER_CPU(struct thermal_state, thermal_state);
80 static atomic_t therm_throt_en = ATOMIC_INIT(0);
82 static u32 lvtthmr_init __read_mostly;
85 #define define_therm_throt_device_one_ro(_name) \
86 static DEVICE_ATTR(_name, 0444, \
87 therm_throt_device_show_##_name, \
90 #define define_therm_throt_device_show_func(event, name) \
92 static ssize_t therm_throt_device_show_##event##_##name( \
94 struct device_attribute *attr, \
97 unsigned int cpu = dev->id; \
100 preempt_disable(); /* CPU hotplug */ \
101 if (cpu_online(cpu)) { \
102 ret = sprintf(buf, "%lu\n", \
103 per_cpu(thermal_state, cpu).event.name); \
111 define_therm_throt_device_show_func(core_throttle, count);
112 define_therm_throt_device_one_ro(core_throttle_count);
114 define_therm_throt_device_show_func(core_power_limit, count);
115 define_therm_throt_device_one_ro(core_power_limit_count);
117 define_therm_throt_device_show_func(package_throttle, count);
118 define_therm_throt_device_one_ro(package_throttle_count);
120 define_therm_throt_device_show_func(package_power_limit, count);
121 define_therm_throt_device_one_ro(package_power_limit_count);
123 static struct attribute *thermal_throttle_attrs[] = {
124 &dev_attr_core_throttle_count.attr,
128 static const struct attribute_group thermal_attr_group = {
129 .attrs = thermal_throttle_attrs,
130 .name = "thermal_throttle"
132 #endif /* CONFIG_SYSFS */
135 #define PACKAGE_LEVEL 1
138 * therm_throt_process - Process thermal throttling event from interrupt
139 * @curr: Whether the condition is current or not (boolean), since the
140 * thermal interrupt normally gets called both when the thermal
141 * event begins and once the event has ended.
143 * This function is called by the thermal interrupt after the
144 * IRQ has been acknowledged.
146 * It will take care of rate limiting and printing messages to the syslog.
148 static void therm_throt_process(bool new_event, int event, int level)
150 struct _thermal_state *state;
151 unsigned int this_cpu = smp_processor_id();
154 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
156 now = get_jiffies_64();
157 if (level == CORE_LEVEL) {
158 if (event == THERMAL_THROTTLING_EVENT)
159 state = &pstate->core_throttle;
160 else if (event == POWER_LIMIT_EVENT)
161 state = &pstate->core_power_limit;
164 } else if (level == PACKAGE_LEVEL) {
165 if (event == THERMAL_THROTTLING_EVENT)
166 state = &pstate->package_throttle;
167 else if (event == POWER_LIMIT_EVENT)
168 state = &pstate->package_power_limit;
174 old_event = state->new_event;
175 state->new_event = new_event;
180 if (time_before64(now, state->next_check) &&
181 state->count != state->last_count)
184 state->next_check = now + CHECK_INTERVAL;
185 state->last_count = state->count;
187 /* if we just entered the thermal event */
189 if (event == THERMAL_THROTTLING_EVENT)
190 pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
192 level == CORE_LEVEL ? "Core" : "Package",
197 if (event == THERMAL_THROTTLING_EVENT)
198 pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
199 level == CORE_LEVEL ? "Core" : "Package");
204 static int thresh_event_valid(int level, int event)
206 struct _thermal_state *state;
207 unsigned int this_cpu = smp_processor_id();
208 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
209 u64 now = get_jiffies_64();
211 if (level == PACKAGE_LEVEL)
212 state = (event == 0) ? &pstate->pkg_thresh0 :
213 &pstate->pkg_thresh1;
215 state = (event == 0) ? &pstate->core_thresh0 :
216 &pstate->core_thresh1;
218 if (time_before64(now, state->next_check))
221 state->next_check = now + CHECK_INTERVAL;
226 static bool int_pln_enable;
227 static int __init int_pln_enable_setup(char *s)
229 int_pln_enable = true;
233 __setup("int_pln_enable", int_pln_enable_setup);
236 /* Add/Remove thermal_throttle interface for CPU device: */
237 static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
240 struct cpuinfo_x86 *c = &cpu_data(cpu);
242 err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
246 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
247 err = sysfs_add_file_to_group(&dev->kobj,
248 &dev_attr_core_power_limit_count.attr,
249 thermal_attr_group.name);
250 if (cpu_has(c, X86_FEATURE_PTS)) {
251 err = sysfs_add_file_to_group(&dev->kobj,
252 &dev_attr_package_throttle_count.attr,
253 thermal_attr_group.name);
254 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
255 err = sysfs_add_file_to_group(&dev->kobj,
256 &dev_attr_package_power_limit_count.attr,
257 thermal_attr_group.name);
263 static void thermal_throttle_remove_dev(struct device *dev)
265 sysfs_remove_group(&dev->kobj, &thermal_attr_group);
268 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
269 static int thermal_throttle_online(unsigned int cpu)
271 struct device *dev = get_cpu_device(cpu);
273 return thermal_throttle_add_dev(dev, cpu);
276 static int thermal_throttle_offline(unsigned int cpu)
278 struct device *dev = get_cpu_device(cpu);
280 thermal_throttle_remove_dev(dev);
284 static __init int thermal_throttle_init_device(void)
288 if (!atomic_read(&therm_throt_en))
291 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online",
292 thermal_throttle_online,
293 thermal_throttle_offline);
294 return ret < 0 ? ret : 0;
296 device_initcall(thermal_throttle_init_device);
298 #endif /* CONFIG_SYSFS */
300 static void notify_package_thresholds(__u64 msr_val)
302 bool notify_thres_0 = false;
303 bool notify_thres_1 = false;
305 if (!platform_thermal_package_notify)
308 /* lower threshold check */
309 if (msr_val & THERM_LOG_THRESHOLD0)
310 notify_thres_0 = true;
311 /* higher threshold check */
312 if (msr_val & THERM_LOG_THRESHOLD1)
313 notify_thres_1 = true;
315 if (!notify_thres_0 && !notify_thres_1)
318 if (platform_thermal_package_rate_control &&
319 platform_thermal_package_rate_control()) {
320 /* Rate control is implemented in callback */
321 platform_thermal_package_notify(msr_val);
325 /* lower threshold reached */
326 if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
327 platform_thermal_package_notify(msr_val);
328 /* higher threshold reached */
329 if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
330 platform_thermal_package_notify(msr_val);
333 static void notify_thresholds(__u64 msr_val)
335 /* check whether the interrupt handler is defined;
336 * otherwise simply return
338 if (!platform_thermal_notify)
341 /* lower threshold reached */
342 if ((msr_val & THERM_LOG_THRESHOLD0) &&
343 thresh_event_valid(CORE_LEVEL, 0))
344 platform_thermal_notify(msr_val);
345 /* higher threshold reached */
346 if ((msr_val & THERM_LOG_THRESHOLD1) &&
347 thresh_event_valid(CORE_LEVEL, 1))
348 platform_thermal_notify(msr_val);
351 /* Thermal transition interrupt handler */
352 static void intel_thermal_interrupt(void)
356 if (static_cpu_has(X86_FEATURE_HWP))
357 wrmsrl_safe(MSR_HWP_STATUS, 0);
359 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
361 /* Check for violation of core thermal thresholds*/
362 notify_thresholds(msr_val);
364 therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
365 THERMAL_THROTTLING_EVENT,
368 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
369 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
373 if (this_cpu_has(X86_FEATURE_PTS)) {
374 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
375 /* check violations of package thermal thresholds */
376 notify_package_thresholds(msr_val);
377 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
378 THERMAL_THROTTLING_EVENT,
380 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
381 therm_throt_process(msr_val &
382 PACKAGE_THERM_STATUS_POWER_LIMIT,
388 static void unexpected_thermal_interrupt(void)
390 pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
394 static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
396 asmlinkage __visible void __irq_entry smp_thermal_interrupt(struct pt_regs *regs)
399 trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
400 inc_irq_stat(irq_thermal_count);
401 smp_thermal_vector();
402 trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
406 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
407 static int intel_thermal_supported(struct cpuinfo_x86 *c)
409 if (!boot_cpu_has(X86_FEATURE_APIC))
411 if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
416 void __init mcheck_intel_therm_init(void)
419 * This function is only called on boot CPU. Save the init thermal
420 * LVT value on BSP and use that value to restore APs' thermal LVT
421 * entry BIOS programmed later
423 if (intel_thermal_supported(&boot_cpu_data))
424 lvtthmr_init = apic_read(APIC_LVTTHMR);
427 void intel_init_thermal(struct cpuinfo_x86 *c)
429 unsigned int cpu = smp_processor_id();
433 if (!intel_thermal_supported(c))
437 * First check if its enabled already, in which case there might
438 * be some SMM goo which handles it, so we can't even put a handler
439 * since it might be delivered via SMI already:
441 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
445 * The initial value of thermal LVT entries on all APs always reads
446 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
447 * sequence to them and LVT registers are reset to 0s except for
448 * the mask bits which are set to 1s when APs receive INIT IPI.
449 * If BIOS takes over the thermal interrupt and sets its interrupt
450 * delivery mode to SMI (not fixed), it restores the value that the
451 * BIOS has programmed on AP based on BSP's info we saved since BIOS
452 * is always setting the same value for all threads/cores.
454 if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
455 apic_write(APIC_LVTTHMR, lvtthmr_init);
458 if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
459 if (system_state == SYSTEM_BOOTING)
460 pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
464 /* early Pentium M models use different method for enabling TM2 */
465 if (cpu_has(c, X86_FEATURE_TM2)) {
466 if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
467 rdmsr(MSR_THERM2_CTL, l, h);
468 if (l & MSR_THERM2_CTL_TM_SELECT)
470 } else if (l & MSR_IA32_MISC_ENABLE_TM2)
474 /* We'll mask the thermal vector in the lapic till we're ready: */
475 h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
476 apic_write(APIC_LVTTHMR, h);
478 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
479 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
480 wrmsr(MSR_IA32_THERM_INTERRUPT,
481 (l | (THERM_INT_LOW_ENABLE
482 | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
483 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
484 wrmsr(MSR_IA32_THERM_INTERRUPT,
485 l | (THERM_INT_LOW_ENABLE
486 | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
488 wrmsr(MSR_IA32_THERM_INTERRUPT,
489 l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
491 if (cpu_has(c, X86_FEATURE_PTS)) {
492 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
493 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
494 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
495 (l | (PACKAGE_THERM_INT_LOW_ENABLE
496 | PACKAGE_THERM_INT_HIGH_ENABLE))
497 & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
498 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
499 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
500 l | (PACKAGE_THERM_INT_LOW_ENABLE
501 | PACKAGE_THERM_INT_HIGH_ENABLE
502 | PACKAGE_THERM_INT_PLN_ENABLE), h);
504 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
505 l | (PACKAGE_THERM_INT_LOW_ENABLE
506 | PACKAGE_THERM_INT_HIGH_ENABLE), h);
509 smp_thermal_vector = intel_thermal_interrupt;
511 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
512 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
514 /* Unmask the thermal vector: */
515 l = apic_read(APIC_LVTTHMR);
516 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
518 pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
519 tm2 ? "TM2" : "TM1");
521 /* enable thermal throttle processing */
522 atomic_set(&therm_throt_en, 1);