arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14 #include <linux/irqdomain.h>
  15
  16 #include <asm/fixmap.h>
  17 #include <asm/hpet.h>
  18 #include <asm/time.h>
  19
  20 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  21
  22 /* FSEC = 10^-15
  23    NSEC = 10^-9 */
  24 #define FSEC_PER_NSEC                   1000000L
  25
  26 #define HPET_DEV_USED_BIT               2
  27 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  28 #define HPET_DEV_VALID                  0x8
  29 #define HPET_DEV_FSB_CAP                0x1000
  30 #define HPET_DEV_PERI_CAP               0x2000
  31
  32 #define HPET_MIN_CYCLES                 128
  33 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  34
  35 /*
  36  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  37  */
  38 unsigned long                           hpet_address;
  39 u8                                      hpet_blockid; /* OS timer block num */
  40 u8                                      hpet_msi_disable;
  41
  42 #ifdef CONFIG_PCI_MSI
  43 static unsigned long                    hpet_num_timers;
  44 #endif
  45 static void __iomem                     *hpet_virt_address;
  46
  47 struct hpet_dev {
  48         struct clock_event_device       evt;
  49         unsigned int                    num;
  50         int                             cpu;
  51         unsigned int                    irq;
  52         unsigned int                    flags;
  53         char                            name[10];
  54 };
  55
  56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  57 {
  58         return container_of(evtdev, struct hpet_dev, evt);
  59 }
  60
  61 inline unsigned int hpet_readl(unsigned int a)
  62 {
  63         return readl(hpet_virt_address + a);
  64 }
  65
  66 static inline void hpet_writel(unsigned int d, unsigned int a)
  67 {
  68         writel(d, hpet_virt_address + a);
  69 }
  70
  71 #ifdef CONFIG_X86_64
  72 #include <asm/pgtable.h>
  73 #endif
  74
  75 static inline void hpet_set_mapping(void)
  76 {
  77         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  78 }
  79
  80 static inline void hpet_clear_mapping(void)
  81 {
  82         iounmap(hpet_virt_address);
  83         hpet_virt_address = NULL;
  84 }
  85
  86 /*
  87  * HPET command line enable / disable
  88  */
  89 int boot_hpet_disable;
  90 int hpet_force_user;
  91 static int hpet_verbose;
  92
  93 static int __init hpet_setup(char *str)
  94 {
  95         while (str) {
  96                 char *next = strchr(str, ',');
  97
  98                 if (next)
  99                         *next++ = 0;
 100                 if (!strncmp("disable", str, 7))
 101                         boot_hpet_disable = 1;
 102                 if (!strncmp("force", str, 5))
 103                         hpet_force_user = 1;
 104                 if (!strncmp("verbose", str, 7))
 105                         hpet_verbose = 1;
 106                 str = next;
 107         }
 108         return 1;
 109 }
 110 __setup("hpet=", hpet_setup);
 111
 112 static int __init disable_hpet(char *str)
 113 {
 114         boot_hpet_disable = 1;
 115         return 1;
 116 }
 117 __setup("nohpet", disable_hpet);
 118
 119 static inline int is_hpet_capable(void)
 120 {
 121         return !boot_hpet_disable && hpet_address;
 122 }
 123
 124 /*
 125  * HPET timer interrupt enable / disable
 126  */
 127 static int hpet_legacy_int_enabled;
 128
 129 /**
 130  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 131  */
 132 int is_hpet_enabled(void)
 133 {
 134         return is_hpet_capable() && hpet_legacy_int_enabled;
 135 }
 136 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 137
 138 static void _hpet_print_config(const char *function, int line)
 139 {
 140         u32 i, timers, l, h;
 141         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 142         l = hpet_readl(HPET_ID);
 143         h = hpet_readl(HPET_PERIOD);
 144         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 145         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 146         l = hpet_readl(HPET_CFG);
 147         h = hpet_readl(HPET_STATUS);
 148         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 149         l = hpet_readl(HPET_COUNTER);
 150         h = hpet_readl(HPET_COUNTER+4);
 151         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 152
 153         for (i = 0; i < timers; i++) {
 154                 l = hpet_readl(HPET_Tn_CFG(i));
 155                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 156                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 157                        i, l, h);
 158                 l = hpet_readl(HPET_Tn_CMP(i));
 159                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 160                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 161                        i, l, h);
 162                 l = hpet_readl(HPET_Tn_ROUTE(i));
 163                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 164                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 165                        i, l, h);
 166         }
 167 }
 168
 169 #define hpet_print_config()                                     \
 170 do {                                                            \
 171         if (hpet_verbose)                                       \
 172                 _hpet_print_config(__func__, __LINE__); \
 173 } while (0)
 174
 175 /*
 176  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 177  * timer 0 and timer 1 in case of RTC emulation.
 178  */
 179 #ifdef CONFIG_HPET
 180
 181 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 182
 183 static void hpet_reserve_platform_timers(unsigned int id)
 184 {
 185         struct hpet __iomem *hpet = hpet_virt_address;
 186         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 187         unsigned int nrtimers, i;
 188         struct hpet_data hd;
 189
 190         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 191
 192         memset(&hd, 0, sizeof(hd));
 193         hd.hd_phys_address      = hpet_address;
 194         hd.hd_address           = hpet;
 195         hd.hd_nirqs             = nrtimers;
 196         hpet_reserve_timer(&hd, 0);
 197
 198 #ifdef CONFIG_HPET_EMULATE_RTC
 199         hpet_reserve_timer(&hd, 1);
 200 #endif
 201
 202         /*
 203          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 204          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 205          * don't bother configuring *any* comparator interrupts.
 206          */
 207         hd.hd_irq[0] = HPET_LEGACY_8254;
 208         hd.hd_irq[1] = HPET_LEGACY_RTC;
 209
 210         for (i = 2; i < nrtimers; timer++, i++) {
 211                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 212                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 213         }
 214
 215         hpet_reserve_msi_timers(&hd);
 216
 217         hpet_alloc(&hd);
 218
 219 }
 220 #else
 221 static void hpet_reserve_platform_timers(unsigned int id) { }
 222 #endif
 223
 224 /*
 225  * Common hpet info
 226  */
 227 static unsigned long hpet_freq;
 228
 229 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 230                           struct clock_event_device *evt);
 231 static int hpet_legacy_next_event(unsigned long delta,
 232                            struct clock_event_device *evt);
 233
 234 /*
 235  * The hpet clock event device
 236  */
 237 static struct clock_event_device hpet_clockevent = {
 238         .name           = "hpet",
 239         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 240         .set_mode       = hpet_legacy_set_mode,
 241         .set_next_event = hpet_legacy_next_event,
 242         .irq            = 0,
 243         .rating         = 50,
 244 };
 245
 246 static void hpet_stop_counter(void)
 247 {
 248         unsigned long cfg = hpet_readl(HPET_CFG);
 249         cfg &= ~HPET_CFG_ENABLE;
 250         hpet_writel(cfg, HPET_CFG);
 251 }
 252
 253 static void hpet_reset_counter(void)
 254 {
 255         hpet_writel(0, HPET_COUNTER);
 256         hpet_writel(0, HPET_COUNTER + 4);
 257 }
 258
 259 static void hpet_start_counter(void)
 260 {
 261         unsigned int cfg = hpet_readl(HPET_CFG);
 262         cfg |= HPET_CFG_ENABLE;
 263         hpet_writel(cfg, HPET_CFG);
 264 }
 265
 266 static void hpet_restart_counter(void)
 267 {
 268         hpet_stop_counter();
 269         hpet_reset_counter();
 270         hpet_start_counter();
 271 }
 272
 273 static void hpet_resume_device(void)
 274 {
 275         force_hpet_resume();
 276 }
 277
 278 static void hpet_resume_counter(struct clocksource *cs)
 279 {
 280         hpet_resume_device();
 281         hpet_restart_counter();
 282 }
 283
 284 static void hpet_enable_legacy_int(void)
 285 {
 286         unsigned int cfg = hpet_readl(HPET_CFG);
 287
 288         cfg |= HPET_CFG_LEGACY;
 289         hpet_writel(cfg, HPET_CFG);
 290         hpet_legacy_int_enabled = 1;
 291 }
 292
 293 static void hpet_legacy_clockevent_register(void)
 294 {
 295         /* Start HPET legacy interrupts */
 296         hpet_enable_legacy_int();
 297
 298         /*
 299          * Start hpet with the boot cpu mask and make it
 300          * global after the IO_APIC has been initialized.
 301          */
 302         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 303         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 304                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 305         global_clock_event = &hpet_clockevent;
 306         printk(KERN_DEBUG "hpet clockevent registered\n");
 307 }
 308
 309 static int hpet_setup_msi_irq(unsigned int irq);
 310
 311 static void hpet_set_mode(enum clock_event_mode mode,
 312                           struct clock_event_device *evt, int timer)
 313 {
 314         unsigned int cfg, cmp, now;
 315         uint64_t delta;
 316
 317         switch (mode) {
 318         case CLOCK_EVT_MODE_PERIODIC:
 319                 hpet_stop_counter();
 320                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 321                 delta >>= evt->shift;
 322                 now = hpet_readl(HPET_COUNTER);
 323                 cmp = now + (unsigned int) delta;
 324                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 325                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 326                        HPET_TN_SETVAL | HPET_TN_32BIT;
 327                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 328                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 329                 udelay(1);
 330                 /*
 331                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 332                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 333                  * bit is automatically cleared after the first write.
 334                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 335                  * Publication # 24674)
 336                  */
 337                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 338                 hpet_start_counter();
 339                 hpet_print_config();
 340                 break;
 341
 342         case CLOCK_EVT_MODE_ONESHOT:
 343                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 344                 cfg &= ~HPET_TN_PERIODIC;
 345                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 346                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 347                 break;
 348
 349         case CLOCK_EVT_MODE_UNUSED:
 350         case CLOCK_EVT_MODE_SHUTDOWN:
 351                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 352                 cfg &= ~HPET_TN_ENABLE;
 353                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 354                 break;
 355
 356         case CLOCK_EVT_MODE_RESUME:
 357                 if (timer == 0) {
 358                         hpet_enable_legacy_int();
 359                 } else {
 360                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 361                         hpet_setup_msi_irq(hdev->irq);
 362                         disable_irq(hdev->irq);
 363                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 364                         enable_irq(hdev->irq);
 365                 }
 366                 hpet_print_config();
 367                 break;
 368         }
 369 }
 370
 371 static int hpet_next_event(unsigned long delta,
 372                            struct clock_event_device *evt, int timer)
 373 {
 374         u32 cnt;
 375         s32 res;
 376
 377         cnt = hpet_readl(HPET_COUNTER);
 378         cnt += (u32) delta;
 379         hpet_writel(cnt, HPET_Tn_CMP(timer));
 380
 381         /*
 382          * HPETs are a complete disaster. The compare register is
 383          * based on a equal comparison and neither provides a less
 384          * than or equal functionality (which would require to take
 385          * the wraparound into account) nor a simple count down event
 386          * mode. Further the write to the comparator register is
 387          * delayed internally up to two HPET clock cycles in certain
 388          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 389          * longer delays. We worked around that by reading back the
 390          * compare register, but that required another workaround for
 391          * ICH9,10 chips where the first readout after write can
 392          * return the old stale value. We already had a minimum
 393          * programming delta of 5us enforced, but a NMI or SMI hitting
 394          * between the counter readout and the comparator write can
 395          * move us behind that point easily. Now instead of reading
 396          * the compare register back several times, we make the ETIME
 397          * decision based on the following: Return ETIME if the
 398          * counter value after the write is less than HPET_MIN_CYCLES
 399          * away from the event or if the counter is already ahead of
 400          * the event. The minimum programming delta for the generic
 401          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 402          */
 403         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 404
 405         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 406 }
 407
 408 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 409                         struct clock_event_device *evt)
 410 {
 411         hpet_set_mode(mode, evt, 0);
 412 }
 413
 414 static int hpet_legacy_next_event(unsigned long delta,
 415                         struct clock_event_device *evt)
 416 {
 417         return hpet_next_event(delta, evt, 0);
 418 }
 419
 420 /*
 421  * HPET MSI Support
 422  */
 423 #ifdef CONFIG_PCI_MSI
 424
 425 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 426 static struct hpet_dev  *hpet_devs;
 427
 428 void hpet_msi_unmask(struct irq_data *data)
 429 {
 430         struct hpet_dev *hdev = data->handler_data;
 431         unsigned int cfg;
 432
 433         /* unmask it */
 434         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 435         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 436         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 437 }
 438
 439 void hpet_msi_mask(struct irq_data *data)
 440 {
 441         struct hpet_dev *hdev = data->handler_data;
 442         unsigned int cfg;
 443
 444         /* mask it */
 445         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 446         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 447         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 448 }
 449
 450 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 451 {
 452         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 453         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 454 }
 455
 456 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 457 {
 458         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 459         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 460         msg->address_hi = 0;
 461 }
 462
 463 static void hpet_msi_set_mode(enum clock_event_mode mode,
 464                                 struct clock_event_device *evt)
 465 {
 466         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 467         hpet_set_mode(mode, evt, hdev->num);
 468 }
 469
 470 static int hpet_msi_next_event(unsigned long delta,
 471                                 struct clock_event_device *evt)
 472 {
 473         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 474         return hpet_next_event(delta, evt, hdev->num);
 475 }
 476
 477 static int hpet_setup_msi_irq(unsigned int irq)
 478 {
 479         if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
 480                 irq_domain_free_irqs(irq, 1);
 481                 return -EINVAL;
 482         }
 483         return 0;
 484 }
 485
 486 static int hpet_assign_irq(struct hpet_dev *dev)
 487 {
 488         int irq;
 489
 490         irq = irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL);
 491         if (irq <= 0)
 492                 return -EINVAL;
 493
 494         irq_set_handler_data(irq, dev);
 495
 496         if (hpet_setup_msi_irq(irq))
 497                 return -EINVAL;
 498
 499         dev->irq = irq;
 500         return 0;
 501 }
 502
 503 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 504 {
 505         struct hpet_dev *dev = (struct hpet_dev *)data;
 506         struct clock_event_device *hevt = &dev->evt;
 507
 508         if (!hevt->event_handler) {
 509                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 510                                 dev->num);
 511                 return IRQ_HANDLED;
 512         }
 513
 514         hevt->event_handler(hevt);
 515         return IRQ_HANDLED;
 516 }
 517
 518 static int hpet_setup_irq(struct hpet_dev *dev)
 519 {
 520
 521         if (request_irq(dev->irq, hpet_interrupt_handler,
 522                         IRQF_TIMER | IRQF_NOBALANCING,
 523                         dev->name, dev))
 524                 return -1;
 525
 526         disable_irq(dev->irq);
 527         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 528         enable_irq(dev->irq);
 529
 530         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 531                          dev->name, dev->irq);
 532
 533         return 0;
 534 }
 535
 536 /* This should be called in specific @cpu */
 537 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 538 {
 539         struct clock_event_device *evt = &hdev->evt;
 540
 541         WARN_ON(cpu != smp_processor_id());
 542         if (!(hdev->flags & HPET_DEV_VALID))
 543                 return;
 544
 545         if (hpet_setup_msi_irq(hdev->irq))
 546                 return;
 547
 548         hdev->cpu = cpu;
 549         per_cpu(cpu_hpet_dev, cpu) = hdev;
 550         evt->name = hdev->name;
 551         hpet_setup_irq(hdev);
 552         evt->irq = hdev->irq;
 553
 554         evt->rating = 110;
 555         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 556         if (hdev->flags & HPET_DEV_PERI_CAP)
 557                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 558
 559         evt->set_mode = hpet_msi_set_mode;
 560         evt->set_next_event = hpet_msi_next_event;
 561         evt->cpumask = cpumask_of(hdev->cpu);
 562
 563         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 564                                         0x7FFFFFFF);
 565 }
 566
 567 #ifdef CONFIG_HPET
 568 /* Reserve at least one timer for userspace (/dev/hpet) */
 569 #define RESERVE_TIMERS 1
 570 #else
 571 #define RESERVE_TIMERS 0
 572 #endif
 573
 574 static void hpet_msi_capability_lookup(unsigned int start_timer)
 575 {
 576         unsigned int id;
 577         unsigned int num_timers;
 578         unsigned int num_timers_used = 0;
 579         int i;
 580
 581         if (hpet_msi_disable)
 582                 return;
 583
 584         if (boot_cpu_has(X86_FEATURE_ARAT))
 585                 return;
 586         id = hpet_readl(HPET_ID);
 587
 588         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 589         num_timers++; /* Value read out starts from 0 */
 590         hpet_print_config();
 591
 592         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 593         if (!hpet_devs)
 594                 return;
 595
 596         hpet_num_timers = num_timers;
 597
 598         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 599                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 600                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 601
 602                 /* Only consider HPET timer with MSI support */
 603                 if (!(cfg & HPET_TN_FSB_CAP))
 604                         continue;
 605
 606                 hdev->flags = 0;
 607                 if (cfg & HPET_TN_PERIODIC_CAP)
 608                         hdev->flags |= HPET_DEV_PERI_CAP;
 609                 hdev->num = i;
 610
 611                 sprintf(hdev->name, "hpet%d", i);
 612                 if (hpet_assign_irq(hdev))
 613                         continue;
 614
 615                 hdev->flags |= HPET_DEV_FSB_CAP;
 616                 hdev->flags |= HPET_DEV_VALID;
 617                 num_timers_used++;
 618                 if (num_timers_used == num_possible_cpus())
 619                         break;
 620         }
 621
 622         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 623                 num_timers, num_timers_used);
 624 }
 625
 626 #ifdef CONFIG_HPET
 627 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 628 {
 629         int i;
 630
 631         if (!hpet_devs)
 632                 return;
 633
 634         for (i = 0; i < hpet_num_timers; i++) {
 635                 struct hpet_dev *hdev = &hpet_devs[i];
 636
 637                 if (!(hdev->flags & HPET_DEV_VALID))
 638                         continue;
 639
 640                 hd->hd_irq[hdev->num] = hdev->irq;
 641                 hpet_reserve_timer(hd, hdev->num);
 642         }
 643 }
 644 #endif
 645
 646 static struct hpet_dev *hpet_get_unused_timer(void)
 647 {
 648         int i;
 649
 650         if (!hpet_devs)
 651                 return NULL;
 652
 653         for (i = 0; i < hpet_num_timers; i++) {
 654                 struct hpet_dev *hdev = &hpet_devs[i];
 655
 656                 if (!(hdev->flags & HPET_DEV_VALID))
 657                         continue;
 658                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 659                         (unsigned long *)&hdev->flags))
 660                         continue;
 661                 return hdev;
 662         }
 663         return NULL;
 664 }
 665
 666 struct hpet_work_struct {
 667         struct delayed_work work;
 668         struct completion complete;
 669 };
 670
 671 static void hpet_work(struct work_struct *w)
 672 {
 673         struct hpet_dev *hdev;
 674         int cpu = smp_processor_id();
 675         struct hpet_work_struct *hpet_work;
 676
 677         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 678
 679         hdev = hpet_get_unused_timer();
 680         if (hdev)
 681                 init_one_hpet_msi_clockevent(hdev, cpu);
 682
 683         complete(&hpet_work->complete);
 684 }
 685
 686 static int hpet_cpuhp_notify(struct notifier_block *n,
 687                 unsigned long action, void *hcpu)
 688 {
 689         unsigned long cpu = (unsigned long)hcpu;
 690         struct hpet_work_struct work;
 691         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 692
 693         switch (action & 0xf) {
 694         case CPU_ONLINE:
 695                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 696                 init_completion(&work.complete);
 697                 /* FIXME: add schedule_work_on() */
 698                 schedule_delayed_work_on(cpu, &work.work, 0);
 699                 wait_for_completion(&work.complete);
 700                 destroy_delayed_work_on_stack(&work.work);
 701                 break;
 702         case CPU_DEAD:
 703                 if (hdev) {
 704                         free_irq(hdev->irq, hdev);
 705                         hdev->flags &= ~HPET_DEV_USED;
 706                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 707                 }
 708                 break;
 709         }
 710         return NOTIFY_OK;
 711 }
 712 #else
 713
 714 static int hpet_setup_msi_irq(unsigned int irq)
 715 {
 716         return 0;
 717 }
 718 static void hpet_msi_capability_lookup(unsigned int start_timer)
 719 {
 720         return;
 721 }
 722
 723 #ifdef CONFIG_HPET
 724 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 725 {
 726         return;
 727 }
 728 #endif
 729
 730 static int hpet_cpuhp_notify(struct notifier_block *n,
 731                 unsigned long action, void *hcpu)
 732 {
 733         return NOTIFY_OK;
 734 }
 735
 736 #endif
 737
 738 /*
 739  * Clock source related code
 740  */
 741 static cycle_t read_hpet(struct clocksource *cs)
 742 {
 743         return (cycle_t)hpet_readl(HPET_COUNTER);
 744 }
 745
 746 static struct clocksource clocksource_hpet = {
 747         .name           = "hpet",
 748         .rating         = 250,
 749         .read           = read_hpet,
 750         .mask           = HPET_MASK,
 751         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 752         .resume         = hpet_resume_counter,
 753         .archdata       = { .vclock_mode = VCLOCK_HPET },
 754 };
 755
 756 static int hpet_clocksource_register(void)
 757 {
 758         u64 start, now;
 759         cycle_t t1;
 760
 761         /* Start the counter */
 762         hpet_restart_counter();
 763
 764         /* Verify whether hpet counter works */
 765         t1 = hpet_readl(HPET_COUNTER);
 766         rdtscll(start);
 767
 768         /*
 769          * We don't know the TSC frequency yet, but waiting for
 770          * 200000 TSC cycles is safe:
 771          * 4 GHz == 50us
 772          * 1 GHz == 200us
 773          */
 774         do {
 775                 rep_nop();
 776                 rdtscll(now);
 777         } while ((now - start) < 200000UL);
 778
 779         if (t1 == hpet_readl(HPET_COUNTER)) {
 780                 printk(KERN_WARNING
 781                        "HPET counter not counting. HPET disabled\n");
 782                 return -ENODEV;
 783         }
 784
 785         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 786         return 0;
 787 }
 788
 789 static u32 *hpet_boot_cfg;
 790
 791 /**
 792  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 793  */
 794 int __init hpet_enable(void)
 795 {
 796         u32 hpet_period, cfg, id;
 797         u64 freq;
 798         unsigned int i, last;
 799
 800         if (!is_hpet_capable())
 801                 return 0;
 802
 803         hpet_set_mapping();
 804
 805         /*
 806          * Read the period and check for a sane value:
 807          */
 808         hpet_period = hpet_readl(HPET_PERIOD);
 809
 810         /*
 811          * AMD SB700 based systems with spread spectrum enabled use a
 812          * SMM based HPET emulation to provide proper frequency
 813          * setting. The SMM code is initialized with the first HPET
 814          * register access and takes some time to complete. During
 815          * this time the config register reads 0xffffffff. We check
 816          * for max. 1000 loops whether the config register reads a non
 817          * 0xffffffff value to make sure that HPET is up and running
 818          * before we go further. A counting loop is safe, as the HPET
 819          * access takes thousands of CPU cycles. On non SB700 based
 820          * machines this check is only done once and has no side
 821          * effects.
 822          */
 823         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 824                 if (i == 1000) {
 825                         printk(KERN_WARNING
 826                                "HPET config register value = 0xFFFFFFFF. "
 827                                "Disabling HPET\n");
 828                         goto out_nohpet;
 829                 }
 830         }
 831
 832         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 833                 goto out_nohpet;
 834
 835         /*
 836          * The period is a femto seconds value. Convert it to a
 837          * frequency.
 838          */
 839         freq = FSEC_PER_SEC;
 840         do_div(freq, hpet_period);
 841         hpet_freq = freq;
 842
 843         /*
 844          * Read the HPET ID register to retrieve the IRQ routing
 845          * information and the number of channels
 846          */
 847         id = hpet_readl(HPET_ID);
 848         hpet_print_config();
 849
 850         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 851
 852 #ifdef CONFIG_HPET_EMULATE_RTC
 853         /*
 854          * The legacy routing mode needs at least two channels, tick timer
 855          * and the rtc emulation channel.
 856          */
 857         if (!last)
 858                 goto out_nohpet;
 859 #endif
 860
 861         cfg = hpet_readl(HPET_CFG);
 862         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
 863                                 GFP_KERNEL);
 864         if (hpet_boot_cfg)
 865                 *hpet_boot_cfg = cfg;
 866         else
 867                 pr_warn("HPET initial state will not be saved\n");
 868         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
 869         hpet_writel(cfg, HPET_CFG);
 870         if (cfg)
 871                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
 872                         cfg);
 873
 874         for (i = 0; i <= last; ++i) {
 875                 cfg = hpet_readl(HPET_Tn_CFG(i));
 876                 if (hpet_boot_cfg)
 877                         hpet_boot_cfg[i + 1] = cfg;
 878                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
 879                 hpet_writel(cfg, HPET_Tn_CFG(i));
 880                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
 881                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
 882                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
 883                 if (cfg)
 884                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
 885                                 cfg, i);
 886         }
 887         hpet_print_config();
 888
 889         if (hpet_clocksource_register())
 890                 goto out_nohpet;
 891
 892         if (id & HPET_ID_LEGSUP) {
 893                 hpet_legacy_clockevent_register();
 894                 return 1;
 895         }
 896         return 0;
 897
 898 out_nohpet:
 899         hpet_clear_mapping();
 900         hpet_address = 0;
 901         return 0;
 902 }
 903
 904 /*
 905  * Needs to be late, as the reserve_timer code calls kalloc !
 906  *
 907  * Not a problem on i386 as hpet_enable is called from late_time_init,
 908  * but on x86_64 it is necessary !
 909  */
 910 static __init int hpet_late_init(void)
 911 {
 912         int cpu;
 913
 914         if (boot_hpet_disable)
 915                 return -ENODEV;
 916
 917         if (!hpet_address) {
 918                 if (!force_hpet_address)
 919                         return -ENODEV;
 920
 921                 hpet_address = force_hpet_address;
 922                 hpet_enable();
 923         }
 924
 925         if (!hpet_virt_address)
 926                 return -ENODEV;
 927
 928         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 929                 hpet_msi_capability_lookup(2);
 930         else
 931                 hpet_msi_capability_lookup(0);
 932
 933         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 934         hpet_print_config();
 935
 936         if (hpet_msi_disable)
 937                 return 0;
 938
 939         if (boot_cpu_has(X86_FEATURE_ARAT))
 940                 return 0;
 941
 942         cpu_notifier_register_begin();
 943         for_each_online_cpu(cpu) {
 944                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 945         }
 946
 947         /* This notifier should be called after workqueue is ready */
 948         __hotcpu_notifier(hpet_cpuhp_notify, -20);
 949         cpu_notifier_register_done();
 950
 951         return 0;
 952 }
 953 fs_initcall(hpet_late_init);
 954
 955 void hpet_disable(void)
 956 {
 957         if (is_hpet_capable() && hpet_virt_address) {
 958                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 959
 960                 if (hpet_boot_cfg)
 961                         cfg = *hpet_boot_cfg;
 962                 else if (hpet_legacy_int_enabled) {
 963                         cfg &= ~HPET_CFG_LEGACY;
 964                         hpet_legacy_int_enabled = 0;
 965                 }
 966                 cfg &= ~HPET_CFG_ENABLE;
 967                 hpet_writel(cfg, HPET_CFG);
 968
 969                 if (!hpet_boot_cfg)
 970                         return;
 971
 972                 id = hpet_readl(HPET_ID);
 973                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 974
 975                 for (id = 0; id <= last; ++id)
 976                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
 977
 978                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
 979                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
 980         }
 981 }
 982
 983 #ifdef CONFIG_HPET_EMULATE_RTC
 984
 985 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 986  * is enabled, we support RTC interrupt functionality in software.
 987  * RTC has 3 kinds of interrupts:
 988  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 989  *    is updated
 990  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 991  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 992  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 993  * (1) and (2) above are implemented using polling at a frequency of
 994  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 995  * overhead. (DEFAULT_RTC_INT_FREQ)
 996  * For (3), we use interrupts at 64Hz or user specified periodic
 997  * frequency, whichever is higher.
 998  */
 999 #include <linux/mc146818rtc.h>
1000 #include <linux/rtc.h>
1001 #include <asm/rtc.h>
1002
1003 #define DEFAULT_RTC_INT_FREQ    64
1004 #define DEFAULT_RTC_SHIFT       6
1005 #define RTC_NUM_INTS            1
1006
1007 static unsigned long hpet_rtc_flags;
1008 static int hpet_prev_update_sec;
1009 static struct rtc_time hpet_alarm_time;
1010 static unsigned long hpet_pie_count;
1011 static u32 hpet_t1_cmp;
1012 static u32 hpet_default_delta;
1013 static u32 hpet_pie_delta;
1014 static unsigned long hpet_pie_limit;
1015
1016 static rtc_irq_handler irq_handler;
1017
1018 /*
1019  * Check that the hpet counter c1 is ahead of the c2
1020  */
1021 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1022 {
1023         return (s32)(c2 - c1) < 0;
1024 }
1025
1026 /*
1027  * Registers a IRQ handler.
1028  */
1029 int hpet_register_irq_handler(rtc_irq_handler handler)
1030 {
1031         if (!is_hpet_enabled())
1032                 return -ENODEV;
1033         if (irq_handler)
1034                 return -EBUSY;
1035
1036         irq_handler = handler;
1037
1038         return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1041
1042 /*
1043  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1044  * and does cleanup.
1045  */
1046 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1047 {
1048         if (!is_hpet_enabled())
1049                 return;
1050
1051         irq_handler = NULL;
1052         hpet_rtc_flags = 0;
1053 }
1054 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1055
1056 /*
1057  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1058  * is not supported by all HPET implementations for timer 1.
1059  *
1060  * hpet_rtc_timer_init() is called when the rtc is initialized.
1061  */
1062 int hpet_rtc_timer_init(void)
1063 {
1064         unsigned int cfg, cnt, delta;
1065         unsigned long flags;
1066
1067         if (!is_hpet_enabled())
1068                 return 0;
1069
1070         if (!hpet_default_delta) {
1071                 uint64_t clc;
1072
1073                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1074                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1075                 hpet_default_delta = clc;
1076         }
1077
1078         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1079                 delta = hpet_default_delta;
1080         else
1081                 delta = hpet_pie_delta;
1082
1083         local_irq_save(flags);
1084
1085         cnt = delta + hpet_readl(HPET_COUNTER);
1086         hpet_writel(cnt, HPET_T1_CMP);
1087         hpet_t1_cmp = cnt;
1088
1089         cfg = hpet_readl(HPET_T1_CFG);
1090         cfg &= ~HPET_TN_PERIODIC;
1091         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1092         hpet_writel(cfg, HPET_T1_CFG);
1093
1094         local_irq_restore(flags);
1095
1096         return 1;
1097 }
1098 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1099
1100 static void hpet_disable_rtc_channel(void)
1101 {
1102         unsigned long cfg;
1103         cfg = hpet_readl(HPET_T1_CFG);
1104         cfg &= ~HPET_TN_ENABLE;
1105         hpet_writel(cfg, HPET_T1_CFG);
1106 }
1107
1108 /*
1109  * The functions below are called from rtc driver.
1110  * Return 0 if HPET is not being used.
1111  * Otherwise do the necessary changes and return 1.
1112  */
1113 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1114 {
1115         if (!is_hpet_enabled())
1116                 return 0;
1117
1118         hpet_rtc_flags &= ~bit_mask;
1119         if (unlikely(!hpet_rtc_flags))
1120                 hpet_disable_rtc_channel();
1121
1122         return 1;
1123 }
1124 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1125
1126 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1127 {
1128         unsigned long oldbits = hpet_rtc_flags;
1129
1130         if (!is_hpet_enabled())
1131                 return 0;
1132
1133         hpet_rtc_flags |= bit_mask;
1134
1135         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1136                 hpet_prev_update_sec = -1;
1137
1138         if (!oldbits)
1139                 hpet_rtc_timer_init();
1140
1141         return 1;
1142 }
1143 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1144
1145 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1146                         unsigned char sec)
1147 {
1148         if (!is_hpet_enabled())
1149                 return 0;
1150
1151         hpet_alarm_time.tm_hour = hrs;
1152         hpet_alarm_time.tm_min = min;
1153         hpet_alarm_time.tm_sec = sec;
1154
1155         return 1;
1156 }
1157 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1158
1159 int hpet_set_periodic_freq(unsigned long freq)
1160 {
1161         uint64_t clc;
1162
1163         if (!is_hpet_enabled())
1164                 return 0;
1165
1166         if (freq <= DEFAULT_RTC_INT_FREQ)
1167                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1168         else {
1169                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1170                 do_div(clc, freq);
1171                 clc >>= hpet_clockevent.shift;
1172                 hpet_pie_delta = clc;
1173                 hpet_pie_limit = 0;
1174         }
1175         return 1;
1176 }
1177 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1178
1179 int hpet_rtc_dropped_irq(void)
1180 {
1181         return is_hpet_enabled();
1182 }
1183 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1184
1185 static void hpet_rtc_timer_reinit(void)
1186 {
1187         unsigned int delta;
1188         int lost_ints = -1;
1189
1190         if (unlikely(!hpet_rtc_flags))
1191                 hpet_disable_rtc_channel();
1192
1193         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1194                 delta = hpet_default_delta;
1195         else
1196                 delta = hpet_pie_delta;
1197
1198         /*
1199          * Increment the comparator value until we are ahead of the
1200          * current count.
1201          */
1202         do {
1203                 hpet_t1_cmp += delta;
1204                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1205                 lost_ints++;
1206         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1207
1208         if (lost_ints) {
1209                 if (hpet_rtc_flags & RTC_PIE)
1210                         hpet_pie_count += lost_ints;
1211                 if (printk_ratelimit())
1212                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1213                                 lost_ints);
1214         }
1215 }
1216
1217 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1218 {
1219         struct rtc_time curr_time;
1220         unsigned long rtc_int_flag = 0;
1221
1222         hpet_rtc_timer_reinit();
1223         memset(&curr_time, 0, sizeof(struct rtc_time));
1224
1225         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1226                 get_rtc_time(&curr_time);
1227
1228         if (hpet_rtc_flags & RTC_UIE &&
1229             curr_time.tm_sec != hpet_prev_update_sec) {
1230                 if (hpet_prev_update_sec >= 0)
1231                         rtc_int_flag = RTC_UF;
1232                 hpet_prev_update_sec = curr_time.tm_sec;
1233         }
1234
1235         if (hpet_rtc_flags & RTC_PIE &&
1236             ++hpet_pie_count >= hpet_pie_limit) {
1237                 rtc_int_flag |= RTC_PF;
1238                 hpet_pie_count = 0;
1239         }
1240
1241         if (hpet_rtc_flags & RTC_AIE &&
1242             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1243             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1244             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1245                         rtc_int_flag |= RTC_AF;
1246
1247         if (rtc_int_flag) {
1248                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1249                 if (irq_handler)
1250                         irq_handler(rtc_int_flag, dev_id);
1251         }
1252         return IRQ_HANDLED;
1253 }
1254 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1255 #endif